summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2007-03-29 00:51:34 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-03-29 00:51:34 -0700
commit14a7cda195db9fcc6accca62bf2b8dfdb2218e0e (patch)
tree3b60f655c35e373597b5002064f1a208280d0440 /src
parent8a674bed5ca845294412f4736f5ac38b42864801 (diff)
parent77ce05f47842606169e7575ef82e65da65bd6c6e (diff)
downloadgem5-14a7cda195db9fcc6accca62bf2b8dfdb2218e0e.tar.xz
Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 849b63ae1300e240082da19dfeb283cdeeb80aef
Diffstat (limited to 'src')
-rwxr-xr-xsrc/arch/isa_parser.py9
-rw-r--r--src/arch/x86/isa/decoder/one_byte_opcodes.isa2
-rw-r--r--src/arch/x86/isa/main.isa3
-rw-r--r--src/arch/x86/isa/microops/microops.isa57
-rw-r--r--src/arch/x86/isa/operands.isa6
5 files changed, 72 insertions, 5 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index f3981a6eb..a0d671da1 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -311,12 +311,19 @@ def p_output_exec(t):
def p_global_let(t):
'global_let : LET CODELIT SEMI'
updateExportContext()
+ exportContext["header_output"] = ''
+ exportContext["decoder_output"] = ''
+ exportContext["exec_output"] = ''
+ exportContext["decode_block"] = ''
try:
exec fixPythonIndentation(t[2]) in exportContext
except Exception, exc:
error(t.lineno(1),
'error: %s in global let block "%s".' % (exc, t[2]))
- t[0] = GenCode() # contributes nothing to the output C++ file
+ t[0] = GenCode(header_output = exportContext["header_output"],
+ decoder_output = exportContext["decoder_output"],
+ exec_output = exportContext["exec_output"],
+ decode_block = exportContext["decode_block"])
# Define the mapping from operand type extensions to C++ types and bit
# widths (stored in operandTypeMap).
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index c56a8bf92..0f030299a 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -64,7 +64,7 @@
0x6: push_ES();
0x7: pop_ES();
default: MultiOp::add(
- {{out1 = in1 + in2}},
+ {{Add op0, op0, op1}},
OPCODE_OP_BOTTOM3,
[[Eb,Gb],[Ev,Gv],
[Gb,Eb],[Gv,Ev],
diff --git a/src/arch/x86/isa/main.isa b/src/arch/x86/isa/main.isa
index 146f714a7..e4103dea0 100644
--- a/src/arch/x86/isa/main.isa
+++ b/src/arch/x86/isa/main.isa
@@ -84,5 +84,8 @@ namespace X86ISA;
//Include the definitions for the instruction formats
##include "formats/formats.isa"
+//Include the definitions of the micro ops
+##include "microops/microops.isa"
+
//Include the decoder definition
##include "decoder/decoder.isa"
diff --git a/src/arch/x86/isa/microops/microops.isa b/src/arch/x86/isa/microops/microops.isa
new file mode 100644
index 000000000..bbf26f605
--- /dev/null
+++ b/src/arch/x86/isa/microops/microops.isa
@@ -0,0 +1,57 @@
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use. Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+// Director of Intellectual Property Licensing
+// Office of Strategy and Technology
+// Hewlett-Packard Company
+// 1501 Page Mill Road
+// Palo Alto, California 94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer. Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution. Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission. No right of
+// sublicense is granted herewith. Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses. Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//Micro ops
+##include "int.isa"
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 20376f38f..36b0ee4df 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -96,7 +96,7 @@ def operand_types {{
}};
def operands {{
- # This is just copied from SPARC, because having no operands confuses
- # the parser.
- 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1)
+ 'IntRegOp0': ('IntReg', 'udw', 'regIndex0', 'IsInteger', 1),
+ 'IntRegOp1': ('IntReg', 'udw', 'regIndex1', 'IsInteger', 2),
+ 'IntRegOp2': ('IntReg', 'udw', 'regIndex2', 'IsInteger', 2),
}};