Fix caches plus sampling switch over.

src/cpu/o3/cpu.cc:
    Fix up caches plus sampling switch over.

--HG--
extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97

2 files changed, 16 insertions, 13 deletions

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index fc65c5d99..d1d25dd7f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -960,7 +960,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
     Port *peer;
     Port *icachePort = fetch.getIcachePort();
     if (icachePort->getPeer() == NULL) {
-        peer = oldCPU->getPort("icachePort")->getPeer();
+        peer = oldCPU->getPort("icache_port")->getPeer();
         icachePort->setPeer(peer);
     } else {
         peer = icachePort->getPeer();
@@ -969,7 +969,7 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 
     Port *dcachePort = iew.getDcachePort();
     if (dcachePort->getPeer() == NULL) {
-        Port *peer = oldCPU->getPort("dcachePort")->getPeer();
+        peer = oldCPU->getPort("dcache_port")->getPeer();
         dcachePort->setPeer(peer);
     } else {
         peer = dcachePort->getPeer();
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 015fdf8bc..9bed5dab1 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -191,9 +191,13 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
         }
     }
 
+    if (_status != Running) {
+        _status = Idle;
+    }
+
     Port *peer;
     if (icachePort.getPeer() == NULL) {
-        peer = oldCPU->getPort("icachePort")->getPeer();
+        peer = oldCPU->getPort("icache_port")->getPeer();
         icachePort.setPeer(peer);
     } else {
         peer = icachePort.getPeer();
@@ -201,7 +205,7 @@ TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
     peer->setPeer(&icachePort);
 
     if (dcachePort.getPeer() == NULL) {
-        peer = oldCPU->getPort("dcachePort")->getPeer();
+        peer = oldCPU->getPort("dcache_port")->getPeer();
         dcachePort.setPeer(peer);
     } else {
         peer = dcachePort.getPeer();
@@ -545,21 +549,20 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
     numCycles += curTick - previousTick;
     previousTick = curTick;
 
-    if (getState() == SimObject::Draining) {
-        completeDrain();
-
-        delete pkt->req;
-        delete pkt;
-
-        return;
-    }
-
     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 
     delete pkt->req;
     delete pkt;
 
     postExecute();
+
+    if (getState() == SimObject::Draining) {
+        advancePC(fault);
+        completeDrain();
+
+        return;
+    }
+
     advanceInst(fault);
 }