ruby: mesi: slight renaming

2 files changed, 37 insertions, 37 deletions

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index 6c98c23e9..080b0c0bb 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -149,7 +149,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   MessageBuffer mandatoryQueue, ordered="false";
 
@@ -208,7 +208,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   AccessPermission getAccessPermission(Address addr) {
-    TBE tbe := L1_TBEs[addr];
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       DPRINTF(RubySlicc, "%s\n", L1Cache_State_to_permission(tbe.TBEState));
       return L1Cache_State_to_permission(tbe.TBEState);
@@ -225,7 +225,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
-    TBE tbe := L1_TBEs[addr];
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
         return tbe.DataBlk;
     }
@@ -290,7 +290,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // cache. We should drop this request.
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Icache_entry, TBEs[in_msg.LineAddress]);
                   }
 
                   // Check to see if it is in the OTHER L1
@@ -300,7 +300,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // this request.
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Dcache_entry, TBEs[in_msg.LineAddress]);
                   }
 
                   if (L1Icache.cacheAvail(in_msg.LineAddress)) {
@@ -308,13 +308,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // in the L1 so let's see if the L2 has it
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Icache_entry, TBEs[in_msg.LineAddress]);
                   } else {
                       // No room in the L1, so we need to make room in the L1
                       trigger(Event:L1_Replacement,
                               L1Icache.cacheProbe(in_msg.LineAddress),
                               getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
-                              L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
+                              TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
                   }
               } else {
                   // Data prefetch
@@ -324,7 +324,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // cache. We should drop this request.
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Dcache_entry, TBEs[in_msg.LineAddress]);
                   }
 
                   // Check to see if it is in the OTHER L1
@@ -334,7 +334,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // request.
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Icache_entry, TBEs[in_msg.LineAddress]);
                   }
 
                   if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
@@ -342,13 +342,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
                       // the L1 let's see if the L2 has it
                       trigger(prefetch_request_type_to_event(in_msg.Type),
                               in_msg.LineAddress,
-                              L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                              L1Dcache_entry, TBEs[in_msg.LineAddress]);
                   } else {
                       // No room in the L1, so we need to make room in the L1
                       trigger(Event:L1_Replacement,
                               L1Dcache.cacheProbe(in_msg.LineAddress),
                               getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
-                              L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
+                              TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
                   }
               }
           }
@@ -362,7 +362,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         assert(in_msg.Destination.isElement(machineID));
 
         Entry cache_entry := getCacheEntry(in_msg.Addr);
-        TBE tbe := L1_TBEs[in_msg.Addr];
+        TBE tbe := TBEs[in_msg.Addr];
 
         if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
           trigger(Event:Data_Exclusive, in_msg.Addr, cache_entry, tbe);
@@ -402,7 +402,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
         assert(in_msg.Destination.isElement(machineID));
 
         Entry cache_entry := getCacheEntry(in_msg.Addr);
-        TBE tbe := L1_TBEs[in_msg.Addr];
+        TBE tbe := TBEs[in_msg.Addr];
 
         if (in_msg.Type == CoherenceRequestType:INV) {
           trigger(Event:Inv, in_msg.Addr, cache_entry, tbe);
@@ -435,7 +435,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
           if (is_valid(L1Icache_entry)) {
             // The tag matches for the L1, so the L1 asks the L2 for it.
             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                    L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                    L1Icache_entry, TBEs[in_msg.LineAddress]);
           } else {
 
             // Check to see if it is in the OTHER L1
@@ -443,19 +443,19 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
             if (is_valid(L1Dcache_entry)) {
               // The block is in the wrong L1, put the request on the queue to the shared L2
               trigger(Event:L1_Replacement, in_msg.LineAddress,
-                      L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                      L1Dcache_entry, TBEs[in_msg.LineAddress]);
             }
 
             if (L1Icache.cacheAvail(in_msg.LineAddress)) {
               // L1 does't have the line, but we have space for it
               // in the L1 so let's see if the L2 has it.
               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                      L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                      L1Icache_entry, TBEs[in_msg.LineAddress]);
             } else {
               // No room in the L1, so we need to make room in the L1
               trigger(Event:L1_Replacement, L1Icache.cacheProbe(in_msg.LineAddress),
                       getL1ICacheEntry(L1Icache.cacheProbe(in_msg.LineAddress)),
-                      L1_TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
+                      TBEs[L1Icache.cacheProbe(in_msg.LineAddress)]);
             }
           }
         } else {
@@ -465,7 +465,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
           if (is_valid(L1Dcache_entry)) {
             // The tag matches for the L1, so the L1 ask the L2 for it
             trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                    L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                    L1Dcache_entry, TBEs[in_msg.LineAddress]);
           } else {
 
             // Check to see if it is in the OTHER L1
@@ -473,19 +473,19 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
             if (is_valid(L1Icache_entry)) {
               // The block is in the wrong L1, put the request on the queue to the shared L2
               trigger(Event:L1_Replacement, in_msg.LineAddress,
-                      L1Icache_entry, L1_TBEs[in_msg.LineAddress]);
+                      L1Icache_entry, TBEs[in_msg.LineAddress]);
             }
 
             if (L1Dcache.cacheAvail(in_msg.LineAddress)) {
               // L1 does't have the line, but we have space for it
               // in the L1 let's see if the L2 has it.
               trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
-                      L1Dcache_entry, L1_TBEs[in_msg.LineAddress]);
+                      L1Dcache_entry, TBEs[in_msg.LineAddress]);
             } else {
               // No room in the L1, so we need to make room in the L1
               trigger(Event:L1_Replacement, L1Dcache.cacheProbe(in_msg.LineAddress),
                       getL1DCacheEntry(L1Dcache.cacheProbe(in_msg.LineAddress)),
-                      L1_TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
+                      TBEs[L1Dcache.cacheProbe(in_msg.LineAddress)]);
             }
           }
         }
@@ -829,10 +829,10 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
-    check_allocate(L1_TBEs);
+    check_allocate(TBEs);
     assert(is_valid(cache_entry));
-    L1_TBEs.allocate(address);
-    set_tbe(L1_TBEs[address]);
+    TBEs.allocate(address);
+    set_tbe(TBEs[address]);
     tbe.isPrefetch := false;
     tbe.Dirty := cache_entry.Dirty;
     tbe.DataBlk := cache_entry.DataBlk;
@@ -853,7 +853,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
   }
 
   action(s_deallocateTBE, "s", desc="Deallocate TBE") {
-    L1_TBEs.deallocate(address);
+    TBEs.deallocate(address);
     unset_tbe();
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index 9e0522ea2..f4809959d 100644
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -146,7 +146,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
+  TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry a);
   void unset_cache_entry();
@@ -196,7 +196,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   AccessPermission getAccessPermission(Address addr) {
-    TBE tbe := L2_TBEs[addr];
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       DPRINTF(RubySlicc, "%s\n", L2Cache_State_to_permission(tbe.TBEState));
       return L2Cache_State_to_permission(tbe.TBEState);
@@ -213,7 +213,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   DataBlock getDataBlock(Address addr), return_by_ref="yes" {
-    TBE tbe := L2_TBEs[addr];
+    TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
         return tbe.DataBlk;
     }
@@ -273,7 +273,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     if(L1unblockNetwork_in.isReady()) {
       peek(L1unblockNetwork_in,  ResponseMsg) {
         Entry cache_entry := getCacheEntry(in_msg.Addr);
-        TBE tbe := L2_TBEs[in_msg.Addr];
+        TBE tbe := TBEs[in_msg.Addr];
         DPRINTF(RubySlicc, "Addr: %s State: %s Sender: %s Type: %s Dest: %s\n",
                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
                 in_msg.Sender, in_msg.Type, in_msg.Destination);
@@ -297,7 +297,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
         // test wether it's from a local L1 or an off chip source
         assert(in_msg.Destination.isElement(machineID));
         Entry cache_entry := getCacheEntry(in_msg.Addr);
-        TBE tbe := L2_TBEs[in_msg.Addr];
+        TBE tbe := TBEs[in_msg.Addr];
 
         if(machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache) {
           if(in_msg.Type == CoherenceResponseType:DATA) {
@@ -336,7 +336,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     if(L1RequestL2Network_in.isReady()) {
       peek(L1RequestL2Network_in,  RequestMsg) {
         Entry cache_entry := getCacheEntry(in_msg.Addr);
-        TBE tbe := L2_TBEs[in_msg.Addr];
+        TBE tbe := TBEs[in_msg.Addr];
 
         DPRINTF(RubySlicc, "Addr: %s State: %s Req: %s Type: %s Dest: %s\n",
                 in_msg.Addr, getState(tbe, cache_entry, in_msg.Addr),
@@ -361,10 +361,10 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
             Entry L2cache_entry := getCacheEntry(L2cache.cacheProbe(in_msg.Addr));
             if (isDirty(L2cache_entry)) {
               trigger(Event:L2_Replacement, L2cache.cacheProbe(in_msg.Addr),
-                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+                      L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]);
             } else {
               trigger(Event:L2_Replacement_clean, L2cache.cacheProbe(in_msg.Addr),
-                      L2cache_entry, L2_TBEs[L2cache.cacheProbe(in_msg.Addr)]);
+                      L2cache_entry, TBEs[L2cache.cacheProbe(in_msg.Addr)]);
             }
           }
         }
@@ -573,10 +573,10 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
 
   // OTHER ACTIONS
   action(i_allocateTBE, "i", desc="Allocate TBE for request") {
-    check_allocate(L2_TBEs);
+    check_allocate(TBEs);
     assert(is_valid(cache_entry));
-    L2_TBEs.allocate(address);
-    set_tbe(L2_TBEs[address]);
+    TBEs.allocate(address);
+    set_tbe(TBEs[address]);
     tbe.L1_GetS_IDs.clear();
     tbe.DataBlk := cache_entry.DataBlk;
     tbe.Dirty := cache_entry.Dirty;
@@ -584,7 +584,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
   }
 
   action(s_deallocateTBE, "s", desc="Deallocate external TBE") {
-    L2_TBEs.deallocate(address);
+    TBEs.deallocate(address);
     unset_tbe();
   }