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authorVincentius Robby <acolyte@umich.edu>2007-08-08 14:18:09 -0400
committerVincentius Robby <acolyte@umich.edu>2007-08-08 14:18:09 -0400
commit13d10e844c7465b4f7375da6e196cd36ffd0e37d (patch)
tree5ce24f04043b232bb7a658884f5e8adbf7f68d2e /src
parentef32494e723283c5a0a8c27bcb657a0e9ca9e25c (diff)
downloadgem5-13d10e844c7465b4f7375da6e196cd36ffd0e37d.tar.xz
alpha: Make the TLB cache to actually work.
Improve MRU checking for StaticInst, Bus, TLB --HG-- extra : convert_revision : 9116b5655cd2986aeb4205438aad4a0f5a440006
Diffstat (limited to 'src')
-rw-r--r--src/arch/alpha/tlb.cc28
-rw-r--r--src/cpu/static_inst.hh27
-rw-r--r--src/mem/bus.hh37
3 files changed, 53 insertions, 39 deletions
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 205b81baf..16aaca54d 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -80,16 +80,21 @@ TLB::lookup(Addr vpn, uint8_t asn) const
// assume not found...
PTE *retval = NULL;
- if (PTECache[0] && vpn == PTECache[0]->tag &&
- (PTECache[0]->asma || PTECache[0]->asn == asn))
- retval = PTECache[0];
- else if (PTECache[1] && vpn == PTECache[1]->tag &&
- (PTECache[1]->asma || PTECache[1]->asn == asn))
- retval = PTECache[1];
- else if (PTECache[2] && vpn == PTECache[2]->tag &&
- (PTECache[2]->asma || PTECache[2]->asn == asn))
- retval = PTECache[2];
- else {
+ if (PTECache[0]) {
+ if (vpn == PTECache[0]->tag &&
+ (PTECache[0]->asma || PTECache[0]->asn == asn))
+ retval = PTECache[0];
+ else if (PTECache[1]) {
+ if (vpn == PTECache[1]->tag &&
+ (PTECache[1]->asma || PTECache[1]->asn == asn))
+ retval = PTECache[1];
+ else if (PTECache[2] && vpn == PTECache[2]->tag &&
+ (PTECache[2]->asma || PTECache[2]->asn == asn))
+ retval = PTECache[2];
+ }
+ }
+
+ if (retval == NULL)
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
while (i->first == vpn) {
@@ -98,6 +103,9 @@ TLB::lookup(Addr vpn, uint8_t asn) const
assert(pte->valid);
if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
retval = pte;
+ PTECache[2] = PTECache[1];
+ PTECache[1] = PTECache[0];
+ PTECache[0] = pte;
break;
}
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 2e1ebd766..c4a29da59 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -597,20 +597,19 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
Addr page_addr = addr & ~(TheISA::PageBytes - 1);
// checks recently decoded addresses
- if (recentDecodes[0].decodePage &&
- page_addr == recentDecodes[0].page_addr) {
- if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
- return recentDecodes[0].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
- }
-
- if (recentDecodes[1].decodePage &&
- page_addr == recentDecodes[1].page_addr) {
- if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
- return recentDecodes[1].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
+ if (recentDecodes[0].decodePage) {
+ if (page_addr == recentDecodes[0].page_addr) {
+ if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
+ return recentDecodes[0].decodePage->getInst(addr);
+
+ return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
+ } else if (recentDecodes[1].decodePage &&
+ page_addr == recentDecodes[1].page_addr) {
+ if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
+ return recentDecodes[1].decodePage->getInst(addr);
+
+ return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
+ }
}
// searches the page containing the address to decode
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index f5cad0586..32a039335 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -193,15 +193,17 @@ class Bus : public MemObject
// Checks the cache and returns the id of the port that has the requested
// address within its range
inline int checkPortCache(Addr addr) {
- if (portCache[0].valid && addr >= portCache[0].start &&
- addr < portCache[0].end) {
- return portCache[0].id;
- } else if (portCache[1].valid && addr >= portCache[1].start &&
- addr < portCache[1].end) {
- return portCache[1].id;
- } else if (portCache[2].valid && addr >= portCache[2].start &&
- addr < portCache[2].end) {
- return portCache[2].id;
+ if (portCache[0].valid) {
+ if (addr >= portCache[0].start && addr < portCache[0].end) {
+ return portCache[0].id;
+ } else if (portCache[1].valid) {
+ if (addr >= portCache[1].start && addr < portCache[1].end) {
+ return portCache[1].id;
+ } else if (portCache[2].valid && addr >= portCache[2].start &&
+ addr < portCache[2].end) {
+ return portCache[2].id;
+ }
+ }
}
return -1;
@@ -310,12 +312,17 @@ class Bus : public MemObject
// Checks the peer port interfaces cache for the port id and returns
// a pointer to the matching port
inline BusPort* checkBusCache(short id) {
- if (busCache[0].valid && id == busCache[0].id) {
- return busCache[0].port;
- } else if (busCache[1].valid && id == busCache[1].id) {
- return busCache[1].port;
- } else if (busCache[2].valid && id == busCache[2].id) {
- return busCache[2].port;
+ if (busCache[0].valid) {
+ if (id == busCache[0].id) {
+ return busCache[0].port;
+ if (busCache[1].valid) {
+ if (id == busCache[1].id) {
+ return busCache[1].port;
+ if (busCache[2].valid && id == busCache[2].id)
+ return busCache[2].port;
+ }
+ }
+ }
}
return NULL;