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author | Gabe Black <gblack@eecs.umich.edu> | 2006-11-08 00:32:40 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-11-08 00:32:40 -0500 |
commit | 16a012e80da8beb2e147bf62ed0d054ed1c0d600 (patch) | |
tree | dc2a475e62232cf5772f3f81fd6979cb11076a4e /src | |
parent | 746ceb93fdb13f74ea2e18f980d122f8bfb5cd0a (diff) | |
download | gem5-16a012e80da8beb2e147bf62ed0d054ed1c0d600.tar.xz |
Stubs for SPARC's tlbs
--HG--
extra : convert_revision : ba08da78693cc6f59f7358134f121f471910dbf6
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/sparc/tlb.cc | 79 | ||||
-rw-r--r-- | src/arch/sparc/tlb.hh | 16 |
2 files changed, 94 insertions, 1 deletions
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc new file mode 100644 index 000000000..0b1a2ff5f --- /dev/null +++ b/src/arch/sparc/tlb.cc @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2001-2005 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Nathan Binkert + * Steve Reinhardt + * Andrew Schultz + */ + +#include "arch/sparc/tlb.hh" +#include "sim/builder.hh" + +namespace SparcISA +{ + DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) + + BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) + + Param<int> size; + + END_DECLARE_SIM_OBJECT_PARAMS(ITB) + + BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) + + INIT_PARAM_DFLT(size, "TLB size", 48) + + END_INIT_SIM_OBJECT_PARAMS(ITB) + + + CREATE_SIM_OBJECT(ITB) + { + return new ITB(getInstanceName(), size); + } + + REGISTER_SIM_OBJECT("SparcITB", ITB) + + BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) + + Param<int> size; + + END_DECLARE_SIM_OBJECT_PARAMS(DTB) + + BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) + + INIT_PARAM_DFLT(size, "TLB size", 64) + + END_INIT_SIM_OBJECT_PARAMS(DTB) + + + CREATE_SIM_OBJECT(DTB) + { + return new DTB(getInstanceName(), size); + } + + REGISTER_SIM_OBJECT("SparcDTB", DTB) +} diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index 0d42e2c97..0fdba6baf 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -31,19 +31,29 @@ #ifndef __ARCH_SPARC_TLB_HH__ #define __ARCH_SPARC_TLB_HH__ +#include "mem/request.hh" #include "sim/faults.hh" +#include "sim/sim_object.hh" class ThreadContext; namespace SparcISA { - class TLB + class TLB : public SimObject { + public: + TLB(const std::string &name, int size) : SimObject(name) + { + } }; class ITB : public TLB { public: + ITB(const std::string &name, int size) : TLB(name, size) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc) const { return NoFault; @@ -53,6 +63,10 @@ namespace SparcISA class DTB : public TLB { public: + DTB(const std::string &name, int size) : TLB(name, size) + { + } + Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const { return NoFault; |