diff options
| author | Gabe Black <gabeblack@google.com> | 2017-11-04 03:45:23 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2017-11-07 01:31:24 +0000 |
| commit | 344911b885114b8401482679202aaee89fa8b29b (patch) | |
| tree | 395424b6f248c24977462489c8c1e3c1e97e7c34 /src | |
| parent | 7e02ab1dc622081a30e5b8bec3a944bd1fc7fca6 (diff) | |
| download | gem5-344911b885114b8401482679202aaee89fa8b29b.tar.xz | |
alpha,arm,mips,power,riscv,sparc,x86: Merge exec decl templates.
In the ISA instruction definitions, some classes were declared with
execute, etc., functions outside of the main template because they
had CPU specific signatures and would need to be duplicated with
each CPU plugged into them. Now that the instructions always just
use an ExecContext, there's no reason for those templates to be
separate. This change folds those templates together.
Change-Id: I13bda247d3d1cc07c0ea06968e48aa5b4aace7fa
Reviewed-on: https://gem5-review.googlesource.com/5401
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Alec Roelke <ar4jc@virginia.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
62 files changed, 453 insertions, 727 deletions
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index a6c9afe88..a23710a2d 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -285,11 +285,6 @@ output decoder {{ } }}; -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -301,7 +296,7 @@ def template BasicDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -383,7 +378,7 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; /// Helper function for decoding nops. Substitute Nop object diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index 5c76c263e..6756b7258 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -129,30 +129,13 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; - -def template EACompDeclare {{ - Fault eaComp(ExecContext *, Trace::InstRecord *) const; -}}; - -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - def template LoadStoreConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa index 3ea56573a..3bd3835a1 100644 --- a/src/arch/alpha/isa/opcdec.isa +++ b/src/arch/alpha/isa/opcdec.isa @@ -48,7 +48,7 @@ output header {{ { } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa index 0446707bb..39f177663 100644 --- a/src/arch/alpha/isa/unimp.isa +++ b/src/arch/alpha/isa/unimp.isa @@ -53,7 +53,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -84,7 +84,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -163,7 +163,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh index 09ebbb120..b4186c8e5 100644 --- a/src/arch/arm/insts/pred_inst.hh +++ b/src/arch/arm/insts/pred_inst.hh @@ -333,6 +333,12 @@ class PredMacroOp : public PredOp return microOps[microPC]; } + Fault + execute(ExecContext *, Trace::InstRecord *) const + { + panic("Execute method called when it shouldn't!"); + } + std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; }; diff --git a/src/arch/arm/isa/formats/breakpoint.isa b/src/arch/arm/isa/formats/breakpoint.isa index 69d6855e3..a22f2de7a 100644 --- a/src/arch/arm/isa/formats/breakpoint.isa +++ b/src/arch/arm/isa/formats/breakpoint.isa @@ -63,7 +63,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa index dff906755..dcf5889fb 100644 --- a/src/arch/arm/isa/insts/fp.isa +++ b/src/arch/arm/isa/insts/fp.isa @@ -60,8 +60,6 @@ class VfpMacroRegRegOp : public VfpMacroOp nextIdxs(_dest, _op1); } } - - %(BasicExecPanic)s }; template <class VfpOp> @@ -96,8 +94,6 @@ class VfpMacroRegImmOp : public VfpMacroOp nextIdxs(_dest); } } - - %(BasicExecPanic)s }; template <class VfpOp> @@ -132,8 +128,6 @@ class VfpMacroRegRegImmOp : public VfpMacroOp nextIdxs(_dest, _op1); } } - - %(BasicExecPanic)s }; template <class VfpOp> @@ -168,8 +162,6 @@ class VfpMacroRegRegRegOp : public VfpMacroOp nextIdxs(_dest, _op1, _op2); } } - - %(BasicExecPanic)s }; template <class VfpOp> diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa index c4c570bbe..ebfddb0a6 100644 --- a/src/arch/arm/isa/templates/basic.isa +++ b/src/arch/arm/isa/templates/basic.isa @@ -40,11 +40,6 @@ // // Authors: Stephen Hines -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -55,7 +50,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -108,13 +103,3 @@ def template BasicDecode {{ def template BasicDecodeWithMnemonic {{ return new %(class_name)s("%(mnemonic)s", machInst); }}; - -// Definitions of execute methods that panic. -def template BasicExecPanic {{ -Fault execute(ExecContext *, Trace::InstRecord *) const -{ - panic("Execute method called when it shouldn't!"); - // GCC < 4.3 fail to recognize the above panic as no return - return NoFault; -} -}}; diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa index 92c566726..54821e7c8 100644 --- a/src/arch/arm/isa/templates/branch.isa +++ b/src/arch/arm/isa/templates/branch.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; /// Explicitly import the otherwise hidden branchTarget @@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -135,7 +135,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -167,7 +167,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -178,11 +178,9 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -211,7 +209,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; /// Explicitly import the otherwise hidden branchTarget diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa index 241d12260..c55d20541 100644 --- a/src/arch/arm/isa/templates/branch64.isa +++ b/src/arch/arm/isa/templates/branch64.isa @@ -43,7 +43,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -63,7 +63,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -84,7 +84,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -125,7 +125,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa index 7b0438a01..85dde6bed 100644 --- a/src/arch/arm/isa/templates/data64.isa +++ b/src/arch/arm/isa/templates/data64.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -68,7 +68,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -94,7 +94,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ArmExtendType _extendType, int32_t _shiftAmt); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -163,7 +163,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -187,7 +187,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -211,7 +211,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, uint8_t _defCc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -236,7 +236,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -261,7 +261,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa index 05acb52eb..b0e3d29fd 100644 --- a/src/arch/arm/isa/templates/macromem.isa +++ b/src/arch/arm/isa/templates/macromem.isa @@ -53,9 +53,9 @@ def template MicroMemDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -85,9 +85,9 @@ def template MicroMemPairDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -134,9 +134,9 @@ def template MicroNeonMemDeclare {{ } } - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -154,7 +154,7 @@ def template MicroSetPCCPSRDeclare {{ IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -189,7 +189,7 @@ def template MicroIntDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -251,7 +251,7 @@ def template MicroNeonMixDeclare {{ } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -304,7 +304,7 @@ def template MicroNeonMixLaneDeclare {{ } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -319,7 +319,7 @@ def template MicroIntMovDeclare {{ public: %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; def template MicroIntMovConstructor {{ @@ -350,7 +350,7 @@ def template MicroIntImmDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, int32_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -390,7 +390,7 @@ def template MicroIntRegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -412,7 +412,7 @@ def template MicroIntXERegDeclare {{ %(class_name)s(ExtMachInst machInst, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -448,7 +448,6 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex rn, bool index, bool up, bool user, bool writeback, bool load, uint32_t reglist); - %(BasicExecPanic)s }; }}; @@ -476,7 +475,6 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm); - %(BasicExecPanic)s }; }}; @@ -497,7 +495,6 @@ class %(class_name)s : public %(base_class)s %(class_name)s(const char *mnemonic, ExtMachInst machInst, bool load, IntRegIndex dest, IntRegIndex base, IntRegIndex offset, ArmExtendType type, int64_t imm); - %(BasicExecPanic)s }; }}; @@ -519,7 +516,6 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(const char *mnemonic, ExtMachInst machInst, IntRegIndex dest, int64_t imm); - %(BasicExecPanic)s }; }}; @@ -542,7 +538,6 @@ class %(class_name)s : public %(base_class)s bool exclusive, bool acrel, uint32_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2); - %(BasicExecPanic)s }; }}; @@ -567,7 +562,6 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, unsigned width, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm); - %(BasicExecPanic)s }; }}; @@ -595,7 +589,6 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, bool all, unsigned width, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane = 0); - %(BasicExecPanic)s }; }}; @@ -626,7 +619,6 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset); - %(BasicExecPanic)s }; }}; diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index 44f6ea797..38f5d2051 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -582,11 +582,9 @@ def template RfeDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -602,11 +600,9 @@ def template SrsDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -622,11 +618,9 @@ def template SwapDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -643,11 +637,9 @@ def template LoadStoreDImmDeclare {{ uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -664,11 +656,9 @@ def template StoreExDImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -684,11 +674,9 @@ def template LoadStoreImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -710,11 +698,9 @@ def template StoreExImmDeclare {{ uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -733,11 +719,9 @@ def template StoreDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -755,11 +739,9 @@ def template StoreRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -783,11 +765,9 @@ def template LoadDRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -805,11 +785,9 @@ def template LoadRegDeclare {{ int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -830,11 +808,9 @@ def template LoadImmDeclare {{ %(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -843,14 +819,6 @@ def template LoadImmDeclare {{ }; }}; -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - def template RfeConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb) diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index fc922b330..ff4114898 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -258,9 +258,9 @@ def template DCStore64Declare {{ /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _base, IntRegIndex _dest, uint64_t _imm); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -340,9 +340,9 @@ def template LoadStoreImm64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, int64_t _imm); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -362,9 +362,9 @@ def template LoadStoreImmU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -384,9 +384,9 @@ def template LoadStoreImmDU64Declare {{ int64_t _imm = 0, bool noAlloc = false, bool exclusive = false, bool acrel = false); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -408,11 +408,9 @@ def template StoreImmDEx64Declare {{ IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm = 0); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -427,9 +425,9 @@ def template LoadStoreReg64Declare {{ IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset, ArmExtendType _type, uint32_t _shiftAmt); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -450,9 +448,9 @@ def template LoadStoreRegU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -470,9 +468,9 @@ def template LoadStoreRaw64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -490,9 +488,9 @@ def template LoadStoreEx64Declare {{ %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -509,9 +507,9 @@ def template LoadStoreLit64Declare {{ /// Constructor. %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { @@ -530,9 +528,9 @@ def template LoadStoreLitU64Declare {{ bool noAlloc = false, bool exclusive = false, bool acrel = false); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; virtual void annotateFault(ArmFault *fault) { diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa index d661b4f18..0a23ba5d3 100644 --- a/src/arch/arm/isa/templates/misc.isa +++ b/src/arch/arm/isa/templates/misc.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _sysM, bool _r); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -104,7 +104,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t _sysM, bool _r); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -158,7 +158,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -185,7 +185,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -215,7 +215,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest, uint32_t imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -244,7 +244,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -268,7 +268,7 @@ class %(class_name)s : public %(base_class)s public: // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -294,7 +294,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -321,7 +321,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -352,7 +352,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -382,7 +382,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -412,7 +412,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -442,7 +442,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -472,7 +472,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -501,7 +501,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -531,7 +531,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -561,7 +561,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -591,7 +591,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, int32_t _shiftAmt, ArmShiftType _shiftType); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa index 3ccb3dc17..842997902 100644 --- a/src/arch/arm/isa/templates/misc64.isa +++ b/src/arch/arm/isa/templates/misc64.isa @@ -46,7 +46,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -72,7 +72,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa index 0099e5c9d..87d96f743 100644 --- a/src/arch/arm/isa/templates/mult.isa +++ b/src/arch/arm/isa/templates/mult.isa @@ -44,7 +44,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -73,7 +73,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2, IntRegIndex _reg3); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa index c1ec74135..5cde08dcf 100644 --- a/src/arch/arm/isa/templates/neon.isa +++ b/src/arch/arm/isa/templates/neon.isa @@ -71,7 +71,7 @@ class %(class_name)s : public %(base_class)s } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -97,7 +97,7 @@ class %(class_name)s : public %(base_class)s } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -122,7 +122,7 @@ class %(class_name)s : public %(base_class)s } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -145,7 +145,7 @@ class %(class_name)s : public %(base_class)s } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -170,7 +170,7 @@ class %(class_name)s : public %(base_class)s } } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa index f11ee91d4..153933611 100644 --- a/src/arch/arm/isa/templates/neon64.isa +++ b/src/arch/arm/isa/templates/neon64.isa @@ -58,7 +58,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -79,7 +79,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -99,7 +99,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -119,7 +119,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -140,7 +140,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -160,7 +160,7 @@ class %(class_name)s : public %(base_class)s %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -267,9 +267,9 @@ def template MicroNeonMemDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -420,7 +420,6 @@ def template VMemMultDeclare64 {{ %(class_name)s(ExtMachInst machInst, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb); - %(BasicExecPanic)s }; }}; @@ -433,7 +432,6 @@ def template VMemSingleDeclare64 {{ RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate = false); - %(BasicExecPanic)s }; }}; @@ -479,7 +477,7 @@ def template MicroNeonMixDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -498,7 +496,7 @@ def template MicroNeonMixLaneDeclare64 {{ %(constructor)s; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa index fb0a404cb..d2060a7cd 100644 --- a/src/arch/arm/isa/templates/pred.isa +++ b/src/arch/arm/isa/templates/pred.isa @@ -57,7 +57,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC=true); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -96,7 +96,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, int32_t _shiftAmt, ArmShiftType _shiftType); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -141,7 +141,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift, ArmShiftType _shiftType); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa index d94f4652a..c5765f21e 100644 --- a/src/arch/arm/isa/templates/vfp.isa +++ b/src/arch/arm/isa/templates/vfp.isa @@ -105,7 +105,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -132,7 +132,7 @@ class %(class_name)s : public %(base_class)s // Constructor %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -159,7 +159,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -189,7 +189,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -220,7 +220,7 @@ class %(class_name)s : public %(base_class)s IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _cond, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa index ea76472f5..64932336f 100644 --- a/src/arch/arm/isa/templates/vfp64.isa +++ b/src/arch/arm/isa/templates/vfp64.isa @@ -92,7 +92,7 @@ class %(class_name)s : public %(base_class)s %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa index 7431b94f5..b824fda18 100644 --- a/src/arch/mips/isa/formats/basic.isa +++ b/src/arch/mips/isa/formats/basic.isa @@ -31,11 +31,6 @@ // Authors: Steve Reinhardt // Korey Sewell -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -46,7 +41,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 9e5f538e6..671c7643d 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -142,28 +142,13 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; }; }}; -def template EACompDeclare {{ - Fault eaComp(ExecContext *, Trace::InstRecord *) const; -}}; - -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; -}}; def template LoadStoreConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa index 17c653f14..f33c1130c 100644 --- a/src/arch/mips/isa/formats/noop.isa +++ b/src/arch/mips/isa/formats/noop.isa @@ -56,7 +56,7 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa index 6f573b667..fb0051b4f 100644 --- a/src/arch/mips/isa/formats/unimp.isa +++ b/src/arch/mips/isa/formats/unimp.isa @@ -53,7 +53,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -70,7 +70,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -87,7 +87,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -104,7 +104,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -135,7 +135,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa index fb29eea4b..65fd18f7a 100644 --- a/src/arch/mips/isa/formats/unknown.isa +++ b/src/arch/mips/isa/formats/unknown.isa @@ -51,7 +51,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/power/isa/formats/basic.isa b/src/arch/power/isa/formats/basic.isa index e1885fa1b..8adce1c7b 100644 --- a/src/arch/power/isa/formats/basic.isa +++ b/src/arch/power/isa/formats/basic.isa @@ -28,11 +28,6 @@ // // Authors: Timothy M. Jones -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -43,7 +38,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -86,14 +81,6 @@ def template BasicDecodeWithMnemonic {{ return new %(class_name)s("%(mnemonic)s", machInst); }}; -// Definitions of execute methods that panic. -def template BasicExecPanic {{ -Fault execute(ExecContext *, Trace::InstRecord *) const -{ - panic("Execute method called when it shouldn't!"); -} -}}; - // The most basic instruction format... def format BasicOp(code, *flags) {{ iop = InstObjParams(name, Name, 'PowerStaticInst', code, flags) diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index ca2d404f8..8f89bc208 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -44,25 +44,13 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - - def template LoadStoreConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa index 241e6218b..f9af7f0fc 100644 --- a/src/arch/power/isa/formats/unimp.isa +++ b/src/arch/power/isa/formats/unimp.isa @@ -55,7 +55,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -86,7 +86,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa index 9f08bc1ee..f8cd3bf43 100644 --- a/src/arch/power/isa/formats/unknown.isa +++ b/src/arch/power/isa/formats/unknown.isa @@ -53,7 +53,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/riscv/isa/base.isa b/src/arch/riscv/isa/base.isa deleted file mode 100644 index d54d7940b..000000000 --- a/src/arch/riscv/isa/base.isa +++ /dev/null @@ -1,63 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2015 RISC-V Foundation -// Copyright (c) 2016 The University of Virginia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Maxwell Walter -// Alec Roelke - -//////////////////////////////////////////////////////////////////// -// -// Base class for Riscv instructions, and some support functions -// - -//Outputs to decoder.hh -output header {{ - using namespace RiscvISA; - - /** - * Base class for all RISC-V static instructions. - */ - class RiscvStaticInst : public StaticInst - { - protected: - // Constructor - RiscvStaticInst(const char *mnem, MachInst _machInst, - OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) - {} - - virtual std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; - - public: - void - advancePC(RiscvISA::PCState &pc) const - { - pc.advance(); - } - }; -}}; diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index 983c1f4cc..80a5faa19 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -148,13 +148,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sLoad(ExtMachInst machInst, %(class_name)s *_p); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)sStore : public %(base_class)sMicro @@ -163,13 +161,11 @@ def template AtomicMemOpDeclare {{ // Constructor %(class_name)sStore(ExtMachInst machInst, %(class_name)s *_p); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; }; }}; diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa index 2d27fd8b5..bb8401e3d 100644 --- a/src/arch/riscv/isa/formats/basic.isa +++ b/src/arch/riscv/isa/formats/basic.isa @@ -30,11 +30,6 @@ // Authors: Maxwell Walter // Alec Roelke -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ // @@ -45,7 +40,7 @@ def template BasicDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; using %(base_class)s::generateDisassembly; }; }}; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index 5f469dc8d..bce76c4d5 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -109,31 +109,13 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; -def template EACompDeclare {{ - Fault - eaComp(ExecContext *, Trace::InstRecord *) const; -}}; - -def template InitiateAccDeclare {{ - Fault - initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - - -def template CompleteAccDeclare {{ - Fault - completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; def template LoadStoreConstructor {{ %(class_name)s::%(class_name)s(ExtMachInst machInst): diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa index 70d6ada33..35c3fa878 100644 --- a/src/arch/riscv/isa/formats/standard.isa +++ b/src/arch/riscv/isa/formats/standard.isa @@ -184,7 +184,7 @@ def template ImmDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; }; @@ -240,7 +240,7 @@ def template BranchDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; @@ -299,7 +299,7 @@ def template JumpDeclare {{ public: /// Constructor. %(class_name)s(MachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const override; diff --git a/src/arch/riscv/isa/formats/unknown.isa b/src/arch/riscv/isa/formats/unknown.isa index aaab21137..b6d76497d 100644 --- a/src/arch/riscv/isa/formats/unknown.isa +++ b/src/arch/riscv/isa/formats/unknown.isa @@ -51,7 +51,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa index 82d1794fd..c172d0300 100644 --- a/src/arch/riscv/isa/includes.isa +++ b/src/arch/riscv/isa/includes.isa @@ -42,6 +42,7 @@ output header {{ #include <tuple> #include <vector> +#include "arch/riscv/static_inst.hh" #include "cpu/static_inst.hh" #include "mem/packet.hh" #include "mem/request.hh" diff --git a/src/arch/riscv/isa/main.isa b/src/arch/riscv/isa/main.isa index 58ec22341..3ffb3e6b4 100644 --- a/src/arch/riscv/isa/main.isa +++ b/src/arch/riscv/isa/main.isa @@ -53,12 +53,6 @@ namespace RiscvISA; //Include the operand_types and operand definitions ##include "operands.isa" -//Include the base class for riscv instructions, and some support code -##include "base.isa" - -// Include the base class for instructions with micro code -##include "micro.isa" - //Include the definitions for the instruction formats ##include "formats/formats.isa" diff --git a/src/arch/riscv/isa/micro.isa b/src/arch/riscv/isa/micro.isa deleted file mode 100644 index 61be076b0..000000000 --- a/src/arch/riscv/isa/micro.isa +++ /dev/null @@ -1,114 +0,0 @@ -// -*- mode:c++ -*- - -// Copyright (c) 2015 Riscv Developers -// Copyright (c) 2016 The University of Virginia -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are -// met: redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer; -// redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution; -// neither the name of the copyright holders nor the names of its -// contributors may be used to endorse or promote products derived from -// this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -// Authors: Alec Roelke - -def template MacroInitiateAcc {{ - Fault initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -def template MacroCompleteAcc {{ - Fault completeAcc(PacketPtr pkt, ExecContext *xc, - Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -def template MacroExecute {{ - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -output header {{ - /** - * Base class for all RISC-V Macroops - */ - class RiscvMacroInst : public RiscvStaticInst - { - protected: - std::vector<StaticInstPtr> microops; - - // Constructor - RiscvMacroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMacroop] = true; - } - - ~RiscvMacroInst() - { - microops.clear(); - } - - StaticInstPtr fetchMicroop(MicroPC upc) const - { - return microops[upc]; - } - - %(MacroInitiateAcc)s - - %(MacroCompleteAcc)s - - %(MacroExecute)s - }; - - /** - * Base class for all RISC-V Microops - */ - class RiscvMicroInst : public RiscvStaticInst - { - protected: - // Constructor - RiscvMicroInst(const char *mnem, ExtMachInst _machInst, - OpClass __opClass) - : RiscvStaticInst(mnem, _machInst, __opClass) - { - flags[IsMicroop] = true; - } - - void advancePC(RiscvISA::PCState &pcState) const - { - if (flags[IsLastMicroop]) { - pcState.uEnd(); - } else { - pcState.uAdvance(); - } - } - }; -}}; diff --git a/src/arch/riscv/static_inst.hh b/src/arch/riscv/static_inst.hh new file mode 100644 index 000000000..bdcdee74a --- /dev/null +++ b/src/arch/riscv/static_inst.hh @@ -0,0 +1,139 @@ +// -*- mode:c++ -*- + +// Copyright (c) 2015 RISC-V Foundation +// Copyright (c) 2016 The University of Virginia +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer; +// redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution; +// neither the name of the copyright holders nor the names of its +// contributors may be used to endorse or promote products derived from +// this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// Authors: Maxwell Walter +// Alec Roelke + +#ifndef __ARCH_RISCV_STATIC_INST_HH__ +#define __ARCH_RISCV_STATIC_INST_HH__ + +//////////////////////////////////////////////////////////////////// +// +// Base class for Riscv instructions, and some support functions +// + +namespace RiscvISA { + +/** + * Base class for all RISC-V static instructions. + */ +class RiscvStaticInst : public StaticInst +{ + protected: + // Constructor + RiscvStaticInst(const char *mnem, MachInst _machInst, + OpClass __opClass) : StaticInst(mnem, _machInst, __opClass) + {} + + virtual std::string + generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0; + + public: + void + advancePC(RiscvISA::PCState &pc) const + { + pc.advance(); + } +}; + +/** + * Base class for all RISC-V Macroops + */ +class RiscvMacroInst : public RiscvStaticInst +{ + protected: + std::vector<StaticInstPtr> microops; + + // Constructor + RiscvMacroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMacroop] = true; + } + + ~RiscvMacroInst() + { + microops.clear(); + } + + StaticInstPtr + fetchMicroop(MicroPC upc) const + { + return microops[upc]; + } + + Fault + initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + completeAcc(PacketPtr pkt, ExecContext *xc, + Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + execute(ExecContext *xc, Trace::InstRecord *traceData) const + { + panic("Tried to execute a macroop directly!\n"); + } +}; + +/** + * Base class for all RISC-V Microops + */ +class RiscvMicroInst : public RiscvStaticInst +{ + protected: + // Constructor + RiscvMicroInst(const char *mnem, ExtMachInst _machInst, + OpClass __opClass) : + RiscvStaticInst(mnem, _machInst, __opClass) + { + flags[IsMicroop] = true; + } + + void + advancePC(RiscvISA::PCState &pcState) const + { + if (flags[IsLastMicroop]) { + pcState.uEnd(); + } else { + pcState.uAdvance(); + } + } +}; + +} + +#endif // __ARCH_RISCV_STATIC_INST_HH__ diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa index a81de05ad..63f3e4a6c 100644 --- a/src/arch/sparc/isa/formats/basic.isa +++ b/src/arch/sparc/isa/formats/basic.isa @@ -28,26 +28,6 @@ // Gabe Black // Steve Reinhardt -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - -def template DoFpOpDeclare {{ - Fault doFpOp(ExecContext *, Trace::InstRecord *) - const M5_NO_INLINE; -}}; - -// Definitions of execute methods that panic. -def template BasicExecPanic {{ - Fault - execute(ExecContext *, Trace::InstRecord *) const - { - panic("Execute method called when it shouldn't!"); - M5_DUMMY_RETURN - } -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -58,7 +38,7 @@ def template BasicDeclare {{ public: // Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -72,8 +52,9 @@ def template FpBasicDeclare {{ public: // Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - %(DoFpOpDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault doFpOp(ExecContext *, + Trace::InstRecord *) const M5_NO_INLINE; }; }}; @@ -87,7 +68,7 @@ def template BasicDeclareWithMnemonic {{ public: // Constructor. %(class_name)s(const char * mnemonic, ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa index 5dcb955e3..391063cf8 100644 --- a/src/arch/sparc/isa/formats/mem/basicmem.isa +++ b/src/arch/sparc/isa/formats/mem/basicmem.isa @@ -45,13 +45,11 @@ def template MemDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s - - %(EACompDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; }}; diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa index 03b395b12..3e3aabfcb 100644 --- a/src/arch/sparc/isa/formats/mem/blockmem.isa +++ b/src/arch/sparc/isa/formats/mem/blockmem.isa @@ -161,9 +161,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_0(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_1 : public %(base_class)sMicro @@ -171,9 +172,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_1(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_2 : public %(base_class)sMicro @@ -181,9 +183,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_2(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_3 : public %(base_class)sMicro @@ -191,9 +194,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_3(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_4 : public %(base_class)sMicro @@ -201,9 +205,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_4(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_5 : public %(base_class)sMicro @@ -211,9 +216,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_5(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_6 : public %(base_class)sMicro @@ -221,9 +227,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_6(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; class %(class_name)s_7 : public %(base_class)sMicro @@ -231,9 +238,10 @@ def template BlockMemDeclare {{ public: // Constructor %(class_name)s_7(ExtMachInst machInst); - %(BasicExecDeclare)s - %(InitiateAccDeclare)s - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const; }; }; }}; diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index ff14f060f..4d7fc0608 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -280,15 +280,6 @@ def template EACompExecute {{ } }}; -def template EACompDeclare {{ - Fault eaComp(ExecContext *, Trace::InstRecord *) const; -}}; - -// This delcares the initiateAcc function in memory operations -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - // This declares the completeAcc function in memory operations def template CompleteAccDeclare {{ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; diff --git a/src/arch/sparc/isa/formats/micro.isa b/src/arch/sparc/isa/formats/micro.isa index c57d9346d..f9c4ebd6c 100644 --- a/src/arch/sparc/isa/formats/micro.isa +++ b/src/arch/sparc/isa/formats/micro.isa @@ -26,35 +26,6 @@ // // Authors: Gabe Black -// This delcares the initiateAcc function in memory operations -def template MacroInitiateAcc {{ - Fault - initiateAcc(ExecContext *, Trace::InstRecord *) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -def template MacroCompleteAcc {{ - Fault - completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - -// This template provides the execute functions for a store -def template MacroExecute {{ - Fault - execute(ExecContext *, Trace::InstRecord *) const - { - panic("Tried to execute a macroop directly!\n"); - return NoFault; - } -}}; - output header {{ class SparcMacroInst : public SparcStaticInst @@ -90,9 +61,23 @@ output header {{ return microops[upc]; } - %(MacroExecute)s - %(MacroInitiateAcc)s - %(MacroCompleteAcc)s + Fault + execute(ExecContext *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + initiateAcc(ExecContext *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + } + + Fault + completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const + { + panic("Tried to execute a macroop directly!\n"); + } }; class SparcMicroInst : public SparcStaticInst diff --git a/src/arch/sparc/isa/formats/nop.isa b/src/arch/sparc/isa/formats/nop.isa index e725f49b0..d1257907f 100644 --- a/src/arch/sparc/isa/formats/nop.isa +++ b/src/arch/sparc/isa/formats/nop.isa @@ -34,12 +34,6 @@ // Per-cpu-model nop execute method. def template NopExec {{ - - Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const - { - // Nothing to see here, move along - return NoFault; - } }}; output header {{ @@ -56,12 +50,11 @@ output header {{ flags[IsNop] = true; } - // All Nop instructions do the same thing, so this can be - // defined here. Nops can be defined directly, so there - // needs to be a default implementation. Interpolate via - // template so i gets expanded to a set of - // cpu-model-specific functions. - %(NopExec)s + Fault + execute(ExecContext *xc, Trace::InstRecord *traceData) const + { + return NoFault; + } std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/sparc/isa/formats/unimp.isa b/src/arch/sparc/isa/formats/unimp.isa index f612b8bc6..aa03c926e 100644 --- a/src/arch/sparc/isa/formats/unimp.isa +++ b/src/arch/sparc/isa/formats/unimp.isa @@ -53,7 +53,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -84,7 +84,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/sparc/isa/formats/unknown.isa b/src/arch/sparc/isa/formats/unknown.isa index 226f0191e..f6f9e878b 100644 --- a/src/arch/sparc/isa/formats/unknown.isa +++ b/src/arch/sparc/isa/formats/unknown.isa @@ -46,7 +46,7 @@ output header {{ { } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa index af540962b..2542df8c3 100644 --- a/src/arch/x86/isa/formats/basic.isa +++ b/src/arch/x86/isa/formats/basic.isa @@ -38,20 +38,6 @@ // // Authors: Gabe Black -// Declarations for execute() methods. -def template BasicExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; -}}; - -// Definitions of execute methods that panic. -def template BasicExecPanic {{ - Fault execute(ExecContext *, Trace::InstRecord *) const - { - panic("Execute method called when it shouldn't!"); - M5_DUMMY_RETURN - } -}}; - // Basic instruction class declaration template. def template BasicDeclare {{ /** @@ -62,7 +48,7 @@ def template BasicDeclare {{ public: // Constructor. %(class_name)s(ExtMachInst machInst); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa index 5e68b8738..9ceb129a6 100644 --- a/src/arch/x86/isa/formats/monitor_mwait.isa +++ b/src/arch/x86/isa/formats/monitor_mwait.isa @@ -45,20 +45,15 @@ def format MonitorInst(code, *opt_flags) {{ // Mwait instruction -// Declarations for execute() methods. -def template MwaitExecDeclare {{ - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - def template MwaitDeclare {{ class %(class_name)s : public %(base_class)s { public: // Constructor. %(class_name)s(ExtMachInst machInst); - %(MwaitExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa index ee0600dfd..963e07c77 100644 --- a/src/arch/x86/isa/formats/unimp.isa +++ b/src/arch/x86/isa/formats/unimp.isa @@ -62,7 +62,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -93,7 +93,7 @@ output header {{ flags[IsNonSpeculative] = true; } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa index 769ffb7b8..a5c48fce1 100644 --- a/src/arch/x86/isa/formats/unknown.isa +++ b/src/arch/x86/isa/formats/unknown.isa @@ -57,7 +57,7 @@ output header {{ { } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa index 99faa2e03..3a1a84a7d 100644 --- a/src/arch/x86/isa/macroop.isa +++ b/src/arch/x86/isa/macroop.isa @@ -61,7 +61,12 @@ output header {{ uint32_t _numMicroops, X86ISA::EmulEnv _env) : MacroopBase(mnem, _machInst, _numMicroops, _env) {} - %(MacroExecPanic)s + + Fault + execute(ExecContext *, Trace::InstRecord *) const + { + panic("Tried to execute macroop directly!"); + } }; }}; diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa index 87e7879f1..6852f6826 100644 --- a/src/arch/x86/isa/microops/debug.isa +++ b/src/arch/x86/isa/microops/debug.isa @@ -78,7 +78,7 @@ def template MicroDebugDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, uint64_t setFlags, std::string _message, uint8_t _cc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa index 5973c7d06..65c2fdb57 100644 --- a/src/arch/x86/isa/microops/fpop.isa +++ b/src/arch/x86/isa/microops/fpop.isa @@ -85,7 +85,7 @@ def template MicroFpOpDeclare {{ InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, int8_t _spm); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa index 2f1c267a2..5ff4f0cea 100644 --- a/src/arch/x86/isa/microops/ldstop.isa +++ b/src/arch/x86/isa/microops/ldstop.isa @@ -81,7 +81,7 @@ def template MicroLeaDeclare {{ uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -223,18 +223,6 @@ def template MicroStoreCompleteAcc {{ } }}; -// Common templates - -//This delcares the initiateAcc function in memory operations -def template InitiateAccDeclare {{ - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; -}}; - -//This declares the completeAcc function in memory operations -def template CompleteAccDeclare {{ - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; -}}; - def template MicroLdStOpDeclare {{ class %(class_name)s : public %(base_class)s { @@ -247,11 +235,9 @@ def template MicroLdStOpDeclare {{ uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; @@ -269,11 +255,9 @@ def template MicroLdStSplitOpDeclare {{ uint8_t _dataSize, uint8_t _addressSize, Request::FlagsType _memFlags); - %(BasicExecDeclare)s - - %(InitiateAccDeclare)s - - %(CompleteAccDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; + Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa index ac0438ae0..fce12d2a4 100644 --- a/src/arch/x86/isa/microops/limmop.isa +++ b/src/arch/x86/isa/microops/limmop.isa @@ -71,7 +71,7 @@ def template MicroLimmOpDeclare {{ uint64_t setFlags, InstRegIndex _dest, uint64_t _imm, uint8_t _dataSize); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa index 19bbc6392..7e28bc277 100644 --- a/src/arch/x86/isa/microops/mediaop.isa +++ b/src/arch/x86/isa/microops/mediaop.isa @@ -57,7 +57,7 @@ def template MediaOpRegDeclare {{ InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -71,7 +71,7 @@ def template MediaOpImmDeclare {{ InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index 2f8fc4dfc..4fd3b2aa6 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -111,7 +111,7 @@ def template MicroRegOpDeclare {{ InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -125,7 +125,7 @@ def template MicroRegOpImmDeclare {{ InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, uint8_t _dataSize, uint16_t _ext); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa index 601aa6775..f5cb589f3 100644 --- a/src/arch/x86/isa/microops/seqop.isa +++ b/src/arch/x86/isa/microops/seqop.isa @@ -63,7 +63,7 @@ def template SeqOpDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, uint64_t setFlags, uint16_t _target, uint8_t _cc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa index 2b1d8ba44..7bfe22fbc 100644 --- a/src/arch/x86/isa/microops/specop.isa +++ b/src/arch/x86/isa/microops/specop.isa @@ -69,7 +69,7 @@ output header {{ { } - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -83,7 +83,7 @@ def template MicroFaultDeclare {{ %(class_name)s(ExtMachInst _machInst, const char * instMnem, uint64_t setFlags, Fault _fault, uint8_t _cc); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; @@ -214,7 +214,7 @@ def template MicroFenceOpDeclare {{ const char * instMnem, uint64_t setFlags); - %(BasicExecDeclare)s + Fault execute(ExecContext *, Trace::InstRecord *) const; }; }}; |