diff options
| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-21 12:06:37 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | 7d70967abaf1ce3a09433620dc41ed48c2fc0db0 (patch) | |
| tree | afe7e0283905573ae9e8d3655401fabf45184148 /src | |
| parent | 099cb037e83d1e7bb47ec0e8eaf649a63f889d38 (diff) | |
| download | gem5-7d70967abaf1ce3a09433620dc41ed48c2fc0db0.tar.xz | |
arm: Add CMO support for Non-Cacheable memory
Cache Maintainance operations to the point of coherence are treated as
normal cahceable requests and clean and/or invalidate the caches of
all PEs.
Change-Id: Ia4a749c2318fe29c8601848b034b8315c4186c8a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5056
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/tlb.cc | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 6f7998db2..de7ebf8b6 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1007,7 +1007,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, if ((req->isInstFetch() && (!sctlr.i)) || ((!req->isInstFetch()) && (!sctlr.c))){ - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); + if (!req->isCacheMaintenance()) { + req->setFlags(Request::UNCACHEABLE); + } + req->setFlags(Request::STRICT_ORDER); } if (!is_fetch) { assert(flags & MustBeOne); @@ -1033,11 +1036,12 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, req->setFlags(Request::SECURE); // @todo: double check this (ARM ARM issue C B3.2.1) - if (long_desc_format || sctlr.tre == 0) { - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); - } else { - if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) - req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER); + if (long_desc_format || sctlr.tre == 0 || nmrr.ir0 == 0 || + nmrr.or0 == 0 || prrr.tr0 != 0x2) { + if (!req->isCacheMaintenance()) { + req->setFlags(Request::UNCACHEABLE); + } + req->setFlags(Request::STRICT_ORDER); } // Set memory attributes @@ -1091,7 +1095,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, static_cast<uint8_t>(te->mtype), isStage2); setAttr(te->attributes); - if (te->nonCacheable) + if (te->nonCacheable && !req->isCacheMaintenance()) req->setFlags(Request::UNCACHEABLE); // Require requests to be ordered if the request goes to |