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authorGabe Black <gblack@eecs.umich.edu>2009-06-21 09:48:51 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-06-21 09:48:51 -0700
commit7e4f132369193f3a8a8f05ecf1f5a531c762288a (patch)
treeb777444109b9b01bc123591f9672d1e928035276 /src
parent4415e2dcd6ca508c4ffa8aa1fdcc53daee79b898 (diff)
downloadgem5-7e4f132369193f3a8a8f05ecf1f5a531c762288a.tar.xz
ARM: Get rid of a few more unused operands.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/decoder.isa1
-rw-r--r--src/arch/arm/isa/operands.isa3
2 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 8b4175f9c..af325b57a 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -832,7 +832,6 @@ decode COND_CODE default Unknown::unknown() {
// ARM System Call (SoftWare Interrupt)
1: swi({{ if (testPredicate(Cpsr, condCode))
{
- //xc->syscall(R7);
xc->syscall(IMMED_23_0);
}
}});
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index be4ec6e03..c056d41f2 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -48,12 +48,9 @@ def operands {{
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
- 'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
- 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
- 'Ignore': ('IntReg', 'uw', '16', 'IsInteger', 99),
#General Purpose Floating Point Reg Operands
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),