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authorAndreas Sandberg <andreas@sandberg.pp.se>2013-06-04 10:08:21 +0200
committerAndreas Sandberg <andreas@sandberg.pp.se>2013-06-04 10:08:21 +0200
commita3685b0181ea4a71bd82fea11fa0e6df47b0cd93 (patch)
treed1cfb2302c424cbef2eb01a16537e4d5d92bfbec /src
parent7846f59d0dcb36c13e06a3ba8a4c461e646582b6 (diff)
downloadgem5-a3685b0181ea4a71bd82fea11fa0e6df47b0cd93.tar.xz
dev: Clarify why updates are delayed when the MC14818 is activated
Diffstat (limited to 'src')
-rw-r--r--src/dev/mc146818.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc
index abacd8742..81366b774 100644
--- a/src/dev/mc146818.cc
+++ b/src/dev/mc146818.cc
@@ -163,8 +163,10 @@ MC146818::writeData(const uint8_t addr, const uint8_t data)
if (tickEvent.scheduled())
deschedule(tickEvent);
} else if (rega_dv_disabled(old_rega)) {
- // If the divider chain goes from reset to active, we
- // need to schedule a tick after precisely 0.5s.
+ // According to the specification, the next tick
+ // happens after 0.5s when the divider chain goes
+ // from reset to active. So, we simply schedule the
+ // tick after 0.5s.
assert(!tickEvent.scheduled());
schedule(tickEvent, curTick() + SimClock::Int::s / 2);
}