ARM: Fold the MiscRegFile all the way into the ISA object.

4 files changed, 37 insertions, 178 deletions

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 7244252d8..519435489 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -39,7 +39,6 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/mem.cc')
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
-    Source('isa.cc')
     Source('pagetable.cc')
     Source('tlb.cc')
     Source('vtophys.cc')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
deleted file mode 100644
index 944f19c0b..000000000
--- a/src/arch/arm/isa.cc
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2009 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
- */
-
-#include "arch/arm/isa.hh"
-#include "cpu/thread_context.hh"
-
-namespace ArmISA
-{
-
-void
-ISA::clear()
-{
-    miscRegFile.clear();
-}
-
-MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
-{
-    return miscRegFile.readRegNoEffect(miscReg);
-}
-
-MiscReg
-ISA::readMiscReg(int miscReg, ThreadContext *tc)
-{
-    return miscRegFile.readReg(miscReg, tc);
-}
-
-void
-ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
-{
-    miscRegFile.setRegNoEffect(miscReg, val);
-}
-
-void
-ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
-{
-    miscRegFile.setReg(miscReg, val, tc);
-}
-
-void
-ISA::serialize(std::ostream &os)
-{
-    //miscRegFile.serialize(os);
-}
-
-void
-ISA::unserialize(Checkpoint *cp, const std::string &section)
-{
-    //miscRegFile.unserialize(cp, section);
-}
-
-}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 0f1347eac..39acc9c08 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -31,9 +31,10 @@
 #ifndef __ARCH_ARM_ISA_HH__
 #define __ARCH_MRM_ISA_HH__
 
-#include "arch/arm/misc_regfile.hh"
+#include "arch/arm/registers.hh"
 #include "arch/arm/types.hh"
 
+class ThreadContext;
 class Checkpoint;
 class EventManager;
 
@@ -42,17 +43,41 @@ namespace ArmISA
     class ISA
     {
       protected:
-        MiscRegFile miscRegFile;
+        MiscReg miscRegs[NumMiscRegs];
 
       public:
-        void clear();
+        void clear()
+        {
+            // Unknown startup state currently
+        }
+
+        MiscReg
+        readMiscRegNoEffect(int misc_reg)
+        {
+            assert(misc_reg < NumMiscRegs);
+            return miscRegs[misc_reg];
+        }
+
+        MiscReg
+        readMiscReg(int misc_reg, ThreadContext *tc)
+        {
+            assert(misc_reg < NumMiscRegs);
+            return miscRegs[misc_reg];
+        }
 
-        MiscReg readMiscRegNoEffect(int miscReg);
-        MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+        void
+        setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+        {
+            assert(misc_reg < NumMiscRegs);
+            miscRegs[misc_reg] = val;
+        }
 
-        void setMiscRegNoEffect(int miscReg, const MiscReg val);
-        void setMiscReg(int miscReg, const MiscReg val,
-                ThreadContext *tc);
+        void
+        setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
+        {
+            assert(misc_reg < NumMiscRegs);
+            miscRegs[misc_reg] = val;
+        }
 
         int
         flattenIntIndex(int reg)
@@ -66,8 +91,10 @@ namespace ArmISA
             return reg;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        void serialize(std::ostream &os)
+        {}
+        void unserialize(Checkpoint *cp, const std::string &section)
+        {}
 
         ISA()
         {
diff --git a/src/arch/arm/misc_regfile.hh b/src/arch/arm/misc_regfile.hh
deleted file mode 100644
index 6cafc524f..000000000
--- a/src/arch/arm/misc_regfile.hh
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
-
-#include "arch/arm/registers.hh"
-#include "arch/arm/types.hh"
-#include "sim/faults.hh"
-
-class ThreadContext;
-
-namespace ArmISA
-{
-    static inline std::string
-    getMiscRegName(RegIndex)
-    {
-        return "";
-    }
-
-    class MiscRegFile {
-
-      protected:
-        MiscReg miscRegFile[NumMiscRegs];
-
-      public:
-        void clear()
-        {
-            // Unknown startup state in misc register file currently
-        }
-
-        void copyMiscRegs(ThreadContext *tc);
-
-        MiscReg readRegNoEffect(int misc_reg)
-        {
-            assert(misc_reg < NumMiscRegs);
-            return miscRegFile[misc_reg];
-        }
-
-        MiscReg readReg(int misc_reg, ThreadContext *tc)
-        {
-            assert(misc_reg < NumMiscRegs);
-            return miscRegFile[misc_reg];
-        }
-
-        void setRegNoEffect(int misc_reg, const MiscReg &val)
-        {
-            assert(misc_reg < NumMiscRegs);
-            miscRegFile[misc_reg] = val;
-        }
-
-        void setReg(int misc_reg, const MiscReg &val,
-                               ThreadContext *tc)
-        {
-            assert(misc_reg < NumMiscRegs);
-            miscRegFile[misc_reg] = val;
-        }
-    };
-} // namespace ArmISA
-
-#endif