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authorAli Saidi <saidi@eecs.umich.edu>2006-06-27 15:04:11 -0400
committerAli Saidi <saidi@eecs.umich.edu>2006-06-27 15:04:11 -0400
commitecab4b426c949dad797df0bde1c0c120b4b5fb00 (patch)
tree3e37ef3c4cd06aab776f4cedf6840526eded9215 /src
parent07cd37c48b018679553e6b12a5591c5759f433d6 (diff)
downloadgem5-ecab4b426c949dad797df0bde1c0c120b4b5fb00.tar.xz
change the page table from map to hash_map and create small cache to to speed up lookups
--HG-- extra : convert_revision : 4c73ed33c2a22ae3254b459b0fd189e6ac9d438e
Diffstat (limited to 'src')
-rw-r--r--src/mem/page_table.cc28
-rw-r--r--src/mem/page_table.hh11
2 files changed, 35 insertions, 4 deletions
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 7daf31900..a34a0393a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -54,6 +54,9 @@ PageTable::PageTable(System *_system, Addr _pageSize)
system(_system)
{
assert(isPowerOf2(pageSize));
+ pTableCache[0].vaddr = 0;
+ pTableCache[1].vaddr = 0;
+ pTableCache[2].vaddr = 0;
}
PageTable::~PageTable()
@@ -95,7 +98,7 @@ PageTable::allocate(Addr vaddr, int size)
assert(pageOffset(vaddr) == 0);
for (; size > 0; size -= pageSize, vaddr += pageSize) {
- std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
+ m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr);
if (iter != pTable.end()) {
// already mapped
@@ -103,6 +106,12 @@ PageTable::allocate(Addr vaddr, int size)
}
pTable[vaddr] = system->new_page();
+ pTableCache[2].paddr = pTableCache[1].paddr;
+ pTableCache[2].vaddr = pTableCache[1].vaddr;
+ pTableCache[1].paddr = pTableCache[0].paddr;
+ pTableCache[1].vaddr = pTableCache[0].vaddr;
+ pTableCache[0].paddr = pTable[vaddr];
+ pTableCache[0].vaddr = vaddr;
}
}
@@ -112,7 +121,22 @@ bool
PageTable::translate(Addr vaddr, Addr &paddr)
{
Addr page_addr = pageAlign(vaddr);
- std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
+ paddr = 0;
+
+ if (pTableCache[0].vaddr == vaddr) {
+ paddr = pTableCache[0].paddr;
+ return true;
+ }
+ if (pTableCache[1].vaddr == vaddr) {
+ paddr = pTableCache[1].paddr;
+ return true;
+ }
+ if (pTableCache[2].vaddr == vaddr) {
+ paddr = pTableCache[2].paddr;
+ return true;
+ }
+
+ m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr);
if (iter == pTable.end()) {
return false;
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index f7212d423..494c0ce9a 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -37,9 +37,9 @@
#define __PAGE_TABLE__
#include <string>
-#include <map>
#include "arch/isa_traits.hh"
+#include "base/hashmap.hh"
#include "base/trace.hh"
#include "mem/request.hh"
#include "mem/packet.hh"
@@ -53,7 +53,14 @@ class System;
class PageTable
{
protected:
- std::map<Addr,Addr> pTable;
+ m5::hash_map<Addr,Addr> pTable;
+
+ struct cacheElement {
+ Addr paddr;
+ Addr vaddr;
+ } ;
+
+ struct cacheElement pTableCache[3];
const Addr pageSize;
const Addr offsetMask;