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| author | Kevin Lim <ktlim@umich.edu> | 2006-11-28 11:41:08 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-11-28 11:41:08 -0500 |
| commit | 2b5fdf603399c63a9344206f1593b20fcb834013 (patch) | |
| tree | b04175ff5f3beee931aa750b6c2d5f4999d6dd4e /src | |
| parent | 07e525e8b78fba0ebaf5c50f32fbf30d17051891 (diff) | |
| download | gem5-2b5fdf603399c63a9344206f1593b20fcb834013.tar.xz | |
Remove assertion. It's not needed and messes up writebacks when a 2 level cache is used in a uniprocessor setting.
--HG--
extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/cache/coherence/uni_coherence.cc | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mem/cache/coherence/uni_coherence.cc b/src/mem/cache/coherence/uni_coherence.cc index 5813a0281..ea615d70a 100644 --- a/src/mem/cache/coherence/uni_coherence.cc +++ b/src/mem/cache/coherence/uni_coherence.cc @@ -94,10 +94,6 @@ UniCoherence::handleBusRequest(PacketPtr &pkt, CacheBlk *blk, MSHR *mshr, bool UniCoherence::propogateInvalidate(PacketPtr pkt, bool isTiming) { - //Make sure we don't snoop a write - //we are expecting writeInvalidates on the snoop port of a uni-coherent cache - assert(!(!pkt->isInvalidate() && pkt->isWrite())); - if (pkt->isInvalidate()) { /* Temp Fix for now, forward all invalidates up as functional accesses */ if (isTiming) { |