Merge with head.

--HG--
extra : convert_revision : f331b9cbd82086d63d4f35e18f9e08466c016225

14 files changed, 941 insertions, 259 deletions

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index b3fd67f89..f4a8782f2 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -105,7 +105,9 @@ if env['TARGET_ISA'] == 'x86':
 
     if env['FULL_SYSTEM']:
         # Full-system sources
-        pass
+        Source('stacktrace.cc')
+        Source('utility.cc')
+        Source('vtophys.cc')
     else:
         Source('process.cc')
 
diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh
index 3f33b8d85..614909f73 100644
--- a/src/arch/x86/interrupts.hh
+++ b/src/arch/x86/interrupts.hh
@@ -58,10 +58,75 @@
 #ifndef __ARCH_X86_INTERRUPTS_HH__
 #define __ARCH_X86_INTERRUPTS_HH__
 
-#error X86 is not yet supported!
+#include "arch/x86/faults.hh"
+#include "cpu/thread_context.hh"
 
 namespace X86ISA
 {
+
+class Interrupts
+{
+  public:
+    Interrupts()
+    {
+        clear_all();
+    }
+
+    int InterruptLevel(uint64_t softint)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return 0;
+    }
+
+    void post(int int_num, int index)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void clear(int int_num, int index)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void clear_all()
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    bool check_interrupts(ThreadContext * tc) const
+    {
+        panic("Interrupts don't work on x86!\n");
+        return false;
+    }
+
+    Fault getInterrupt(ThreadContext * tc)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return NoFault;
+    }
+
+    void updateIntrInfo(ThreadContext * tc)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    uint64_t get_vec(int int_num)
+    {
+        panic("Interrupts don't work on x86!\n");
+        return 0;
+    }
+
+    void serialize(std::ostream & os)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+
+    void unserialize(Checkpoint * cp, const std::string & section)
+    {
+        panic("Interrupts don't work on x86!\n");
+    }
+};
+
 };
 
 #endif // __ARCH_X86_INTERRUPTS_HH__
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index f3478d7f6..e69813836 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -61,6 +61,7 @@
 #include "arch/x86/intregs.hh"
 #include "arch/x86/types.hh"
 #include "arch/x86/x86_traits.hh"
+#include "sim/host.hh"
 
 class StaticInstPtr;
 
@@ -132,6 +133,8 @@ namespace X86ISA
     const int BranchPredAddrShiftAmt = 0;
 
     StaticInstPtr decodeInst(ExtMachInst);
+
+    const Addr LoadAddrMask = ULL(0xffffffffff);
 };
 
 #endif // __ARCH_X86_ISATRAITS_HH__
diff --git a/src/arch/x86/kernel_stats.hh b/src/arch/x86/kernel_stats.hh
index 8cd80073e..7679cb305 100644
--- a/src/arch/x86/kernel_stats.hh
+++ b/src/arch/x86/kernel_stats.hh
@@ -58,10 +58,33 @@
 #ifndef __ARCH_X86_KERNELSTATS_HH__
 #define __ARCH_X86_KERNELSTATS_HH__
 
-#error X86 is not yet supported!
+#include "kern/kernel_stats.hh"
 
-namespace X86ISA
+namespace X86ISA {
+namespace Kernel {
+
+enum cpu_mode {
+    ring0,
+    ring1,
+    ring2,
+    ring3,
+    kernel = ring0,
+    user = ring3,
+    idle,
+    //What is this next one for?
+    cpu_mode_num
+};
+
+extern const char *modestr[];
+
+class Statistics : public ::Kernel::Statistics
 {
+  public:
+    Statistics(System * system) : ::Kernel::Statistics(system)
+    {}
 };
 
+}
+}
+
 #endif // __ARCH_X86_KERNELSTATS_HH__
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index bab813719..8080bd90b 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -61,6 +61,12 @@
 #include "arch/x86/x86_traits.hh"
 #include "base/bitunion.hh"
 
+//These get defined in some system headers (at least termbits.h). That confuses
+//things here significantly.
+#undef CR0
+#undef CR2
+#undef CR3
+
 namespace X86ISA
 {
     enum CondFlagBit {
diff --git a/src/arch/x86/mmaped_ipr.hh b/src/arch/x86/mmaped_ipr.hh
index a33a3f4f0..1fef72fa6 100644
--- a/src/arch/x86/mmaped_ipr.hh
+++ b/src/arch/x86/mmaped_ipr.hh
@@ -75,6 +75,8 @@ namespace X86ISA
     {
 #if !FULL_SYSTEM
         panic("Shouldn't have a memory mapped register in SE\n");
+#else
+        panic("Memory mapped registers aren't implemented for x86!\n");
 #endif
     }
 
@@ -83,6 +85,8 @@ namespace X86ISA
     {
 #if !FULL_SYSTEM
         panic("Shouldn't have a memory mapped register in SE\n");
+#else
+        panic("Memory mapped registers aren't implemented for x86!\n");
 #endif
     }
 };
diff --git a/src/arch/x86/stacktrace.cc b/src/arch/x86/stacktrace.cc
new file mode 100644
index 000000000..300e8dcd0
--- /dev/null
+++ b/src/arch/x86/stacktrace.cc
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <string>
+
+#include "arch/x86/isa_traits.hh"
+#include "arch/x86/stacktrace.hh"
+#include "arch/x86/vtophys.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+
+using namespace std;
+namespace X86ISA
+{
+    ProcessInfo::ProcessInfo(ThreadContext *_tc)
+        : tc(_tc)
+    {
+        Addr addr = 0;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
+            panic("thread info not compiled into kernel\n");
+        thread_info_size = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
+            panic("thread info not compiled into kernel\n");
+        task_struct_size = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
+            panic("thread info not compiled into kernel\n");
+        task_off = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
+            panic("thread info not compiled into kernel\n");
+        pid_off = vp->readGtoH<int32_t>(addr);
+
+        if (!tc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
+            panic("thread info not compiled into kernel\n");
+        name_off = vp->readGtoH<int32_t>(addr);
+
+        tc->delVirtPort(vp);
+    }
+
+    Addr
+    ProcessInfo::task(Addr ksp) const
+    {
+        Addr base = ksp & ~0x3fff;
+        if (base == ULL(0xfffffc0000000000))
+            return 0;
+
+        Addr tsk;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        tsk = vp->readGtoH<Addr>(base + task_off);
+        tc->delVirtPort(vp);
+
+        return tsk;
+    }
+
+    int
+    ProcessInfo::pid(Addr ksp) const
+    {
+        Addr task = this->task(ksp);
+        if (!task)
+            return -1;
+
+        uint16_t pd;
+
+        VirtualPort *vp;
+
+        vp = tc->getVirtPort();
+        pd = vp->readGtoH<uint16_t>(task + pid_off);
+        tc->delVirtPort(vp);
+
+        return pd;
+    }
+
+    string
+    ProcessInfo::name(Addr ksp) const
+    {
+        Addr task = this->task(ksp);
+        if (!task)
+            return "console";
+
+        char comm[256];
+        CopyStringOut(tc, comm, task + name_off, sizeof(comm));
+        if (!comm[0])
+            return "startup";
+
+        return comm;
+    }
+
+    StackTrace::StackTrace()
+        : tc(0), stack(64)
+    {
+    }
+
+    StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+        : tc(0), stack(64)
+    {
+        trace(_tc, inst);
+    }
+
+    StackTrace::~StackTrace()
+    {
+    }
+
+    void
+    StackTrace::trace(ThreadContext *_tc, bool is_call)
+    {
+    }
+
+    bool
+    StackTrace::isEntry(Addr addr)
+    {
+        return false;
+    }
+
+    bool
+    StackTrace::decodeStack(MachInst inst, int &disp)
+    {
+        disp = 0;
+        return true;
+    }
+
+    bool
+    StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
+    {
+        reg = 0;
+        disp = 0;
+        return true;
+    }
+
+    /*
+     * Decode the function prologue for the function we're in, and note
+     * which registers are stored where, and how large the stack frame is.
+     */
+    bool
+    StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
+                               int &size, Addr &ra)
+    {
+        size = 0;
+        ra = 0;
+
+        for (Addr pc = func; pc < callpc; pc += sizeof(MachInst)) {
+            MachInst inst;
+            CopyOut(tc, (uint8_t *)&inst, pc, sizeof(MachInst));
+
+            int reg, disp;
+            if (decodeStack(inst, disp)) {
+                if (size) {
+                    // panic("decoding frame size again");
+                    return true;
+                }
+                size += disp;
+            } else if (decodeSave(inst, reg, disp)) {
+                if (!ra && reg == ReturnAddressReg) {
+                    CopyOut(tc, (uint8_t *)&ra, sp + disp, sizeof(Addr));
+                    if (!ra) {
+                        // panic("no return address value pc=%#x\n", pc);
+                        return false;
+                    }
+                }
+            }
+        }
+
+        return true;
+    }
+
+#if TRACING_ON
+    void
+    StackTrace::dump()
+    {
+        StringWrap name(tc->getCpuPtr()->name());
+        SymbolTable *symtab = tc->getSystemPtr()->kernelSymtab;
+
+        DPRINTFN("------ Stack ------\n");
+
+        string symbol;
+        for (int i = 0, size = stack.size(); i < size; ++i) {
+            Addr addr = stack[size - i - 1];
+            if (addr == user)
+                symbol = "user";
+            else if (addr == console)
+                symbol = "console";
+            else if (addr == unknown)
+                symbol = "unknown";
+            else
+                symtab->findSymbol(addr, symbol);
+
+            DPRINTFN("%#x: %s\n", addr, symbol);
+        }
+    }
+#endif
+}
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index d2db8cb0b..ad23cb7e4 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -57,6 +57,83 @@
 
 #include <cstring>
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
+
+#include "arch/x86/tlb.hh"
+#include "base/bitfield.hh"
+#include "base/trace.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "mem/packet_access.hh"
+#include "mem/request.hh"
+#include "sim/system.hh"
+
+namespace X86ISA {
+
+TLB::TLB(const Params *p) : SimObject(p)
+{
+}
+
+Fault
+ITB::translate(RequestPtr &req, ThreadContext *tc)
+{
+    return NoFault;
+}
+
+
+
+Fault
+DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
+{
+    return NoFault;
+};
+
+#if FULL_SYSTEM
+
+Tick
+DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
+{
+    return tc->getCpuPtr()->cycles(1);
+}
+
+Tick
+DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
+{
+    return tc->getCpuPtr()->cycles(1);
+}
+
+#endif
+
+void
+TLB::serialize(std::ostream &os)
+{
+}
+
+void
+TLB::unserialize(Checkpoint *cp, const std::string &section)
+{
+}
+
+void
+DTB::serialize(std::ostream &os)
+{
+    TLB::serialize(os);
+}
+
+void
+DTB::unserialize(Checkpoint *cp, const std::string &section)
+{
+    TLB::unserialize(cp, section);
+}
+
+/* end namespace X86ISA */ }
+
+#else
+
+#include <cstring>
+
 #include "arch/x86/tlb.hh"
 #include "params/X86DTB.hh"
 #include "params/X86ITB.hh"
@@ -76,6 +153,8 @@ namespace X86ISA {
     }
 };
 
+#endif
+
 X86ISA::ITB *
 X86ITBParams::create()
 {
diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 354443794..386d1635d 100644
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -58,6 +58,80 @@
 #ifndef __ARCH_X86_TLB_HH__
 #define __ARCH_X86_TLB_HH__
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
+
+#include "mem/request.hh"
+#include "params/X86DTB.hh"
+#include "params/X86ITB.hh"
+#include "sim/faults.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+class Packet;
+
+namespace X86ISA
+{
+    struct TlbEntry
+    {
+        Addr pageStart;
+        TlbEntry() {}
+        TlbEntry(Addr paddr) : pageStart(paddr) {}
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+class TLB : public SimObject
+{
+  public:
+    typedef X86TLBParams Params;
+    TLB(const Params *p);
+
+    void dumpAll();
+
+    // Checkpointing
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+class ITB : public TLB
+{
+  public:
+    typedef X86ITBParams Params;
+    ITB(const Params *p) : TLB(p)
+    {
+    }
+
+    Fault translate(RequestPtr &req, ThreadContext *tc);
+
+    friend class DTB;
+};
+
+class DTB : public TLB
+{
+  public:
+    typedef X86DTBParams Params;
+    DTB(const Params *p) : TLB(p)
+    {
+    }
+
+    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+#if FULL_SYSTEM
+    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
+
+    // Checkpointing
+    virtual void serialize(std::ostream &os);
+    virtual void unserialize(Checkpoint *cp, const std::string &section);
+};
+
+}
+
+#else
+
 #include <iostream>
 
 #include "sim/host.hh"
@@ -92,4 +166,6 @@ namespace X86ISA
     };
 };
 
+#endif
+
 #endif // __ARCH_X86_TLB_HH__
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
new file mode 100644
index 000000000..b2532a13e
--- /dev/null
+++ b/src/arch/x86/utility.cc
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/x86/utility.hh"
+
+namespace X86ISA {
+
+uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
+#if FULL_SYSTEM
+    panic("getArgument() not implemented for x86!\n");
+#else
+    panic("getArgument() only implemented for FULL_SYSTEM\n");
+    M5_DUMMY_RETURN
+#endif
+}
+} //namespace X86_ISA
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 3f3f1cca3..9497986e6 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -87,6 +87,8 @@ namespace __hash_namespace {
 
 namespace X86ISA
 {
+    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
     static inline bool
     inUserMode(ThreadContext *tc)
     {
diff --git a/src/arch/x86/vtophys.cc b/src/arch/x86/vtophys.cc
new file mode 100644
index 000000000..bac2748a4
--- /dev/null
+++ b/src/arch/x86/vtophys.cc
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * Redistribution and use of this software in source and binary forms,
+ * with or without modification, are permitted provided that the
+ * following conditions are met:
+ *
+ * The software must be used only for Non-Commercial Use which means any
+ * use which is NOT directed to receiving any direct monetary
+ * compensation for, or commercial advantage from such use.  Illustrative
+ * examples of non-commercial use are academic research, personal study,
+ * teaching, education and corporate research & development.
+ * Illustrative examples of commercial use are distributing products for
+ * commercial advantage and providing services using the software for
+ * commercial advantage.
+ *
+ * If you wish to use this software or functionality therein that may be
+ * covered by patents for commercial use, please contact:
+ *     Director of Intellectual Property Licensing
+ *     Office of Strategy and Technology
+ *     Hewlett-Packard Company
+ *     1501 Page Mill Road
+ *     Palo Alto, California  94304
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.  Redistributions
+ * in binary form must reproduce the above copyright notice, this list of
+ * conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.  Neither the name of
+ * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.  No right of
+ * sublicense is granted herewith.  Derivatives of the software and
+ * output created using the software may be prepared, but only for
+ * Non-Commercial Uses.  Derivatives of the software may be shared with
+ * others provided: (i) the others agree to abide by the list of
+ * conditions herein which includes the Non-Commercial Use restrictions;
+ * and (ii) such Derivatives of the software include the above copyright
+ * notice to acknowledge the contribution from this software where
+ * applicable, this list of conditions and the disclaimer below.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include <string>
+
+#include "arch/x86/vtophys.hh"
+
+using namespace std;
+
+namespace X86ISA
+{
+    Addr vtophys(Addr vaddr)
+    {
+        return vaddr;
+    }
+
+    Addr vtophys(ThreadContext *tc, Addr addr)
+    {
+        return addr;
+    }
+}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d6b124efc..9fc1d1dd9 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -428,11 +428,10 @@ void
 BaseSimpleCPU::postExecute()
 {
 #if FULL_SYSTEM
-    if (thread->profile) {
+    if (thread->profile && curStaticInst) {
         bool usermode = TheISA::inUserMode(tc);
         thread->profilePC = usermode ? 1 : thread->readPC();
-        StaticInstPtr si(inst, thread->readPC());
-        ProfileNode *node = thread->profile->consume(tc, si);
+        ProfileNode *node = thread->profile->consume(tc, curStaticInst);
         if (node)
             thread->profileNode = node;
     }
diff --git a/src/dev/ns_gige_reg.h b/src/dev/ns_gige_reg.h
index 80ac5800d..c37c06aed 100644
--- a/src/dev/ns_gige_reg.h
+++ b/src/dev/ns_gige_reg.h
@@ -37,280 +37,320 @@
 #define __DEV_NS_GIGE_REG_H__
 
 /* Device Register Address Map */
-#define CR		0x00
-#define CFGR		0x04
-#define MEAR		0x08
-#define PTSCR		0x0c
-#define	ISR		0x10
-#define	IMR		0x14
-#define	IER		0x18
-#define	IHR		0x1c
-#define TXDP		0x20
-#define TXDP_HI		0x24
-#define TX_CFG		0x28
-#define GPIOR		0x2c
-#define RXDP		0x30
-#define RXDP_HI		0x34
-#define RX_CFG		0x38
-#define PQCR		0x3c
-#define WCSR		0x40
-#define PCR		0x44
-#define RFCR		0x48
-#define RFDR		0x4c
-#define BRAR            0x50
-#define BRDR            0x54
-#define SRR		0x58
-#define MIBC            0x5c
-#define MIB_START       0x60
-#define MIB_END         0x88
-#define VRCR		0xbc
-#define VTCR		0xc0
-#define VDR		0xc4
-#define CCSR		0xcc
-#define TBICR		0xe0
-#define TBISR		0xe4
-#define TANAR		0xe8
-#define TANLPAR		0xec
-#define TANER		0xf0
-#define TESR		0xf4
-#define M5REG		0xf8
-#define LAST            0xf8
-#define RESERVED        0xfc
+enum DeviceRegisterAddress {
+    CR =                0x00,
+    CFGR =              0x04,
+    MEAR =              0x08,
+    PTSCR =             0x0c,
+    ISR =               0x10,
+    IMR =               0x14,
+    IER =               0x18,
+    IHR =               0x1c,
+    TXDP =              0x20,
+    TXDP_HI =           0x24,
+    TX_CFG =            0x28,
+    GPIOR =             0x2c,
+    RXDP =              0x30,
+    RXDP_HI =           0x34,
+    RX_CFG =            0x38,
+    PQCR =              0x3c,
+    WCSR =              0x40,
+    PCR =               0x44,
+    RFCR =              0x48,
+    RFDR =              0x4c,
+    BRAR =              0x50,
+    BRDR =              0x54,
+    SRR =               0x58,
+    MIBC =              0x5c,
+    MIB_START =         0x60,
+    MIB_END =           0x88,
+    VRCR =              0xbc,
+    VTCR =              0xc0,
+    VDR =               0xc4,
+    CCSR =              0xcc,
+    TBICR =             0xe0,
+    TBISR =             0xe4,
+    TANAR =             0xe8,
+    TANLPAR =           0xec,
+    TANER =             0xf0,
+    TESR =              0xf4,
+    M5REG =             0xf8,
+    LAST =              0xf8,
+    RESERVED =          0xfc
+};
 
 /* Chip Command Register */
-#define CR_TXE		0x00000001
-#define CR_TXD		0x00000002
-#define CR_RXE		0x00000004
-#define CR_RXD		0x00000008
-#define CR_TXR		0x00000010
-#define CR_RXR		0x00000020
-#define CR_SWI		0x00000080
-#define CR_RST		0x00000100
+enum ChipCommandRegister {
+     CR_TXE =           0x00000001,
+     CR_TXD =           0x00000002,
+     CR_RXE =           0x00000004,
+     CR_RXD =           0x00000008,
+     CR_TXR =           0x00000010,
+     CR_RXR =           0x00000020,
+     CR_SWI =           0x00000080,
+     CR_RST =           0x00000100
+};
 
 /* configuration register */
-#define CFGR_LNKSTS	0x80000000
-#define CFGR_SPDSTS	0x60000000
-#define CFGR_SPDSTS1	0x40000000
-#define CFGR_SPDSTS0	0x20000000
-#define CFGR_DUPSTS	0x10000000
-#define CFGR_TBI_EN	0x01000000
-#define CFGR_RESERVED    0x0e000000
-#define CFGR_MODE_1000	0x00400000
-#define CFGR_AUTO_1000	0x00200000
-#define CFGR_PINT_CTL	0x001c0000
-#define CFGR_PINT_DUPSTS	0x00100000
-#define CFGR_PINT_LNKSTS	0x00080000
-#define CFGR_PINT_SPDSTS	0x00040000
-#define CFGR_TMRTEST	0x00020000
-#define CFGR_MRM_DIS	0x00010000
-#define CFGR_MWI_DIS	0x00008000
-#define CFGR_T64ADDR	0x00004000
-#define CFGR_PCI64_DET	0x00002000
-#define CFGR_DATA64_EN	0x00001000
-#define CFGR_M64ADDR	0x00000800
-#define CFGR_PHY_RST	0x00000400
-#define CFGR_PHY_DIS	0x00000200
-#define CFGR_EXTSTS_EN	0x00000100
-#define CFGR_REQALG	0x00000080
-#define CFGR_SB		0x00000040
-#define CFGR_POW		0x00000020
-#define CFGR_EXD		0x00000010
-#define CFGR_PESEL	0x00000008
-#define CFGR_BROM_DIS	0x00000004
-#define CFGR_EXT_125	0x00000002
-#define CFGR_BEM		0x00000001
+enum ConfigurationRegisters {
+     CFGR_LNKSTS =      0x80000000,
+     CFGR_SPDSTS =      0x60000000,
+     CFGR_SPDSTS1 =     0x40000000,
+     CFGR_SPDSTS0 =     0x20000000,
+     CFGR_DUPSTS =      0x10000000,
+     CFGR_TBI_EN =      0x01000000,
+     CFGR_RESERVED =    0x0e000000,
+     CFGR_MODE_1000 =   0x00400000,
+     CFGR_AUTO_1000 =   0x00200000,
+     CFGR_PINT_CTL =    0x001c0000,
+     CFGR_PINT_DUPSTS = 0x00100000,
+     CFGR_PINT_LNKSTS = 0x00080000,
+     CFGR_PINT_SPDSTS = 0x00040000,
+     CFGR_TMRTEST =     0x00020000,
+     CFGR_MRM_DIS =     0x00010000,
+     CFGR_MWI_DIS =     0x00008000,
+     CFGR_T64ADDR =     0x00004000,
+     CFGR_PCI64_DET =   0x00002000,
+     CFGR_DATA64_EN =   0x00001000,
+     CFGR_M64ADDR =     0x00000800,
+     CFGR_PHY_RST =     0x00000400,
+     CFGR_PHY_DIS =     0x00000200,
+     CFGR_EXTSTS_EN =   0x00000100,
+     CFGR_REQALG =      0x00000080,
+     CFGR_SB =          0x00000040,
+     CFGR_POW =         0x00000020,
+     CFGR_EXD =         0x00000010,
+     CFGR_PESEL =       0x00000008,
+     CFGR_BROM_DIS =    0x00000004,
+     CFGR_EXT_125 =     0x00000002,
+     CFGR_BEM =         0x00000001
+};
 
 /* EEPROM access register */
-#define MEAR_EEDI             	0x00000001
-#define MEAR_EEDO		0x00000002
-#define MEAR_EECLK		0x00000004
-#define MEAR_EESEL		0x00000008
-#define MEAR_MDIO		0x00000010
-#define MEAR_MDDIR		0x00000020
-#define MEAR_MDC		0x00000040
+enum EEPROMAccessRegister {
+     MEAR_EEDI =        0x00000001,
+     MEAR_EEDO =        0x00000002,
+     MEAR_EECLK =       0x00000004,
+     MEAR_EESEL =       0x00000008,
+     MEAR_MDIO =        0x00000010,
+     MEAR_MDDIR =       0x00000020,
+     MEAR_MDC =         0x00000040,
+};
 
 /* PCI test control register */
-#define PTSCR_EEBIST_FAIL       0x00000001
-#define PTSCR_EEBIST_EN         0x00000002
-#define PTSCR_EELOAD_EN         0x00000004
-#define PTSCR_RBIST_FAIL        0x000001b8
-#define PTSCR_RBIST_DONE        0x00000200
-#define PTSCR_RBIST_EN          0x00000400
-#define PTSCR_RBIST_RST         0x00002000
-#define PTSCR_RBIST_RDONLY      0x000003f9
+enum PCITestControlRegister {
+     PTSCR_EEBIST_FAIL =        0x00000001,
+     PTSCR_EEBIST_EN =          0x00000002,
+     PTSCR_EELOAD_EN =          0x00000004,
+     PTSCR_RBIST_FAIL =         0x000001b8,
+     PTSCR_RBIST_DONE =         0x00000200,
+     PTSCR_RBIST_EN =           0x00000400,
+     PTSCR_RBIST_RST =          0x00002000,
+     PTSCR_RBIST_RDONLY =       0x000003f9
+};
 
 /* interrupt status register */
-#define ISR_RESERVE     0x80000000
-#define ISR_TXDESC3	0x40000000
-#define ISR_TXDESC2	0x20000000
-#define ISR_TXDESC1	0x10000000
-#define ISR_TXDESC0	0x08000000
-#define ISR_RXDESC3	0x04000000
-#define ISR_RXDESC2	0x02000000
-#define ISR_RXDESC1	0x01000000
-#define ISR_RXDESC0	0x00800000
-#define ISR_TXRCMP	0x00400000
-#define ISR_RXRCMP	0x00200000
-#define ISR_DPERR	0x00100000
-#define ISR_SSERR	0x00080000
-#define ISR_RMABT	0x00040000
-#define ISR_RTABT	0x00020000
-#define ISR_RXSOVR	0x00010000
-#define ISR_HIBINT	0x00008000
-#define ISR_PHY		0x00004000
-#define ISR_PME		0x00002000
-#define ISR_SWI		0x00001000
-#define ISR_MIB		0x00000800
-#define ISR_TXURN	0x00000400
-#define ISR_TXIDLE	0x00000200
-#define ISR_TXERR	0x00000100
-#define ISR_TXDESC	0x00000080
-#define ISR_TXOK	0x00000040
-#define ISR_RXORN	0x00000020
-#define ISR_RXIDLE	0x00000010
-#define ISR_RXEARLY	0x00000008
-#define ISR_RXERR	0x00000004
-#define ISR_RXDESC	0x00000002
-#define ISR_RXOK	0x00000001
-#define ISR_ALL         0x7FFFFFFF
-#define ISR_DELAY	(ISR_TXIDLE|ISR_TXDESC|ISR_TXOK| \
-                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
-#define ISR_NODELAY	(ISR_ALL & ~ISR_DELAY)
-#define ISR_IMPL        (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
-                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK)
-#define ISR_NOIMPL	(ISR_ALL & ~ISR_IMPL)
+enum InterruptStatusRegister {
+     ISR_RESERVE =      0x80000000,
+     ISR_TXDESC3 =      0x40000000,
+     ISR_TXDESC2 =      0x20000000,
+     ISR_TXDESC1 =      0x10000000,
+     ISR_TXDESC0 =      0x08000000,
+     ISR_RXDESC3 =      0x04000000,
+     ISR_RXDESC2 =      0x02000000,
+     ISR_RXDESC1 =      0x01000000,
+     ISR_RXDESC0 =      0x00800000,
+     ISR_TXRCMP =       0x00400000,
+     ISR_RXRCMP =       0x00200000,
+     ISR_DPERR =        0x00100000,
+     ISR_SSERR =        0x00080000,
+     ISR_RMABT =        0x00040000,
+     ISR_RTAB =         0x00020000,
+     ISR_RXSOVR =       0x00010000,
+     ISR_HIBINT =       0x00008000,
+     ISR_PHY =          0x00004000,
+     ISR_PME =          0x00002000,
+     ISR_SWI =          0x00001000,
+     ISR_MIB =          0x00000800,
+     ISR_TXURN =        0x00000400,
+     ISR_TXIDLE =       0x00000200,
+     ISR_TXERR =        0x00000100,
+     ISR_TXDESC =       0x00000080,
+     ISR_TXOK =         0x00000040,
+     ISR_RXORN =        0x00000020,
+     ISR_RXIDLE =       0x00000010,
+     ISR_RXEARLY =      0x00000008,
+     ISR_RXERR =        0x00000004,
+     ISR_RXDESC =       0x00000002,
+     ISR_RXOK =         0x00000001,
+     ISR_ALL =          0x7FFFFFFF,
+     ISR_DELAY =        (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|
+                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
+     ISR_NODELAY =      (ISR_ALL & ~ISR_DELAY),
+     ISR_IMPL =         (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN|
+                         ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
+     ISR_NOIMPL =       (ISR_ALL & ~ISR_IMPL)
+};
 
 /* transmit configuration register */
-#define TX_CFG_CSI	0x80000000
-#define TX_CFG_HBI	0x40000000
-#define TX_CFG_MLB	0x20000000
-#define TX_CFG_ATP	0x10000000
-#define TX_CFG_ECRETRY	0x00800000
-#define TX_CFG_BRST_DIS	0x00080000
-#define TX_CFG_MXDMA1024	0x00000000
-#define TX_CFG_MXDMA512	0x00700000
-#define TX_CFG_MXDMA256	0x00600000
-#define TX_CFG_MXDMA128	0x00500000
-#define TX_CFG_MXDMA64	0x00400000
-#define TX_CFG_MXDMA32	0x00300000
-#define TX_CFG_MXDMA16	0x00200000
-#define TX_CFG_MXDMA8	0x00100000
-#define TX_CFG_MXDMA     0x00700000
+enum TransmitConfigurationRegister {
+     TX_CFG_CSI =       0x80000000,
+     TX_CFG_HBI =       0x40000000,
+     TX_CFG_MLB =       0x20000000,
+     TX_CFG_ATP =       0x10000000,
+     TX_CFG_ECRETRY =   0x00800000,
+     TX_CFG_BRST_DIS =  0x00080000,
+     TX_CFG_MXDMA1024 = 0x00000000,
+     TX_CFG_MXDMA512 =  0x00700000,
+     TX_CFG_MXDMA256 =  0x00600000,
+     TX_CFG_MXDMA128 =  0x00500000,
+     TX_CFG_MXDMA64 =   0x00400000,
+     TX_CFG_MXDMA32 =   0x00300000,
+     TX_CFG_MXDMA16 =   0x00200000,
+     TX_CFG_MXDMA8 =    0x00100000,
+     TX_CFG_MXDMA =     0x00700000,
 
-#define TX_CFG_FLTH_MASK 0x0000ff00
-#define TX_CFG_DRTH_MASK 0x000000ff
+     TX_CFG_FLTH_MASK = 0x0000ff00,
+     TX_CFG_DRTH_MASK = 0x000000ff
+};
 
 /*general purpose I/O control register */
-#define GPIOR_UNUSED		0xffff8000
-#define GPIOR_GP5_IN		0x00004000
-#define GPIOR_GP4_IN		0x00002000
-#define GPIOR_GP3_IN		0x00001000
-#define GPIOR_GP2_IN		0x00000800
-#define GPIOR_GP1_IN		0x00000400
-#define GPIOR_GP5_OE		0x00000200
-#define GPIOR_GP4_OE		0x00000100
-#define GPIOR_GP3_OE		0x00000080
-#define GPIOR_GP2_OE		0x00000040
-#define GPIOR_GP1_OE		0x00000020
-#define GPIOR_GP5_OUT		0x00000010
-#define GPIOR_GP4_OUT		0x00000008
-#define GPIOR_GP3_OUT		0x00000004
-#define GPIOR_GP2_OUT		0x00000002
-#define GPIOR_GP1_OUT		0x00000001
+enum GeneralPurposeIOControlRegister {
+     GPIOR_UNUSED =     0xffff8000,
+     GPIOR_GP5_IN =     0x00004000,
+     GPIOR_GP4_IN =     0x00002000,
+     GPIOR_GP3_IN =     0x00001000,
+     GPIOR_GP2_IN =     0x00000800,
+     GPIOR_GP1_IN =     0x00000400,
+     GPIOR_GP5_OE =     0x00000200,
+     GPIOR_GP4_OE =     0x00000100,
+     GPIOR_GP3_OE =     0x00000080,
+     GPIOR_GP2_OE =     0x00000040,
+     GPIOR_GP1_OE =     0x00000020,
+     GPIOR_GP5_OUT =    0x00000010,
+     GPIOR_GP4_OUT =    0x00000008,
+     GPIOR_GP3_OUT =    0x00000004,
+     GPIOR_GP2_OUT =    0x00000002,
+     GPIOR_GP1_OUT =    0x00000001
+};
 
 /* receive configuration register */
-#define RX_CFG_AEP	0x80000000
-#define RX_CFG_ARP	0x40000000
-#define RX_CFG_STRIPCRC	0x20000000
-#define RX_CFG_RX_FD	0x10000000
-#define RX_CFG_ALP	0x08000000
-#define RX_CFG_AIRL	0x04000000
-#define RX_CFG_MXDMA512	0x00700000
-#define RX_CFG_MXDMA     0x00700000
-#define RX_CFG_DRTH	0x0000003e
-#define RX_CFG_DRTH0	0x00000002
+enum ReceiveConfigurationRegister {
+     RX_CFG_AEP =       0x80000000,
+     RX_CFG_ARP =       0x40000000,
+     RX_CFG_STRIPCRC =  0x20000000,
+     RX_CFG_RX_FD =     0x10000000,
+     RX_CFG_ALP =       0x08000000,
+     RX_CFG_AIRL =      0x04000000,
+     RX_CFG_MXDMA512 =  0x00700000,
+     RX_CFG_MXDMA =     0x00700000,
+     RX_CFG_DRTH =      0x0000003e,
+     RX_CFG_DRTH0 =     0x00000002
+};
 
 /* pause control status register */
-#define PCR_PSEN	(1 << 31)
-#define PCR_PS_MCAST	(1 << 30)
-#define PCR_PS_DA	(1 << 29)
-#define PCR_STHI_8	(3 << 23)
-#define PCR_STLO_4	(1 << 23)
-#define PCR_FFHI_8K	(3 << 21)
-#define PCR_FFLO_4K	(1 << 21)
-#define PCR_PAUSE_CNT	0xFFFE
+enum PauseControlStatusRegister {
+     PCR_PSEN =         (1 << 31),
+     PCR_PS_MCAST =     (1 << 30),
+     PCR_PS_DA =        (1 << 29),
+     PCR_STHI_8 =       (3 << 23),
+     PCR_STLO_4 =       (1 << 23),
+     PCR_FFHI_8K =      (3 << 21),
+     PCR_FFLO_4K =      (1 << 21),
+     PCR_PAUSE_CNT =    0xFFFE
+};
 
 /*receive filter/match control register */
-#define RFCR_RFEN	0x80000000
-#define RFCR_AAB	0x40000000
-#define RFCR_AAM	0x20000000
-#define RFCR_AAU	0x10000000
-#define RFCR_APM	0x08000000
-#define RFCR_APAT	0x07800000
-#define RFCR_APAT3	0x04000000
-#define RFCR_APAT2	0x02000000
-#define RFCR_APAT1	0x01000000
-#define RFCR_APAT0	0x00800000
-#define RFCR_AARP	0x00400000
-#define RFCR_MHEN	0x00200000
-#define RFCR_UHEN	0x00100000
-#define RFCR_ULM	0x00080000
-#define RFCR_RFADDR     0x000003ff
+enum ReceiveFilterMatchControlRegister {
+     RFCR_RFEN =        0x80000000,
+     RFCR_AAB =         0x40000000,
+     RFCR_AAM =         0x20000000,
+     RFCR_AAU =         0x10000000,
+     RFCR_APM =         0x08000000,
+     RFCR_APAT =        0x07800000,
+     RFCR_APAT3 =       0x04000000,
+     RFCR_APAT2 =       0x02000000,
+     RFCR_APAT1 =       0x01000000,
+     RFCR_APAT0 =       0x00800000,
+     RFCR_AARP =        0x00400000,
+     RFCR_MHEN =        0x00200000,
+     RFCR_UHEN =        0x00100000,
+     RFCR_ULM =         0x00080000,
+     RFCR_RFADDR =      0x000003ff
+};
 
 /* receive filter/match data register */
-#define RFDR_BMASK      0x00030000
-#define RFDR_RFDATA0    0x000000ff
-#define RFDR_RFDATA1    0x0000ff00
+enum ReceiveFilterMatchDataRegister {
+     RFDR_BMASK =       0x00030000,
+     RFDR_RFDATA0 =     0x000000ff,
+     RFDR_RFDATA1 =     0x0000ff00
+};
 
 /* management information base control register */
-#define MIBC_MIBS	0x00000008
-#define MIBC_ACLR	0x00000004
-#define MIBC_FRZ	0x00000002
-#define MIBC_WRN	0x00000001
+enum ManagementInformationBaseControlRegister {
+     MIBC_MIBS =        0x00000008,
+     MIBC_ACLR =        0x00000004,
+     MIBC_FRZ =         0x00000002,
+     MIBC_WRN =         0x00000001
+};
 
 /* VLAN/IP receive control register */
-#define VRCR_RUDPE	0x00000080
-#define VRCR_RTCPE	0x00000040
-#define VRCR_RIPE	0x00000020
-#define VRCR_IPEN	0x00000010
-#define VRCR_DUTF	0x00000008
-#define VRCR_DVTF	0x00000004
-#define VRCR_VTREN	0x00000002
-#define VRCR_VTDEN	0x00000001
+enum VLANIPReceiveControlRegister {
+     VRCR_RUDPE =       0x00000080,
+     VRCR_RTCPE =       0x00000040,
+     VRCR_RIPE =        0x00000020,
+     VRCR_IPEN =        0x00000010,
+     VRCR_DUTF =        0x00000008,
+     VRCR_DVTF =        0x00000004,
+     VRCR_VTREN =       0x00000002,
+     VRCR_VTDEN =       0x00000001
+};
 
 /* VLAN/IP transmit control register */
-#define VTCR_PPCHK	0x00000008
-#define VTCR_GCHK	0x00000004
-#define VTCR_VPPTI	0x00000002
-#define VTCR_VGTI	0x00000001
+enum VLANIPTransmitControlRegister {
+     VTCR_PPCHK =       0x00000008,
+     VTCR_GCHK =        0x00000004,
+     VTCR_VPPTI =       0x00000002,
+     VTCR_VGTI =        0x00000001
+};
 
 /* Clockrun Control/Status Register */
-#define CCSR_CLKRUN_EN  0x00000001
+enum ClockrunControlStatusRegister {
+     CCSR_CLKRUN_EN =   0x00000001
+};
 
 /* TBI control register */
-#define TBICR_MR_LOOPBACK       0x00004000
-#define TBICR_MR_AN_ENABLE	0x00001000
-#define TBICR_MR_RESTART_AN	0x00000200
+enum TBIControlRegister {
+     TBICR_MR_LOOPBACK =        0x00004000,
+     TBICR_MR_AN_ENABLE =       0x00001000,
+     TBICR_MR_RESTART_AN =      0x00000200
+};
 
 /* TBI status register */
-#define TBISR_MR_LINK_STATUS	0x00000020
-#define TBISR_MR_AN_COMPLETE	0x00000004
+enum TBIStatusRegister {
+     TBISR_MR_LINK_STATUS =     0x00000020,
+     TBISR_MR_AN_COMPLETE =     0x00000004
+};
 
 /* TBI auto-negotiation advertisement register */
-#define TANAR_NP		0x00008000
-#define TANAR_RF2		0x00002000
-#define TANAR_RF1		0x00001000
-#define TANAR_PS2 		0x00000100
-#define TANAR_PS1 		0x00000080
-#define TANAR_HALF_DUP		0x00000040
-#define TANAR_FULL_DUP		0x00000020
-#define TANAR_UNUSED		0x00000E1F
+enum TBIAutoNegotiationAdvertisementRegister {
+     TANAR_NP =         0x00008000,
+     TANAR_RF2 =        0x00002000,
+     TANAR_RF1 =        0x00001000,
+     TANAR_PS2 =        0x00000100,
+     TANAR_PS1 =        0x00000080,
+     TANAR_HALF_DUP =   0x00000040,
+     TANAR_FULL_DUP =   0x00000020,
+     TANAR_UNUSED =     0x00000E1F
+};
 
 /* M5 control register */
-#define M5REG_RESERVED		0xfffffffc
-#define M5REG_RSS		0x00000004
-#define M5REG_RX_THREAD		0x00000002
-#define M5REG_TX_THREAD		0x00000001
+enum M5ControlRegister {
+     M5REG_RESERVED =   0xfffffffc,
+     M5REG_RSS =        0x00000004,
+     M5REG_RX_THREAD =  0x00000002,
+     M5REG_TX_THREAD =  0x00000001
+};
 
 struct ns_desc32 {
     uint32_t link;    /* link field to next descriptor in linked list */
@@ -327,27 +367,35 @@ struct ns_desc64 {
 };
 
 /* cmdsts flags for descriptors */
-#define CMDSTS_OWN	0x80000000
-#define CMDSTS_MORE	0x40000000
-#define CMDSTS_INTR	0x20000000
-#define CMDSTS_ERR	0x10000000
-#define CMDSTS_OK	0x08000000
-#define CMDSTS_LEN_MASK	0x0000ffff
+enum CMDSTSFlatsForDescriptors {
+     CMDSTS_OWN =       0x80000000,
+     CMDSTS_MORE =      0x40000000,
+     CMDSTS_INTR =      0x20000000,
+     CMDSTS_ERR =       0x10000000,
+     CMDSTS_OK =        0x08000000,
+     CMDSTS_LEN_MASK =  0x0000ffff,
 
-#define CMDSTS_DEST_MASK	0x01800000
-#define CMDSTS_DEST_SELF	0x00800000
-#define CMDSTS_DEST_MULTI	0x01000000
+     CMDSTS_DEST_MASK = 0x01800000,
+     CMDSTS_DEST_SELF = 0x00800000,
+     CMDSTS_DEST_MULTI = 0x01000000
+};
 
 /* extended flags for descriptors */
-#define EXTSTS_UDPERR   0x00400000
-#define EXTSTS_UDPPKT	0x00200000
-#define EXTSTS_TCPERR   0x00100000
-#define EXTSTS_TCPPKT	0x00080000
-#define EXTSTS_IPERR    0x00040000
-#define EXTSTS_IPPKT	0x00020000
-
+enum ExtendedFlagsForDescriptors {
+     EXTSTS_UDPERR =    0x00400000,
+     EXTSTS_UDPPKT =    0x00200000,
+     EXTSTS_TCPERR =    0x00100000,
+     EXTSTS_TCPPKT =    0x00080000,
+     EXTSTS_IPERR =     0x00040000,
+     EXTSTS_IPPKT =     0x00020000
+};
 
 /* speed status */
-#define SPDSTS_POLARITY	(CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0))
+static inline int
+SPDSTS_POLARITY(int lnksts)
+{
+    return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
+            (lnksts ? CFGR_LNKSTS : 0));
+}
 
 #endif /* __DEV_NS_GIGE_REG_H__ */