Remove unused functions/comments cluttering up the code.

13 files changed, 14 insertions, 159 deletions

diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index dc5ff6f46..a987c4e05 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -47,7 +47,7 @@ if 'InOrderCPU' in env['CPU_MODELS']:
 	TraceFlag('RefCount')
 
 	CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
-	       'InOrderMDU', 'RegDepMap', 'Resource'])
+	       'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource'])
 
 	Source('pipeline_traits.cc')        
 	Source('inorder_dyn_inst.cc')
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 9c957487d..7dafd826f 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -46,7 +46,6 @@
 #include "cpu/inorder/resource_pool.hh"
 #include "mem/translating_port.hh"
 #include "sim/process.hh"
-//#include "sim/root.hh"
 #include "sim/stat_control.hh"
 #include <algorithm>
 
@@ -162,7 +161,6 @@ InOrderCPU::InOrderCPU(Params *params)
     cpu_params = params;
 
     resPool = new ResourcePool(this, params);
-//    resPool->init();
 
     coreType = "default"; // eventually get this from params
 
@@ -191,13 +189,9 @@ InOrderCPU::InOrderCPU(Params *params)
     }
 
 
-    /* Use this port to for syscall emulation writes to memory. */
-    //Port *mem_port = NULL;
-    //TranslatingPort *trans_port = NULL;
-
     for (int i = 0; i < numThreads; ++i) {
         if (i < params->workload.size()) {
-            DPRINTF(InOrderCPU, "Workload[%i] process is %#x",
+            DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
                     i, this->thread[i]);
             this->thread[i] = new Thread(this, i, params->workload[i],
                                          i);
@@ -208,11 +202,8 @@ InOrderCPU::InOrderCPU(Params *params)
         } else {
             //Allocate Empty thread so M5 can use later
             //when scheduling threads to CPU
-            Process* dummy_proc = params->workload[0]; //LiveProcess::createDummy();
+            Process* dummy_proc = params->workload[0];
             this->thread[i] = new Thread(this, i, dummy_proc, i);
-
-            // Set Up Syscall Emulation Port
-            //this->thread[i]->setMemPort(trans_port);
         }
 
         // Setup the TC that will serve as the interface to the threads/CPU.
@@ -790,8 +781,6 @@ InOrderCPU::deallocateThread(unsigned tid)
 {
     DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid);
 
-    //removeThread(tid);
-
     removeFromCurrentThreads(tid);
 
     deactivateThread(tid);
@@ -840,19 +829,6 @@ InOrderCPU::activateWhenReady(int tid)
 }
 
 
-void
-InOrderCPU::signalSwitched()
-{
-    panic("Unimplemented Function\n.");
-}
-
-
-void
-InOrderCPU::takeOverFrom(BaseCPU *oldCPU)
-{
-    panic("Take Over From Another CPU\n.");
-}
-
 uint64_t
 InOrderCPU::readPC(unsigned tid)
 {
@@ -1205,14 +1181,6 @@ InOrderCPU::cleanUpRemovedEvents()
     }
 }
 
-/*
-
-void
-InOrderCPU::removeAllInsts()
-{
-    instList.clear();
-}
-*/
 
 void
 InOrderCPU::dumpInsts()
@@ -1233,14 +1201,6 @@ InOrderCPU::dumpInsts()
         ++num;
     }
 }
-/*
-
-void
-InOrderCPU::wakeDependents(DynInstPtr &inst)
-{
-    iew.wakeDependents(inst);
-}
-*/
 
 void
 InOrderCPU::wakeCPU()
@@ -1252,6 +1212,7 @@ InOrderCPU::wakeCPU()
 
     DPRINTF(Activity, "Waking up CPU\n");
 
+    //@todo: figure out how to count idleCycles correctly
     //idleCycles += (curTick - 1) - lastRunningCycle;
 
     mainEventQueue.schedule(&tickEvent, curTick);
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index e27687a72..36c90a0e9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -249,9 +249,6 @@ class InOrderCPU : public BaseCPU
     TheISA::IntReg nextNPC[ThePipeline::MaxThreads];
 
     /** The Register File for the CPU */
-    /** @TODO: This regFile wont be a sufficient solution for out-of-order, add register
-     *  files as a resource in order to handle ths problem
-     */
     TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
     TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
     TheISA::MiscRegFile miscRegFile;
@@ -362,15 +359,6 @@ class InOrderCPU : public BaseCPU
     void switchToActive(int stage_idx)
     { /*pipelineStage[stage_idx]->switchToActive();*/ }
 
-    /** Switches out this CPU. (Unused currently) */
-    //void switchOut(Sampler *sampler);
-
-    /** Signals to this CPU that a stage has completed switching out. (Unused currently)*/
-    void signalSwitched();
-
-    /** Takes over from another CPU. (Unused currently)*/
-    void takeOverFrom(BaseCPU *oldCPU);
-
     /** Get the current instruction sequence number, and increment it. */
     InstSeqNum getAndIncrementInstSeq(unsigned tid)
     { return globalSeqNum[tid]++; }
@@ -389,6 +377,7 @@ class InOrderCPU : public BaseCPU
         globalSeqNum[tid] = seq_num;
     }
 
+    /** Get & Update Next Event Number */
     InstSeqNum getNextEventNum()
     {
         return cpuEventNum++;
@@ -463,9 +452,6 @@ class InOrderCPU : public BaseCPU
     /** Sets the next NPC of a specific thread. */
     void setNextNPC(uint64_t val, unsigned tid);
 
-    /** Add Destination Register To Dependency Maps */
-    //void addToRegDepMap(DynInstPtr &inst);
-
     /** Function to add instruction onto the head of the list of the
      *  instructions.  Used when new instructions are fetched.
      */
@@ -530,13 +516,6 @@ class InOrderCPU : public BaseCPU
      */
     std::queue<Event*> cpuEventRemoveList;
 
-#ifdef DEBUG
-    /** Debug structure to keep track of the sequence numbers still in
-     * flight.
-     */
-    std::set<InstSeqNum> snList;
-#endif
-
     /** Records if instructions need to be removed this cycle due to
      *  being retired or squashed.
      */
@@ -610,7 +589,6 @@ class InOrderCPU : public BaseCPU
     unsigned readStCondFailures() { return stCondFails; }
     unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; }
 
-  public:
     /** Returns a pointer to a thread context. */
     ThreadContext *tcBase(unsigned tid = 0)
     {
@@ -631,6 +609,7 @@ class InOrderCPU : public BaseCPU
 
     /** Pointer to the icache interface. */
     MemInterface *icacheInterface;
+
     /** Pointer to the dcache interface. */
     MemInterface *dcacheInterface;
 
diff --git a/src/cpu/inorder/inorder_cpu_builder.cc b/src/cpu/inorder/inorder_cpu_builder.cc
index b1b4bea80..0088a3bd9 100644
--- a/src/cpu/inorder/inorder_cpu_builder.cc
+++ b/src/cpu/inorder/inorder_cpu_builder.cc
@@ -35,7 +35,6 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/inorder/cpu.hh"
-//#include "cpu/inorder/params.hh"
 #include "cpu/inorder/inorder_dyn_inst.hh"
 #include "cpu/inorder/pipeline_traits.hh"
 #include "params/InOrderCPU.hh"
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index e5fac7141..d292d72f0 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -167,10 +167,6 @@ InOrderDynInst::initVars()
 
     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n",
             threadNumber, seqNum, instcount);
-
-#ifdef DEBUG
-    cpu->snList.insert(seqNum);
-#endif
 }
 
 
@@ -192,9 +188,6 @@ InOrderDynInst::~InOrderDynInst()
 
     DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n",
             threadNumber, seqNum, instcount);
-#ifdef DEBUG
-    cpu->snList.erase(seqNum);
-#endif
 }
 
 void
@@ -305,44 +298,13 @@ InOrderDynInst::syscall(int64_t callnum)
 void
 InOrderDynInst::prefetch(Addr addr, unsigned flags)
 {
-    // This is the "functional" implementation of prefetch.  Not much
-    // happens here since prefetches don't affect the architectural
-    // state.
-/*
-    // Generate a MemReq so we can translate the effective address.
-    MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags);
-    req->asid = asid;
-
-    // Prefetches never cause faults.
-    fault = NoFault;
-
-    // note this is a local, not InOrderDynInst::fault
-    Fault trans_fault = cpu->translateDataReadReq(req);
-
-    if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) {
-        // It's a valid address to cacheable space.  Record key MemReq
-        // parameters so we can generate another one just like it for
-        // the timing access without calling translate() again (which
-        // might mess up the TLB).
-        effAddr = req->vaddr;
-        physEffAddr = req->paddr;
-        memReqFlags = req->flags;
-    } else {
-        // Bogus address (invalid or uncacheable space).  Mark it by
-        // setting the eff_addr to InvalidAddr.
-        effAddr = physEffAddr = MemReq::inval_addr;
-    }
-
-    if (traceData) {
-        traceData->setAddr(addr);
-    }
-*/
+    panic("Prefetch Unimplemented\n");
 }
 
 void
 InOrderDynInst::writeHint(Addr addr, int size, unsigned flags)
 {
-    // Not currently supported.
+    panic("Write-Hint Unimplemented\n");
 }
 
 /**
@@ -762,20 +724,3 @@ my_hash_t;
 
 my_hash_t thishash;
 #endif
-
-#ifdef DEBUG
-
-void
-InOrderDynInst::dumpSNList()
-{
-    std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin();
-
-    int count = 0;
-    while (sn_it != cpu->snList.end()) {
-        cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it));
-        count++;
-        sn_it++;
-    }
-}
-#endif
-
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 9f52f954f..55c61ffb9 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -957,10 +957,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
     /** Count of total number of dynamic instructions. */
     static int instcount;
 
-#ifdef DEBUG
-    void dumpSNList();
-#endif
-
     /** Dumps out contents of this BaseDynInst. */
     void dump();
 
diff --git a/src/cpu/inorder/params.hh b/src/cpu/inorder/params.hh
index 67f8f47f0..51b7409ad 100644
--- a/src/cpu/inorder/params.hh
+++ b/src/cpu/inorder/params.hh
@@ -121,4 +121,4 @@ class InOrderParams : public BaseCPU::Params
 
 };
 
-#endif // __CPU_O3_CPU_INORDER_PARAMS_HH__
+#endif // _CPU_INORDER_PARAMS_HH__
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index 1c8da2b13..ab7328f4a 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -193,7 +193,7 @@ void
 PipelineStage::switchOut()
 {
     // Stage can immediately switch out.
-    cpu->signalSwitched();
+    panic("Switching Out of Stages Unimplemented");
 }
 
 
@@ -691,13 +691,6 @@ PipelineStage::tick()
     DPRINTF(InOrderStage, "\n\n");
 }
 
-bool
-PipelineStage::outOfOrderValid()
-{
-    //@TODO: Define this function when OOO is valid
-    return false;
-}
-
 void
 PipelineStage::setResStall(ResReqPtr res_req, unsigned tid)
 {
@@ -861,7 +854,7 @@ PipelineStage::processInsts(unsigned tid)
 
         // Don't let instruction pass to next stage if it hasnt completed
         // all of it's requests for this stage.
-        if (!last_req_completed && !outOfOrderValid())
+        if (!last_req_completed)
             continue;
 
         // Send to Next Stage or Break Loop
@@ -1018,7 +1011,7 @@ PipelineStage::sendInstToNextStage(DynInstPtr inst)
 void
 PipelineStage::dumpInsts()
 {
-    std::cerr << "Insts in Stage " << stageNum << " skidbuffers:" << endl;
+    cprintf("Insts in Stage %i skidbuffers\n",stageNum);
 
     for (int tid=0; tid < ThePipeline::MaxThreads; tid++) {
 
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh
index 17ca32595..19bf8154f 100644
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -147,9 +147,6 @@ class PipelineStage
      */
     virtual void tick();
 
-    /** Is out of order processing valid? */
-    bool outOfOrderValid();
-
     /** Set a resource stall in the pipeline-stage */
     void setResStall(ResReqPtr res_req, unsigned tid);
 
diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh
index c5e4bb228..3c49143bc 100644
--- a/src/cpu/inorder/pipeline_traits.hh
+++ b/src/cpu/inorder/pipeline_traits.hh
@@ -38,7 +38,6 @@
 
 #include "arch/isa_traits.hh"
 #include "cpu/base.hh"
-//#include "cpu/inorder/params.hh"
 
 #include "params/InOrderCPU.hh"
 
@@ -122,12 +121,6 @@ namespace ThePipeline {
             if (lhs->stageNum > rhs->stageNum) {
                 return true;
             } else if (lhs->stageNum == rhs->stageNum) {
-                /*if (lhs->resNum > rhs->resNum) {
-                  return true;
-                } else {
-                  return false;
-                  }*/
-
                 if (lhs->priority > rhs->priority) {
                   return true;
                 } else {
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index e3536258d..9b9e3c3dc 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -79,9 +79,6 @@ class Resource {
     virtual void init();    
     virtual void initSlots();
 
-    /** Tasks to perform when simulation starts */
-    //virtual void startup() { }
-
     /** Register Stats for this resource */
     virtual void regStats();
 
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 6b62c864a..6fd7ae36c 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -454,12 +454,10 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
         findRequest(cache_pkt->cacheReq->getInst()));
     assert(cache_req);
 
-#if TRACING_ON
+
     // Get resource request info
+    // @todo: SMT needs to figure out where to get thread # from.
     unsigned tid = 0;
-#endif
-
-    //tid = pkt->req->getThreadNum();
     unsigned stage_num = cache_req->getStageNum();
     DynInstPtr inst = cache_req->inst;
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index dce150b47..8b3b47290 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -111,9 +111,6 @@ class InOrderThreadContext : public ThreadContext
     virtual void setStatus(Status new_status)
     { thread->setStatus(new_status); }
 
-    /** Returns a pointer to the last graduated/committed instruction in the thread */
-    //DynInstPtr getLastGradInst() { return thread->getLastGradInst(); }
-
     /** Set the status to Active.  Optional delay indicates number of
      * cycles to wait before beginning execution. */
     virtual void activate(int delay = 1);