summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
committerMitch Hayenga <mitch.hayenga@arm.com>2015-09-30 11:14:19 -0500
commit52d521e4337995d417b6f7b68644959edcc0c6b4 (patch)
tree9ca1e0e33ef7bced4c041b1ef8813c14d46822a1 /src
parentc05d268cfabbe26d032d73abcea6dc921c49e549 (diff)
downloadgem5-52d521e4337995d417b6f7b68644959edcc0c6b4.tar.xz
cpu: Change thread assignments for heterogenous SMT
Trying to run an SE system with varying threads per core (SMT cores + Non-SMT cores) caused failures due to the CPU id assignment logic. The comment about thread assignment (worrying about core 0 not having tid 0) seems not to be valid given that our configuration scripts initialize them in order. This removes that constraint so a heterogenously threaded sytem can work.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/base.cc16
-rw-r--r--src/sim/System.py3
-rw-r--r--src/sim/system.cc1
-rw-r--r--src/sim/system.hh1
4 files changed, 11 insertions, 10 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index eb5cadfcc..77ac5f2bb 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -436,21 +436,17 @@ BaseCPU::getMasterPort(const string &if_name, PortID idx)
void
BaseCPU::registerThreadContexts()
{
+ assert(system->multiThread || numThreads == 1);
+
ThreadID size = threadContexts.size();
for (ThreadID tid = 0; tid < size; ++tid) {
ThreadContext *tc = threadContexts[tid];
- /** This is so that contextId and cpuId match where there is a
- * 1cpu:1context relationship. Otherwise, the order of registration
- * could affect the assignment and cpu 1 could have context id 3, for
- * example. We may even want to do something like this for SMT so that
- * cpu 0 has the lowest thread contexts and cpu N has the highest, but
- * I'll just do this for now
- */
- if (numThreads == 1)
- tc->setContextId(system->registerThreadContext(tc, _cpuId));
- else
+ if (system->multiThread) {
tc->setContextId(system->registerThreadContext(tc));
+ } else {
+ tc->setContextId(system->registerThreadContext(tc, _cpuId));
+ }
if (!FullSystem)
tc->getProcessPtr()->assignThreadContext(tc->contextId());
diff --git a/src/sim/System.py b/src/sim/System.py
index e24a1e6b2..74dfdca53 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -99,6 +99,9 @@ class System(MemObject):
"Address to mask loading binaries with")
load_offset = Param.UInt64(0, "Address to offset loading binaries with")
+ multi_thread = Param.Bool(False,
+ "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
+
# Dynamic voltage and frequency handler for the system, disabled by default
# Provide list of domains that need to be controlled by the handler
dvfs_handler = DVFSHandler()
diff --git a/src/sim/system.cc b/src/sim/system.cc
index d0418d99b..2e74d01c8 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -80,6 +80,7 @@ int System::numSystemsRunning = 0;
System::System(Params *p)
: MemObject(p), _systemPort("system_port", this),
_numContexts(0),
+ multiThread(p->multi_thread),
pagePtr(0),
init_param(p->init_param),
physProxy(_systemPort, p->cache_line_size),
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 634c78a6a..82096826d 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -196,6 +196,7 @@ class System : public MemObject
std::vector<ThreadContext *> threadContexts;
int _numContexts;
+ const bool multiThread;
ThreadContext *getThreadContext(ContextID tid)
{