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author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-13 17:52:24 -0500 |
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committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-12-13 17:52:24 -0500 |
commit | a10eff03a529ef79ac9481188cdaf01b269efe16 (patch) | |
tree | bb21ad6e6dd4db8366e8c5555a26a54aee9c7e6b /src | |
parent | 0fa30e579edace72b923bd0dde4e687d43c5fbad (diff) | |
parent | 98bb1c62b31e988f81d9fc03cf14aca25fd008db (diff) | |
download | gem5-a10eff03a529ef79ac9481188cdaf01b269efe16.tar.xz |
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision : 8cf3e824e4892249b12ed0fd92bb310748b18fa2
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/alpha/miscregfile.cc | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/src/arch/alpha/miscregfile.cc b/src/arch/alpha/miscregfile.cc index 962d4609f..67f6c98e4 100644 --- a/src/arch/alpha/miscregfile.cc +++ b/src/arch/alpha/miscregfile.cc @@ -89,12 +89,26 @@ namespace AlphaISA MiscReg MiscRegFile::readRegWithEffect(int misc_reg, ThreadContext *tc) { + switch(misc_reg) { + case MISCREG_FPCR: + return fpcr; + case MISCREG_UNIQ: + return uniq; + case MISCREG_LOCKFLAG: + return lock_flag; + case MISCREG_LOCKADDR: + return lock_addr; + case MISCREG_INTR: + return intr_flag; #if FULL_SYSTEM - return readIpr(misc_reg, tc); + default: + return readIpr(misc_reg, tc); #else - panic("No faulting misc regs in SE mode!"); - return 0; + default: + panic("No faulting misc regs in SE mode!"); + return 0; #endif + } } void |