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authorAli Saidi <saidi@eecs.umich.edu>2008-04-08 11:08:26 -0400
committerAli Saidi <saidi@eecs.umich.edu>2008-04-08 11:08:26 -0400
commited27c4c52183d9527a0c123b9be84bbe968f4afa (patch)
tree6a7ece11798f1c8f67d142e317c10861b150d786 /src
parentbee4d454e84c12e96e7b929e5a9abefa2ae6746a (diff)
downloadgem5-ed27c4c52183d9527a0c123b9be84bbe968f4afa.tar.xz
SCons: Manually specifying header only directories with Dir() works around the problem
--HG-- extra : convert_revision : d9713228d934cf4a45114a972603b8bca2bd27d3
Diffstat (limited to 'src')
-rw-r--r--src/cpu/SConscript2
-rw-r--r--src/mem/SConscript2
2 files changed, 4 insertions, 0 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index c7d0c33bd..2abddef22 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -148,6 +148,8 @@ if env['USE_CHECKER']:
print i,
print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
+else:
+ Dir('checker')
TraceFlag('Activity')
TraceFlag('Commit')
diff --git a/src/mem/SConscript b/src/mem/SConscript
index b572f703c..0fdf9f9bb 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -35,6 +35,8 @@ SimObject('Bus.py')
SimObject('PhysicalMemory.py')
SimObject('MemObject.py')
+Dir('config')
+
Source('bridge.cc')
Source('bus.cc')
Source('dram.cc')