Merge python and x86 changes with cache branch

--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233

168 files changed, 3470 insertions, 7022 deletions

diff --git a/src/SConscript b/src/SConscript
index 7a3b25c92..1cd1a1627 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -26,14 +26,17 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Nathan Binkert
 
+import imp
 import os
 import sys
-import zipfile
 
 from os.path import basename
 from os.path import join as joinpath
+from os.path import exists
+from os.path import isdir
+from os.path import isfile
 
 import SCons
 
@@ -45,47 +48,87 @@ Import('*')
 # Children need to see the environment
 Export('env')
 
+def sort_list(_list):
+    """return a sorted copy of '_list'"""
+    if isinstance(_list, list):
+        _list = _list[:]
+    else:
+        _list = list(_list)
+    _list.sort()
+    return _list
+
+class PySourceFile(object):
+    def __init__(self, package, source):
+        filename = str(source)
+        pyname = basename(filename)
+        assert pyname.endswith('.py')
+        name = pyname[:-3]
+        path = package.split('.')
+        modpath = path
+        if name != '__init__':
+            modpath += [name]
+        modpath = '.'.join(modpath)
+
+        arcpath = package.split('.') + [ pyname + 'c' ]
+        arcname = joinpath(*arcpath)
+
+        self.source = source
+        self.pyname = pyname
+        self.srcpath = source.srcnode().abspath
+        self.package = package
+        self.modpath = modpath
+        self.arcname = arcname
+        self.filename = filename
+        self.compiled = File(filename + 'c')
+
 ########################################################################
-# Code for adding source files
+# Code for adding source files of various types
 #
-sources = []
+cc_sources = []
 def Source(source):
-    if isinstance(source, SCons.Node.FS.File):
-        sources.append(source)
-    else:
-        sources.append(File(source))
+    '''Add a C/C++ source file to the build'''
+    if not isinstance(source, SCons.Node.FS.File):
+        source = File(source)
 
-# Children should have access
-Export('Source')
+    cc_sources.append(source)
 
-########################################################################
-# Code for adding python objects
-#
 py_sources = []
-py_source_packages = {}
 def PySource(package, source):
+    '''Add a python source file to the named package'''
     if not isinstance(source, SCons.Node.FS.File):
         source = File(source)
-    py_source_packages[source] = package
+
+    source = PySourceFile(package, source)
     py_sources.append(source)
 
-sim_objects = []
+sim_objects_fixed = False
+sim_object_modfiles = set()
 def SimObject(source):
+    '''Add a SimObject python file as a python source object and add
+    it to a list of sim object modules'''
+
+    if sim_objects_fixed:
+        raise AttributeError, "Too late to call SimObject now."
+
     if not isinstance(source, SCons.Node.FS.File):
         source = File(source)
+
     PySource('m5.objects', source)
-    modname = basename(str(source))
-    sim_objects.append(modname)
+    modfile = basename(str(source))
+    assert modfile.endswith('.py')
+    modname = modfile[:-3]
+    sim_object_modfiles.add(modname)
 
 swig_sources = []
-swig_source_packages = {}
 def SwigSource(package, source):
+    '''Add a swig file to build'''
     if not isinstance(source, SCons.Node.FS.File):
         source = File(source)
-    swig_source_packages[source] = package
-    swig_sources.append(source)
+    val = source,package
+    swig_sources.append(val)
 
 # Children should have access
+Export('Source')
 Export('PySource')
 Export('SimObject')
 Export('SwigSource')
@@ -105,140 +148,177 @@ env.Append(CPPPATH=Dir('.'))
 env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
 
 ########################################################################
+#
 # Walk the tree and execute all SConscripts
 #
-scripts = []
 srcdir = env['SRCDIR']
 for root, dirs, files in os.walk(srcdir, topdown=True):
     if root == srcdir:
         # we don't want to recurse back into this SConscript
         continue
-    
+
     if 'SConscript' in files:
         # strip off the srcdir part since scons will try to find the
         # script in the build directory
         base = root[len(srcdir) + 1:]
         SConscript(joinpath(base, 'SConscript'))
 
+for extra in env['EXTRAS'].split(':'):
+    extra = os.path.expanduser(extra)
+    env.Append(CPPPATH=[Dir(extra)])
+    for root, dirs, files in os.walk(extra, topdown=True):
+        if 'SConscript' in files:
+            subdir = root[len(os.path.dirname(extra))+1:]
+            build_dir = joinpath(env['BUILDDIR'], subdir)
+            SConscript(joinpath(root, 'SConscript'), build_dir=build_dir)
+
 for opt in env.ExportOptions:
     env.ConfigFile(opt)
 
 ########################################################################
 #
-# Deal with python/swig, object code.  Collect .py files and
-# generating a zip archive that is appended to the m5 binary.
+# Prevent any SimObjects from being added after this point, they
+# should all have been added in the SConscripts above
 #
+sim_objects_fixed = True
 
-# Generate Python file that contains a dict specifying the current
-# build_env flags.
-def MakeDefinesPyFile(target, source, env):
-    f = file(str(target[0]), 'w')
-    print >>f, "m5_build_env = ", source[0]
-    f.close()
+########################################################################
+#
+# Manually turn python/generate.py into a python module and import it
+#
+generate_file = File('python/generate.py')
+generate_module = imp.new_module('generate')
+sys.modules['generate'] = generate_module
+exec file(generate_file.srcnode().abspath, 'r') in generate_module.__dict__
 
+########################################################################
+#
+# build a generate
+#
+from generate import Generate
 optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
-env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile)
-PySource('m5', 'python/m5/defines.py')
+generate = Generate(py_sources, sim_object_modfiles, optionDict)
+m5 = generate.m5
 
-def MakeInfoPyFile(target, source, env):
-    f = file(str(target[0]), 'w')
-    for src in source:
-        data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
-        print >>f, "%s = %s" % (src, repr(data))
-    f.close()
+########################################################################
+#
+# calculate extra dependencies
+#
+module_depends = ["m5", "m5.SimObject", "m5.params"]
+module_depends = [ File(generate.py_modules[dep]) for dep in module_depends ]
+file_depends = [ generate_file ]
+depends = module_depends + file_depends
+
+########################################################################
+#
+# Commands for the basic automatically generated python files
+#
+
+# Generate a file with all of the compile options in it
+env.Command('python/m5/defines.py', Value(optionDict),
+            generate.makeDefinesPyFile)
+PySource('m5', 'python/m5/defines.py')
 
+# Generate a file that wraps the basic top level files
 env.Command('python/m5/info.py',
             [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
-            MakeInfoPyFile)
+            generate.makeInfoPyFile)
 PySource('m5', 'python/m5/info.py')
 
-def MakeObjectsInitFile(target, source, env):
-    f = file(str(target[0]), 'w')
-    print >>f, 'from m5.SimObject import *'
-    for src_path in source:
-        src_file = basename(src_path.get_contents())
-        assert(src_file.endswith('.py'))
-        src_module = src_file[:-3]
-        print >>f, 'from %s import *' % src_module
-    f.close()
-
+# Generate an __init__.py file for the objects package
 env.Command('python/m5/objects/__init__.py',
-            [ Value(o) for o in sim_objects],
-            MakeObjectsInitFile)
+            [ Value(o) for o in sort_list(sim_object_modfiles) ],
+            generate.makeObjectsInitFile)
 PySource('m5.objects', 'python/m5/objects/__init__.py')
 
+########################################################################
+#
+# Create all of the SimObject param headers and enum headers
+#
+
+# Generate all of the SimObject param struct header files
+params_hh_files = []
+for name,simobj in generate.sim_objects.iteritems():
+    extra_deps = [ File(generate.py_modules[simobj.__module__]) ]
+
+    hh_file = File('params/%s.hh' % name)
+    params_hh_files.append(hh_file)
+    env.Command(hh_file, Value(name), generate.createSimObjectParam)
+    env.Depends(hh_file, depends + extra_deps)
+
+# Generate any parameter header files needed
+for name,param in generate.params.iteritems():
+    if isinstance(param, m5.params.VectorParamDesc):
+        ext = 'vptype'
+    else:
+        ext = 'ptype'
+
+    i_file = File('params/%s_%s.i' % (name, ext))
+    env.Command(i_file, Value(name), generate.createSwigParam)
+    env.Depends(i_file, depends)
+
+# Generate all enum header files
+for name,enum in generate.enums.iteritems():
+    extra_deps = [ File(generate.py_modules[enum.__module__]) ]
+
+    cc_file = File('enums/%s.cc' % name)
+    env.Command(cc_file, Value(name), generate.createEnumStrings)
+    env.Depends(cc_file, depends + extra_deps)
+    Source(cc_file)
+
+    hh_file = File('enums/%s.hh' % name)
+    env.Command(hh_file, Value(name), generate.createEnumParam)
+    env.Depends(hh_file, depends + extra_deps)
+
+# Build the big monolithic swigged params module (wraps all SimObject
+# param structs and enum structs)
+params_file = File('params/params.i')
+names = sort_list(generate.sim_objects.keys())
+env.Command(params_file, [ Value(v) for v in names ],
+            generate.buildParams)
+env.Depends(params_file, params_hh_files + depends)
+SwigSource('m5.objects', params_file)
+
+# Build all swig modules
 swig_modules = []
-for source in swig_sources:
-    source.rfile() # Hack to cause the symlink to the .i file to be created
-    package = swig_source_packages[source]
+for source,package in swig_sources:
     filename = str(source)
-    module = basename(filename)
+    assert filename.endswith('.i')
 
-    assert(module.endswith('.i'))
-    module = module[:-2]
-    cc_file = 'swig/%s_wrap.cc' % module
-    py_file = 'm5/internal/%s.py' % module
+    base = '.'.join(filename.split('.')[:-1])
+    module = basename(base)
+    cc_file = base + '_wrap.cc'
+    py_file = base + '.py'
 
     env.Command([cc_file, py_file], source,
                 '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
                 '-o ${TARGETS[0]} $SOURCES')
     env.Depends(py_file, source)
     env.Depends(cc_file, source)
-                
+
     swig_modules.append(Value(module))
     Source(cc_file)
     PySource(package, py_file)
 
-def MakeSwigInit(target, source, env):
-    f = file(str(target[0]), 'w')
-    print >>f, 'extern "C" {'
-    for module in source:
-        print >>f, '    void init_%s();' % module.get_contents()
-    print >>f, '}'
-    print >>f, 'void init_swig() {'
-    for module in source:
-        print >>f, '    init_%s();' % module.get_contents()
-    print >>f, '}'
-    f.close()
-env.Command('python/swig/init.cc', swig_modules, MakeSwigInit)
-
-def CompilePyFile(target, source, env):
-    import py_compile
-    py_compile.compile(str(source[0]), str(target[0]))
+# Generate the main swig init file
+env.Command('swig/init.cc', swig_modules, generate.makeSwigInit)
+Source('swig/init.cc')
 
+# Build the zip file
 py_compiled = []
-py_arcname = {}
 py_zip_depends = []
 for source in py_sources:
-    filename = str(source)
-    package = py_source_packages[source]
-    arc_path = package.split('.') + [ basename(filename) + 'c' ]
-    zip_path = [ 'zip' ] + arc_path
-    arcname = joinpath(*arc_path)
-    zipname = joinpath(*zip_path)
-    f = File(zipname)
-
-    env.Command(f, source, CompilePyFile)
-    py_compiled.append(f)
-    py_arcname[f] = arcname
+    env.Command(source.compiled, source.source, generate.compilePyFile)
+    py_compiled.append(source.compiled)
 
     # make the zipfile depend on the archive name so that the archive
     # is rebuilt if the name changes
-    py_zip_depends.append(Value(arcname))
-
-# Action function to build the zip archive.  Uses the PyZipFile module
-# included in the standard Python library.
-def buildPyZip(target, source, env):
-    zf = zipfile.ZipFile(str(target[0]), 'w')
-    for s in source:
-        arcname = py_arcname[s]
-        zipname = str(s)
-        zf.write(zipname, arcname)
-    zf.close()
+    py_zip_depends.append(Value(source.arcname))
 
 # Add the zip file target to the environment.
-env.Command('m5py.zip', py_compiled, buildPyZip)
-env.Depends('m5py.zip', py_zip_depends)
+m5zip = File('m5py.zip')
+env.Command(m5zip, py_compiled, generate.buildPyZip)
+env.Depends(m5zip, py_zip_depends)
 
 ########################################################################
 #
@@ -273,7 +353,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
     newEnv.Append(**kwargs)
     exe = 'm5.' + label  # final executable
     bin = exe + '.bin'   # executable w/o appended Python zip archive
-    newEnv.Program(bin, make_objs(sources, newEnv))
+    newEnv.Program(bin, make_objs(cc_sources, newEnv))
     if strip:
         stripped_bin = bin + '.stripped'
         if sys.platform == 'sunos5':
@@ -308,7 +388,7 @@ elif env['ICC']:
     ccflags['prof'] = '-fast -g -pg'
 else:
     print 'Unknown compiler, please fix compiler options'
-    Exit(1)    
+    Exit(1)
 
 makeEnv('debug', '.do',
         CCFLAGS = Split(ccflags['debug']),
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 559516725..fec245b75 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -35,8 +35,14 @@ class AlphaTLB(SimObject):
 
 class AlphaDTB(AlphaTLB):
     type = 'AlphaDTB'
+    cxx_namespace = 'AlphaISA'
+    cxx_class = 'DTB'
+
     size = 64
 
 class AlphaITB(AlphaTLB):
     type = 'AlphaITB'
+    cxx_namespace = 'AlphaISA'
+    cxx_class = 'ITB'
+
     size = 48
diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc
index 99be25057..f666de604 100644
--- a/src/arch/alpha/freebsd/system.cc
+++ b/src/arch/alpha/freebsd/system.cc
@@ -35,16 +35,15 @@
  *
  */
 
-#include "arch/alpha/system.hh"
 #include "arch/alpha/freebsd/system.hh"
+#include "arch/alpha/system.hh"
+#include "arch/isa_traits.hh"
+#include "arch/vtophys.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "arch/isa_traits.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
-#include "arch/vtophys.hh"
 
 #define TIMER_FREQUENCY 1193180
 
@@ -77,8 +76,9 @@ FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
     Addr ppc_vaddr = 0;
     Addr timer_vaddr = 0;
 
-    ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1);
-    timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2);
+    assert(NumArgumentRegs >= 3);
+    ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg[1]);
+    timer_vaddr = (Addr)tc->readIntReg(ArgumentReg[2]);
 
     virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
     virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
@@ -92,64 +92,8 @@ FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
     ((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
-
-CREATE_SIM_OBJECT(FreebsdAlphaSystem)
+FreebsdAlphaSystem *
+FreebsdAlphaSystemParams::create()
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new FreebsdAlphaSystem(p);
+    return new FreebsdAlphaSystem(this);
 }
-
-REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)
-
diff --git a/src/arch/alpha/freebsd/system.hh b/src/arch/alpha/freebsd/system.hh
index e0d874e8f..8e8493f97 100644
--- a/src/arch/alpha/freebsd/system.hh
+++ b/src/arch/alpha/freebsd/system.hh
@@ -28,10 +28,13 @@
  * Authors: Ben Nash
  */
 
-#ifndef __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
-#define __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
+#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
 
+#include "arch/alpha/system.hh"
 #include "kern/system_events.hh"
+#include "params/FreebsdAlphaSystem.hh"
+#include "sim/system.hh"
 
 class FreebsdAlphaSystem : public AlphaSystem
 {
@@ -49,10 +52,12 @@ class FreebsdAlphaSystem : public AlphaSystem
     SkipCalibrateClocksEvent *skipCalibrateClocks;
 
   public:
+    typedef FreebsdAlphaSystemParams Params;
     FreebsdAlphaSystem(Params *p);
     ~FreebsdAlphaSystem();
+
     void doCalibrateClocks(ThreadContext *tc);
 
 };
 
-#endif // __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
+#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index a267ac034..7dc7e5151 100644
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -156,14 +156,12 @@ namespace AlphaISA
     const int ReturnAddressReg = 26;
     const int ReturnValueReg = 0;
     const int FramePointerReg = 15;
-    const int ArgumentReg0 = 16;
-    const int ArgumentReg1 = 17;
-    const int ArgumentReg2 = 18;
-    const int ArgumentReg3 = 19;
-    const int ArgumentReg4 = 20;
-    const int ArgumentReg5 = 21;
+
+    const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
     const int SyscallNumReg = ReturnValueReg;
-    const int SyscallPseudoReturnReg = ArgumentReg4;
+    const int SyscallPseudoReturnReg = ArgumentReg[4];
     const int SyscallSuccessReg = 19;
 
     const int LogVMPageSize = 13;	// 8K bytes
diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc
index e8bdc1d66..f93cdfbad 100644
--- a/src/arch/alpha/linux/system.cc
+++ b/src/arch/alpha/linux/system.cc
@@ -54,7 +54,6 @@
 #include "kern/linux/events.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 
 using namespace std;
@@ -192,64 +191,8 @@ LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
             ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
-
-CREATE_SIM_OBJECT(LinuxAlphaSystem)
+LinuxAlphaSystem *
+LinuxAlphaSystemParams::create()
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new LinuxAlphaSystem(p);
+    return new LinuxAlphaSystem(this);
 }
-
-REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem)
-
diff --git a/src/arch/alpha/linux/system.hh b/src/arch/alpha/linux/system.hh
index 14396f8ab..00cde826a 100644
--- a/src/arch/alpha/linux/system.hh
+++ b/src/arch/alpha/linux/system.hh
@@ -41,6 +41,7 @@ class IdleStartEvent;
 #include "arch/alpha/idle_event.hh"
 #include "arch/alpha/system.hh"
 #include "kern/linux/events.hh"
+#include "params/LinuxAlphaSystem.hh"
 
 using namespace AlphaISA;
 using namespace Linux;
@@ -129,6 +130,7 @@ class LinuxAlphaSystem : public AlphaSystem
     IdleStartEvent *idleStartEvent;
 
   public:
+    typedef LinuxAlphaSystemParams Params;
     LinuxAlphaSystem(Params *p);
     ~LinuxAlphaSystem();
 
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index ed0938aeb..2af62ceea 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -39,8 +39,8 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "mem/physical.hh"
+#include "params/AlphaSystem.hh"
 #include "sim/byteswap.hh"
-#include "sim/builder.hh"
 
 
 using namespace LittleEndianGuest;
@@ -56,14 +56,14 @@ AlphaSystem::AlphaSystem(Params *p)
      * Load the pal, and console code into memory
      */
     // Load Console Code
-    console = createObjectFile(params()->console_path);
+    console = createObjectFile(params()->console);
     if (console == NULL)
-        fatal("Could not load console file %s", params()->console_path);
+        fatal("Could not load console file %s", params()->console);
 
     // Load pal file
-    pal = createObjectFile(params()->palcode);
+    pal = createObjectFile(params()->pal);
     if (pal == NULL)
-        fatal("Could not load PALcode file %s", params()->palcode);
+        fatal("Could not load PALcode file %s", params()->pal);
 
 
     // Load program sections into memory
@@ -212,65 +212,8 @@ AlphaSystem::unserialize(Checkpoint *cp, const std::string &section)
     palSymtab->unserialize("pal_symtab", cp, section);
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<std::string> kernel;
-    Param<std::string> console;
-    Param<std::string> pal;
-
-    Param<std::string> boot_osflags;
-    Param<std::string> readfile;
-    Param<std::string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
-
-CREATE_SIM_OBJECT(AlphaSystem)
+AlphaSystem *
+AlphaSystemParams::create()
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-    return new AlphaSystem(p);
+    return new AlphaSystem(this);
 }
-
-REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)
-
-
diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh
index f92b71c9a..a934550b7 100644
--- a/src/arch/alpha/system.hh
+++ b/src/arch/alpha/system.hh
@@ -35,25 +35,18 @@
 #include <string>
 #include <vector>
 
-#include "sim/system.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "kern/system_events.hh"
+#include "params/AlphaSystem.hh"
 #include "sim/sim_object.hh"
+#include "sim/system.hh"
 
 class AlphaSystem : public System
 {
   public:
-    struct Params : public System::Params
-    {
-        std::string console_path;
-        std::string palcode;
-        uint64_t system_type;
-        uint64_t system_rev;
-    };
-
+    typedef AlphaSystemParams Params;
     AlphaSystem(Params *p);
-
     ~AlphaSystem();
 
 /**
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 714bca22a..214b2579f 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -41,7 +41,8 @@
 #include "base/trace.hh"
 #include "config/alpha_tlaser.hh"
 #include "cpu/thread_context.hh"
-#include "sim/builder.hh"
+#include "params/AlphaDTB.hh"
+#include "params/AlphaITB.hh"
 
 using namespace std;
 using namespace EV5;
@@ -600,44 +601,14 @@ TLB::index(bool advance)
 
 /* end namespace AlphaISA */ }
 
-DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
+AlphaISA::ITB *
+AlphaITBParams::create()
 {
-    return new ITB(getInstanceName(), size);
+    return new AlphaISA::ITB(name, size);
 }
 
-REGISTER_SIM_OBJECT("AlphaITB", ITB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
+AlphaISA::DTB *
+AlphaDTBParams::create()
 {
-    return new DTB(getInstanceName(), size);
+    return new AlphaISA::DTB(name, size);
 }
-
-REGISTER_SIM_OBJECT("AlphaDTB", DTB)
diff --git a/src/arch/alpha/tru64/system.cc b/src/arch/alpha/tru64/system.cc
index 00918bda4..db3402d2a 100644
--- a/src/arch/alpha/tru64/system.cc
+++ b/src/arch/alpha/tru64/system.cc
@@ -40,7 +40,6 @@
 #include "kern/system_events.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 
@@ -91,63 +90,8 @@ Tru64AlphaSystem::~Tru64AlphaSystem()
 #endif
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-    Param<Tick> boot_cpu_frequency;
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<string> kernel;
-    Param<string> console;
-    Param<string> pal;
-
-    Param<string> boot_osflags;
-    Param<string> readfile;
-    Param<string> symbolfile;
-    Param<unsigned int> init_param;
-
-    Param<uint64_t> system_type;
-    Param<uint64_t> system_rev;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-    INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(console, "file that contains the console code"),
-    INIT_PARAM(pal, "file that contains palcode"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
-    INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
-    INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1)
-
-END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
-
-CREATE_SIM_OBJECT(Tru64AlphaSystem)
+Tru64AlphaSystem *
+Tru64AlphaSystemParams::create()
 {
-    AlphaSystem::Params *p = new AlphaSystem::Params;
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->console_path = console;
-    p->palcode = pal;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    p->symbolfile = symbolfile;
-    p->system_type = system_type;
-    p->system_rev = system_rev;
-
-    return new Tru64AlphaSystem(p);
+    return new Tru64AlphaSystem(this);
 }
-
-REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem)
diff --git a/src/arch/alpha/tru64/system.hh b/src/arch/alpha/tru64/system.hh
index 947e92f50..815a34213 100644
--- a/src/arch/alpha/tru64/system.hh
+++ b/src/arch/alpha/tru64/system.hh
@@ -34,6 +34,7 @@
 
 #include "arch/alpha/system.hh"
 #include "arch/isa_traits.hh"
+#include "params/Tru64AlphaSystem.hh"
 #include "sim/system.hh"
 
 class ThreadContext;
@@ -64,6 +65,7 @@ class Tru64AlphaSystem : public AlphaSystem
     DumpMbufEvent *dumpMbufEvent;
 
   public:
+    typedef Tru64AlphaSystemParams Params;
     Tru64AlphaSystem(Params *p);
     ~Tru64AlphaSystem();
 
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 5ab6957a3..5d4403553 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -74,10 +74,10 @@ namespace MipsISA
     const int ReturnValueReg = 2;
     const int ReturnValueReg1 = 2;
     const int ReturnValueReg2 = 3;
-    const int ArgumentReg0 = 4;
-    const int ArgumentReg1 = 5;
-    const int ArgumentReg2 = 6;
-    const int ArgumentReg3 = 7;
+
+    const int ArgumentReg[] = {4, 5, 6, 7};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
     const int KernelReg0 = 26;
     const int KernelReg1 = 27;
     const int GlobalPointerReg = 28;
@@ -87,7 +87,7 @@ namespace MipsISA
 
     const int SyscallNumReg = ReturnValueReg1;
     const int SyscallPseudoReturnReg = ReturnValueReg2;
-    const int SyscallSuccessReg = ArgumentReg3;
+    const int SyscallSuccessReg = ArgumentReg[3];
 
     const int LogVMPageSize = 13;	// 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 30e5ebb08..2d0257cd7 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -35,8 +35,14 @@ class SparcTLB(SimObject):
 
 class SparcDTB(SparcTLB):
     type = 'SparcDTB'
+    cxx_namespace = 'SparcISA'
+    cxx_class = 'DTB'
+
     size = 64
 
 class SparcITB(SparcTLB):
     type = 'SparcITB'
+    cxx_namespace = 'SparcISA'
+    cxx_class = 'ITB'
+
     size = 64
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 8b3ec36a6..0edbdec4b 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -69,14 +69,12 @@ namespace SparcISA
     const int ReturnAddressReg = 31; // post call, precall is 15
     const int ReturnValueReg = 8; // Post return, 24 is pre-return.
     const int FramePointerReg = 30;
-    const int ArgumentReg0 = 8;
-    const int ArgumentReg1 = 9;
-    const int ArgumentReg2 = 10;
-    const int ArgumentReg3 = 11;
-    const int ArgumentReg4 = 12;
-    const int ArgumentReg5 = 13;
+
+    const int ArgumentReg[] = {8, 9, 10, 11, 12, 13};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
     // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = ArgumentReg1;
+    const int SyscallPseudoReturnReg = ArgumentReg[1];
 
     //XXX These numbers are bogus
     const int MaxInstSrcRegs = 8;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 0776694ec..bc950301a 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -399,8 +399,9 @@ Sparc64LiveProcess::argsInit(int intSize, int pageSize)
     initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler64, spillSize);
 
     //Set up the thread context to start running the process
-    threadContexts[0]->setIntReg(ArgumentReg0, argc);
-    threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    assert(NumArgumentRegs >= 2);
+    threadContexts[0]->setIntReg(ArgumentReg[0], argc);
+    threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
     threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
 
     Addr prog_entry = objFile->entryPoint();
@@ -627,8 +628,9 @@ Sparc32LiveProcess::argsInit(int intSize, int pageSize)
     initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler32, spillSize);
 
     //Set up the thread context to start running the process
-    //threadContexts[0]->setIntReg(ArgumentReg0, argc);
-    //threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    //assert(NumArgumentRegs >= 2);
+    //threadContexts[0]->setIntReg(ArgumentReg[0], argc);
+    //threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
     threadContexts[0]->setIntReg(StackPointerReg, stack_min);
 
     uint32_t prog_entry = objFile->entryPoint();
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 2600213fd..1ee207844 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -35,8 +35,8 @@
 #include "base/loader/symtab.hh"
 #include "base/trace.hh"
 #include "mem/physical.hh"
+#include "params/SparcSystem.hh"
 #include "sim/byteswap.hh"
-#include "sim/builder.hh"
 
 
 using namespace BigEndianGuest;
@@ -216,104 +216,8 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string &section)
     partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
-
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimObjectParam<PhysicalMemory *> rom;
-    SimObjectParam<PhysicalMemory *> nvram;
-    SimObjectParam<PhysicalMemory *> hypervisor_desc;
-    SimObjectParam<PhysicalMemory *> partition_desc;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-    Param<Addr> reset_addr;
-    Param<Addr> hypervisor_addr;
-    Param<Addr> openboot_addr;
-    Param<Addr> nvram_addr;
-    Param<Addr> hypervisor_desc_addr;
-    Param<Addr> partition_desc_addr;
-
-    Param<std::string> kernel;
-    Param<std::string> reset_bin;
-    Param<std::string> hypervisor_bin;
-    Param<std::string> openboot_bin;
-    Param<std::string> nvram_bin;
-    Param<std::string> hypervisor_desc_bin;
-    Param<std::string> partition_desc_bin;
-
-    Param<Tick> boot_cpu_frequency;
-    Param<std::string> boot_osflags;
-    Param<std::string> readfile;
-    Param<unsigned int> init_param;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
-    INIT_PARAM(physmem, "phsyical memory"),
-    INIT_PARAM(rom, "ROM for boot code"),
-    INIT_PARAM(nvram, "Non-volatile RAM for the nvram"),
-    INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"),
-    INIT_PARAM(partition_desc, "ROM for the partition description"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings),
-
-    INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
-    INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
-    INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
-    INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"),
-    INIT_PARAM(hypervisor_desc_addr,
-            "Address that hypervisor description should be loaded at"),
-    INIT_PARAM(partition_desc_addr,
-            "Address that partition description should be loaded at"),
-
-    INIT_PARAM(kernel, "file that contains the kernel code"),
-    INIT_PARAM(reset_bin, "file that contains the reset code"),
-    INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
-    INIT_PARAM(openboot_bin, "file that contains the openboot code"),
-    INIT_PARAM(nvram_bin, "file that contains the nvram image"),
-    INIT_PARAM(hypervisor_desc_bin,
-            "file that contains the hypervisor description image"),
-    INIT_PARAM(partition_desc_bin,
-            "file that contains the partition description image"),
-    INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
-    INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
-                    "a"),
-    INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
-    INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
-
-CREATE_SIM_OBJECT(SparcSystem)
+SparcSystem *
+SparcSystemParams::create()
 {
-    SparcSystem::Params *p = new SparcSystem::Params;
-    p->name = getInstanceName();
-    p->boot_cpu_frequency = boot_cpu_frequency;
-    p->physmem = physmem;
-    p->rom = rom;
-    p->nvram = nvram;
-    p->hypervisor_desc = hypervisor_desc;
-    p->partition_desc = partition_desc;
-    p->mem_mode = mem_mode;
-    p->kernel_path = kernel;
-    p->reset_addr = reset_addr;
-    p->hypervisor_addr = hypervisor_addr;
-    p->openboot_addr = openboot_addr;
-    p->nvram_addr = nvram_addr;
-    p->hypervisor_desc_addr = hypervisor_desc_addr;
-    p->partition_desc_addr = partition_desc_addr;
-    p->reset_bin = reset_bin;
-    p->hypervisor_bin = hypervisor_bin;
-    p->openboot_bin = openboot_bin;
-    p->nvram_bin = nvram_bin;
-    p->hypervisor_desc_bin = hypervisor_desc_bin;
-    p->partition_desc_bin = partition_desc_bin;
-    p->boot_osflags = boot_osflags;
-    p->init_param = init_param;
-    p->readfile = readfile;
-    return new SparcSystem(p);
+    return new SparcSystem(this);
 }
-
-REGISTER_SIM_OBJECT("SparcSystem", SparcSystem)
-
-
diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh
index ac4d34279..086ce3fdb 100644
--- a/src/arch/sparc/system.hh
+++ b/src/arch/sparc/system.hh
@@ -37,35 +37,15 @@
 #include "base/loader/symtab.hh"
 #include "cpu/pc_event.hh"
 #include "kern/system_events.hh"
+#include "params/SparcSystem.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
 class SparcSystem : public System
 {
   public:
-    struct Params : public System::Params
-    {
-        PhysicalMemory *rom;
-        PhysicalMemory *nvram;
-        PhysicalMemory *hypervisor_desc;
-        PhysicalMemory *partition_desc;
-        Addr reset_addr;
-        Addr hypervisor_addr;
-        Addr openboot_addr;
-        Addr nvram_addr;
-        Addr hypervisor_desc_addr;
-        Addr partition_desc_addr;
-        std::string reset_bin;
-        std::string hypervisor_bin;
-        std::string openboot_bin;
-        std::string nvram_bin;
-        std::string hypervisor_desc_bin;
-        std::string partition_desc_bin;
-        std::string boot_osflags;
-    };
-
+    typedef SparcSystemParams Params;
     SparcSystem(Params *p);
-
     ~SparcSystem();
 
 /**
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 68df19618..21d56b8c6 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -39,7 +39,8 @@
 #include "cpu/base.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/SparcDTB.hh"
+#include "params/SparcITB.hh"
 #include "sim/system.hh"
 
 /* @todo remove some of the magic constants.  -- ali
@@ -1386,46 +1387,14 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
 
 /* end namespace SparcISA */ }
 
-using namespace SparcISA;
-
-DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 48)
-
-END_INIT_SIM_OBJECT_PARAMS(ITB)
-
-
-CREATE_SIM_OBJECT(ITB)
+SparcISA::ITB *
+SparcITBParams::create()
 {
-    return new ITB(getInstanceName(), size);
+    return new SparcISA::ITB(name, size);
 }
 
-REGISTER_SIM_OBJECT("SparcITB", ITB)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-    Param<int> size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DTB)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
-
-    INIT_PARAM_DFLT(size, "TLB size", 64)
-
-END_INIT_SIM_OBJECT_PARAMS(DTB)
-
-
-CREATE_SIM_OBJECT(DTB)
+SparcISA::DTB *
+SparcDTBParams::create()
 {
-    return new DTB(getInstanceName(), size);
+    return new SparcISA::DTB(name, size);
 }
-
-REGISTER_SIM_OBJECT("SparcDTB", DTB)
diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index f90d6670e..ae03d176e 100644
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -96,6 +96,62 @@ namespace X86ISA
 
         std::string generateDisassembly(Addr pc,
             const SymbolTable *symtab) const;
+
+        template<class Context, class MemType>
+        Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const
+        {
+            Fault fault = NoFault;
+            int size = dataSize;
+            Addr alignedEA = EA & ~(dataSize - 1);
+            if (EA != alignedEA)
+                size *= 2;
+            switch(size)
+            {
+              case 1:
+                fault = xc->read(alignedEA, (uint8_t&)Mem, flags);
+                break;
+              case 2:
+                fault = xc->read(alignedEA, (uint16_t&)Mem, flags);
+                break;
+              case 4:
+                fault = xc->read(alignedEA, (uint32_t&)Mem, flags);
+                break;
+              case 8:
+                fault = xc->read(alignedEA, (uint64_t&)Mem, flags);
+                break;
+              default:
+                panic("Bad operand size %d!\n", size);
+            }
+            return fault;
+        }
+
+        template<class Context, class MemType>
+        Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const
+        {
+            Fault fault = NoFault;
+            int size = dataSize;
+            Addr alignedEA = EA & ~(dataSize - 1);
+            if (EA != alignedEA)
+                size *= 2;
+            switch(size)
+            {
+              case 1:
+                fault = xc->write((uint8_t&)Mem, alignedEA, flags, 0);
+                break;
+              case 2:
+                fault = xc->write((uint16_t&)Mem, alignedEA, flags, 0);
+                break;
+              case 4:
+                fault = xc->write((uint32_t&)Mem, alignedEA, flags, 0);
+                break;
+              case 8:
+                fault = xc->write((uint64_t&)Mem, alignedEA, flags, 0);
+                break;
+              default:
+                panic("Bad operand size %d!\n", size);
+            }
+            return fault;
+        }
     };
 }
 
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index b28f2029c..3b51f9d73 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -72,7 +72,7 @@
             default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x01: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -85,7 +85,7 @@
             default: MultiInst::OR(OPCODE_OP_BOTTOM3,
                                    [Eb,Gb], [Ev,Gv],
                                    [Gb,Eb], [Gv,Ev],
-                                   [rAl,Ib], [rAx,Iz]);
+                                   [rAb,Ib], [rAv,Iz]);
         }
         0x02: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -99,7 +99,7 @@
             default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x03: decode OPCODE_OP_BOTTOM3 {
             0x6: decode MODE_SUBMODE {
@@ -113,7 +113,7 @@
             default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x04: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -125,7 +125,7 @@
             default: MultiInst::AND(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x05: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -134,7 +134,7 @@
             default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x06: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -146,7 +146,7 @@
             default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         0x07: decode OPCODE_OP_BOTTOM3 {
             0x6: M5InternalError::error(
@@ -158,37 +158,40 @@
             default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
                                     [Eb,Gb], [Ev,Gv],
                                     [Gb,Eb], [Gv,Ev],
-                                    [rAl,Ib], [rAx,Iz]);
-        }
-        0x08: decode MODE_SUBMODE {
-            0x0: M5InternalError::error (
-                {{"Tried to execute an REX prefix!"}});
-            default: Inst::INC(B);
-        }
-        0x09: decode MODE_SUBMODE {
-            0x0: M5InternalError::error (
-                {{"Tried to execute an REX prefix!"}});
-            default: Inst::DEC(B);
+                                    [rAb,Ib], [rAv,Iz]);
         }
         format Inst {
-            0x0A: PUSH(B);
-            0x0B: POP(B);
+            0x08: decode MODE_SUBMODE {
+                0x0: M5InternalError::error (
+                    {{"Tried to execute an REX prefix!"}});
+                default: INC(Bv);
+            }
+            0x09: decode MODE_SUBMODE {
+                0x0: M5InternalError::error (
+                    {{"Tried to execute an REX prefix!"}});
+                default: DEC(Bv);
+            }
+            0x0A: PUSH(Bv);
+            0x0B: POP(Bv);
         }
         0x0C: decode OPCODE_OP_BOTTOM3 {
             0x0: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
-                default: pusha();
+                default: Inst::PUSHA();
             }
             0x1: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
-                default: popa();
+                default: Inst::POPA();
             }
             0x2: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: bound_Gv_Ma();
             }
             0x3: decode MODE_SUBMODE {
-                0x0: Inst::MOVSXD(Gv,Ed);
+                //The second operand should really be of size "d", but it's
+                //set to "v" in order to have a consistent register size.
+                //This shouldn't affect behavior.
+                0x0: Inst::MOVSXD(Gv,Ev);
                 default: arpl_Ew_Gw();
             }
             0x4: M5InternalError::error(
@@ -201,10 +204,10 @@
                 {{"Tried to execute the DS address size override prefix!"}});
         }
         0x0D: decode OPCODE_OP_BOTTOM3 {
-            0x0: push_Iz();
-            0x1: imul_Gv_Ev_Iz();
-            0x2: push_Ib();
-            0x3: imul_Gv_Ev_Ib();
+            0x0: Inst::PUSH(Iz);
+            0x1: Inst::IMUL(Gv,Ev,Iz);
+            0x2: Inst::PUSH(Ib);
+            0x3: Inst::IMUL(Gv,Ev,Ib);
             0x4: ins_Yb_Dx();
             0x5: ins_Yz_Dx();
             0x6: outs_Dx_Xb();
@@ -302,8 +305,8 @@
             default: xchg_B_rAX();
         }
         0x13: decode OPCODE_OP_BOTTOM3 {
-            0x0: cbw_or_cwde_or_cdqe_rAX();
-            0x1: cwd_or_cdq_or_cqo_rAX_rDX();
+            0x0: Inst::CDQE(rAv);
+            0x1: Inst::CQO(rAv,rDv);
             0x2: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: call_far_Ap();
@@ -333,8 +336,8 @@
             0x7: cmps_Yv_Xv();
         }
         0x15: decode OPCODE_OP_BOTTOM3 {
-            0x0: Inst::TEST(rAl,Ib);
-            0x1: Inst::TEST(rAX,Iz);
+            0x0: Inst::TEST(rAb,Ib);
+            0x1: Inst::TEST(rAv,Iz);
             0x2: stos_Yb_Al();
             0x3: stos_Yv_rAX();
             0x4: lods_Al_Xb();
@@ -343,8 +346,8 @@
             0x7: scas_Yv_rAX();
         }
         format Inst {
-            0x16: MOV(B,Ib);
-            0x17: MOV(B,Iv);
+            0x16: MOV(Bb,Ib);
+            0x17: MOV(Bv,Iv);
             0x18: decode OPCODE_OP_BOTTOM3 {
                 //0x0: group2_Eb_Ib();
                 0x0: decode MODRM_REG {
@@ -404,10 +407,55 @@
             0x7: iret();
         }
         0x1A: decode OPCODE_OP_BOTTOM3 {
-            0x0: group2_Eb_1();
-            0x1: group2_Ev_1();
-            0x2: group2_Eb_Cl();
-            0x3: group2_Ev_Cl();
+            format Inst {
+                //0x0: group2_Eb_1();
+                0x0: decode MODRM_REG {
+                    0x0: ROL_1(Eb);
+                    0x1: ROR_1(Eb);
+                    0x2: RCL_1(Eb);
+                    0x3: RCR_1(Eb);
+                    0x4: SAL_1(Eb);
+                    0x5: SHR_1(Eb);
+                    0x6: SAL_1(Eb);
+                    0x7: SAR_1(Eb);
+                }
+                //0x1: group2_Ev_1();
+                0x1: decode MODRM_REG {
+                    0x0: ROL_1(Ev);
+                    0x1: ROR_1(Ev);
+                    0x2: RCL_1(Ev);
+                    0x3: RCR_1(Ev);
+                    0x4: SAL_1(Ev);
+                    0x5: SHR_1(Ev);
+                    0x6: SAL_1(Ev);
+                    0x7: SAR_1(Ev);
+                }
+                //0x2: group2_Eb_Cl();
+                0x2: decode MODRM_REG {
+                    0x0: ROL(Eb,rCb);
+                    0x1: ROR(Eb,rCb);
+                    0x2: RCL(Eb,rCb);
+                    0x3: RCR(Eb,rCb);
+                    0x4: SAL(Eb,rCb);
+                    0x5: SHR(Eb,rCb);
+                    0x6: SAL(Eb,rCb);
+                    0x7: SAR(Eb,rCb);
+                }
+                //The second operand should have size "b", but to have
+                //consistent register sizes it's "v". This shouldn't have
+                //any affect on functionality.
+                //0x3: group2_Ev_Cl();
+                0x3: decode MODRM_REG {
+                    0x0: ROL(Ev,rCv);
+                    0x1: ROR(Ev,rCv);
+                    0x2: RCL(Ev,rCv);
+                    0x3: RCR(Ev,rCv);
+                    0x4: SAL(Ev,rCv);
+                    0x5: SHR(Ev,rCv);
+                    0x6: SAL(Ev,rCv);
+                    0x7: SAR(Ev,rCv);
+                }
+            }
             0x4: decode MODE_SUBMODE {
                 0x0: Inst::UD2();
                 default: aam_Ib();
@@ -465,8 +513,28 @@
                 {{"Tried to execute the rep/repe prefix!"}});
             0x4: hlt();
             0x5: cmc();
-            0x6: group3_Eb();
-            0x7: group3_Ev();
+            //0x6: group3_Eb();
+            0x6: decode MODRM_REG {
+                0x0: Inst::TEST(Eb,Iz);
+                0x1: Inst::TEST(Eb,Iz);
+                0x2: Inst::NOT(Eb);
+                0x3: Inst::NEG(Eb);
+                0x4: mul_Eb();
+                0x5: imul_Eb();
+                0x6: div_Eb();
+                0x7: idiv_Eb();
+            }
+            //0x7: group3_Ev();
+            0x7: decode MODRM_REG {
+                0x0: Inst::TEST(Ev,Iz);
+                0x1: Inst::TEST(Ev,Iz);
+                0x2: Inst::NOT(Ev);
+                0x3: Inst::NEG(Ev);
+                0x4: mul_Ev();
+                0x5: imul_Ev();
+                0x6: div_Ev();
+                0x7: idiv_Ev();
+            }
         }
         0x1F: decode OPCODE_OP_BOTTOM3 {
             0x0: clc();
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index e5631d37b..da4c82afa 100644
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -81,21 +81,58 @@
                 0x0: invd();
                 0x1: wbinvd();
                 0x2: Inst::UD2();
-                0x3: UD2();
+                0x3: Inst::UD2();
                 0x4: Inst::UD2();
                 0x5: threednow();
                 0x6: threednow();
                 0x7: threednow();
             }
-            0x02: decode OPCODE_OP_BOTTOM3 {
-                0x0: holder();
-                0x1: holder();
-                0x2: holder();
-                0x3: holder();
-                0x4: holder();
-                0x5: holder();
-                0x6: holder();
-                0x7: holder();
+            0x02: decode LEGACY_DECODEVAL {
+                // no prefix
+                0x0: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // repe (0xF3)
+                0x4: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // operand size (0x66)
+                0x1: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                // repne (0xF2)
+                0x8: decode OPCODE_OP_BOTTOM3 {
+                    0x0: holder();
+                    0x1: holder();
+                    0x2: holder();
+                    0x3: holder();
+                    0x4: holder();
+                    0x5: holder();
+                    0x6: holder();
+                    0x7: holder();
+                }
+                default: Inst::UD2();
             }
             0x03: decode OPCODE_OP_BOTTOM3 {
                 0x0: group17();
@@ -147,25 +184,27 @@
                 0x6: three_byte_opcode();
                 0x7: three_byte_opcode();
             }
-            0x08: decode OPCODE_OP_BOTTOM3 {
-                0x0: cmovo_Gv_Ev();
-                0x1: cmovno_Gv_Ev();
-                0x2: cmovb_Gv_Ev();
-                0x3: cmovnb_Gv_Ev();
-                0x4: cmovz_Gv_Ev();
-                0x5: cmovnz_Gv_Ev();
-                0x6: cmovbe_Gv_Ev();
-                0x7: cmovnbe_Gv_Ev();
-            }
-            0x09: decode OPCODE_OP_BOTTOM3 {
-                0x0: cmovs_Gv_Ev();
-                0x1: cmovns_Gv_Ev();
-                0x2: cmovp_Gv_Ev();
-                0x3: cmovnp_Gv_Ev();
-                0x4: cmovl_Gv_Ev();
-                0x5: cmovnl_Gv_Ev();
-                0x6: cmovle_Gv_Ev();
-                0x7: cmovnle_Gv_Ev();
+            format Inst {
+                0x08: decode OPCODE_OP_BOTTOM3 {
+                    0x0: CMOVO(Gv,Ev);
+                    0x1: CMOVNO(Gv,Ev);
+                    0x2: CMOVB(Gv,Ev);
+                    0x3: CMOVNB(Gv,Ev);
+                    0x4: CMOVZ(Gv,Ev);
+                    0x5: CMOVNZ(Gv,Ev);
+                    0x6: CMOVBE(Gv,Ev);
+                    0x7: CMOVNBE(Gv,Ev);
+                }
+                0x09: decode OPCODE_OP_BOTTOM3 {
+                    0x0: CMOVS(Gv,Ev);
+                    0x1: CMOVNS(Gv,Ev);
+                    0x2: CMOVP(Gv,Ev);
+                    0x3: CMOVNP(Gv,Ev);
+                    0x4: CMOVL(Gv,Ev);
+                    0x5: CMOVNL(Gv,Ev);
+                    0x6: CMOVLE(Gv,Ev);
+                    0x7: CMOVNLE(Gv,Ev);
+                }
             }
             0x0A: decode OPCODE_OP_BOTTOM3 {
                 0x0: holder();
@@ -248,26 +287,26 @@
                     0x6: JLE(Jz);
                     0x7: JNLE(Jz);
                 }
-            }
-            0x12: decode OPCODE_OP_BOTTOM3 {
-                0x0: seto_Eb();
-                0x1: setno_Eb();
-                0x2: setb_Eb();
-                0x3: setnb_Eb();
-                0x4: setz_Eb();
-                0x5: setnz_Eb();
-                0x6: setbe_Eb();
-                0x7: setnbe_Eb();
-            }
-            0x13: decode OPCODE_OP_BOTTOM3 {
-                0x0: sets_Eb();
-                0x1: setns_Eb();
-                0x2: setp_Eb();
-                0x3: setnp_Eb();
-                0x4: setl_Eb();
-                0x5: setnl_Eb();
-                0x6: setle_Eb();
-                0x7: setnle_Eb();
+                0x12: decode OPCODE_OP_BOTTOM3 {
+                    0x0: SETO(Eb);
+                    0x1: SETNO(Eb);
+                    0x2: SETB(Eb);
+                    0x3: SETNB(Eb);
+                    0x4: SETZ(Eb);
+                    0x5: SETNZ(Eb);
+                    0x6: SETBE(Eb);
+                    0x7: SETNBE(Eb);
+                }
+                0x13: decode OPCODE_OP_BOTTOM3 {
+                    0x0: SETS(Eb);
+                    0x1: SETNS(Eb);
+                    0x2: SETP(Eb);
+                    0x3: SETNP(Eb);
+                    0x4: SETL(Eb);
+                    0x5: SETNL(Eb);
+                    0x6: SETLE(Eb);
+                    0x7: SETNLE(Eb);
+                }
             }
             0x14: decode OPCODE_OP_BOTTOM3 {
                 0x0: push_fs();
@@ -296,8 +335,11 @@
                 0x3: btr_Ev_Gv();
                 0x4: lfs_Gz_Mp();
                 0x5: lgs_Gz_Mp();
-                0x6: Inst::MOVZX_B(Gv,Eb);
-                0x7: Inst::MOVZX_W(Gv,Ew);
+                //The size of the second operand in these instructions should
+                //really be "b" or "w", but it's set to v in order to have a
+                //consistent register size. This shouldn't affect behavior.
+                0x6: Inst::MOVZX_B(Gv,Ev);
+                0x7: Inst::MOVZX_W(Gv,Ev);
             }
             0x17: decode OPCODE_OP_BOTTOM3 {
                 0x0: jmpe_Jz(); // IA-64?
@@ -306,8 +348,11 @@
                 0x3: btc_Ev_Gv();
                 0x4: bsf_Gv_Ev();
                 0x5: bsr_Gv_Ev();
-                0x6: Inst::MOVSX_B(Gv,Eb);
-                0x7: Inst::MOVSX_W(Gv,Ew);
+                //The size of the second operand in these instructions should
+                //really be "b" or "w", but it's set to v in order to have a
+                //consistent register size. This shouldn't affect behavior.
+                0x6: Inst::MOVSX_B(Gv,Ev);
+                0x7: Inst::MOVSX_W(Gv,Ev);
             }
             0x18: decode OPCODE_OP_BOTTOM3 {
                 0x0: holder();
diff --git a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
index 05aa6cd69..7e5578a3c 100644
--- a/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
+++ b/src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
@@ -77,9 +77,9 @@ def macroop ADD_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_M_R
@@ -92,9 +92,9 @@ def macroop ADD_M_R
 def macroop ADD_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADD_R_M
@@ -106,7 +106,7 @@ def macroop ADD_R_M
 def macroop ADD_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     add reg, reg, t1
 };
 
@@ -130,7 +130,7 @@ def macroop SUB_R_M
 def macroop SUB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub reg, reg, t1
 };
 
@@ -146,9 +146,9 @@ def macroop SUB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SUB_M_R
@@ -161,9 +161,9 @@ def macroop SUB_M_R
 def macroop SUB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sub t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_R
@@ -189,9 +189,9 @@ def macroop ADC_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_M_R
@@ -204,9 +204,9 @@ def macroop ADC_M_R
 def macroop ADC_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc t1, t1, reg
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ADC_R_M
@@ -218,7 +218,7 @@ def macroop ADC_R_M
 def macroop ADC_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     adc reg, reg, t1
 };
 
@@ -242,7 +242,7 @@ def macroop SBB_R_M
 def macroop SBB_R_P
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb reg, reg, t1
 };
 
@@ -258,9 +258,9 @@ def macroop SBB_P_I
 {
     rdip t7
     limm t2, imm
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, t2
-    st t1, ds, [scale, index, base], disp
+    st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SBB_M_R
@@ -273,20 +273,28 @@ def macroop SBB_M_R
 def macroop SBB_P_R
 {
     rdip t7
-    ld t1, ds, [scale, index, base], disp
+    ld t1, ds, [0, t0, t7], disp
     sbb t1, t1, reg
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop NEG_R
+{
+    sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
+};
+
+def macroop NEG_M
+{
+    ld t1, ds, [scale, index, base], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NEG_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
+    st t1, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#    class ADC(Inst):
-#	"Adc ^0 ^0 ^1"
-#    class ADD(Inst):
-#	"Add ^0 ^0 ^1"
-#    class SBB(Inst):
-#	"Sbb ^0 ^0 ^1"
-#    class SUB(Inst):
-#	"Sub ^0 ^0 ^1"
-#    class NEG(Inst):
-#	"Sub ^0 $0 ^0"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
index eed39c10c..f53fa8f05 100644
--- a/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
+++ b/src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
@@ -94,9 +94,3 @@ def macroop DEC_P
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class DEC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class INC(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
index 8697bef65..339e18cf8 100644
--- a/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
+++ b/src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
@@ -77,6 +77,27 @@ def macroop IMUL_R_P
     ld t1, ds, [scale, index, base], disp
     mul1s reg, reg, t1
 };
+
+def macroop IMUL_R_R_I
+{
+    limm t1, imm
+    mul1s reg, regm, t1
+};
+
+def macroop IMUL_R_M_I
+{
+    limm t1, imm
+    ld t2, ds, [scale, index, base], disp
+    mul1s reg, t2, t1
+};
+
+def macroop IMUL_R_P_I
+{
+    rdip t7
+    limm t1, imm
+    ld t2, ds, [0, t0, t7]
+    mul1s reg, t2, t1
+};
 '''
 #let {{
 #    class MUL(Inst):
diff --git a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
index 3d9250c2d..2008bf666 100644
--- a/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
+++ b/src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
@@ -53,8 +53,340 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class SETcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SETZ_R
+{
+    movi reg, reg, 1, flags=(CZF,)
+    movi reg, reg, 0, flags=(nCZF,)
+};
+
+def macroop SETZ_M
+{
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CZF,)
+    movi t1, t1, 0, flags=(nCZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNZ_R
+{
+    movi reg, reg, 1, flags=(nCZF,)
+    movi reg, reg, 0, flags=(CZF,)
+};
+
+def macroop SETNZ_M
+{
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNZ_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCZF,)
+    movi t1, t1, 0, flags=(CZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETB_R
+{
+    movi reg, reg, 1, flags=(CCF,)
+    movi reg, reg, 0, flags=(nCCF,)
+};
+
+def macroop SETB_M
+{
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCF,)
+    movi t1, t1, 0, flags=(nCCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNB_R
+{
+    movi reg, reg, 1, flags=(nCCF,)
+    movi reg, reg, 0, flags=(CCF,)
+};
+
+def macroop SETNB_M
+{
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNB_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCF,)
+    movi t1, t1, 0, flags=(CCF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETBE_R
+{
+    movi reg, reg, 1, flags=(CCvZF,)
+    movi reg, reg, 0, flags=(nCCvZF,)
+};
+
+def macroop SETBE_M
+{
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CCvZF,)
+    movi t1, t1, 0, flags=(nCCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNBE_R
+{
+    movi reg, reg, 1, flags=(nCCvZF,)
+    movi reg, reg, 0, flags=(CCvZF,)
+};
+
+def macroop SETNBE_M
+{
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNBE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCCvZF,)
+    movi t1, t1, 0, flags=(CCvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETS_R
+{
+    movi reg, reg, 1, flags=(CSF,)
+    movi reg, reg, 0, flags=(nCSF,)
+};
+
+def macroop SETS_M
+{
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSF,)
+    movi t1, t1, 0, flags=(nCSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNS_R
+{
+    movi reg, reg, 1, flags=(nCSF,)
+    movi reg, reg, 0, flags=(CSF,)
+};
+
+def macroop SETNS_M
+{
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNS_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSF,)
+    movi t1, t1, 0, flags=(CSF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETP_R
+{
+    movi reg, reg, 1, flags=(CPF,)
+    movi reg, reg, 0, flags=(nCPF,)
+};
+
+def macroop SETP_M
+{
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CPF,)
+    movi t1, t1, 0, flags=(nCPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNP_R
+{
+    movi reg, reg, 1, flags=(nCPF,)
+    movi reg, reg, 0, flags=(CPF,)
+};
+
+def macroop SETNP_M
+{
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNP_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCPF,)
+    movi t1, t1, 0, flags=(CPF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETL_R
+{
+    movi reg, reg, 1, flags=(CSxOF,)
+    movi reg, reg, 0, flags=(nCSxOF,)
+};
+
+def macroop SETL_M
+{
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOF,)
+    movi t1, t1, 0, flags=(nCSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNL_R
+{
+    movi reg, reg, 1, flags=(nCSxOF,)
+    movi reg, reg, 0, flags=(CSxOF,)
+};
+
+def macroop SETNL_M
+{
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNL_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOF,)
+    movi t1, t1, 0, flags=(CSxOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETLE_R
+{
+    movi reg, reg, 1, flags=(CSxOvZF,)
+    movi reg, reg, 0, flags=(nCSxOvZF,)
+};
+
+def macroop SETLE_M
+{
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(CSxOvZF,)
+    movi t1, t1, 0, flags=(nCSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNLE_R
+{
+    movi reg, reg, 1, flags=(nCSxOvZF,)
+    movi reg, reg, 0, flags=(CSxOvZF,)
+};
+
+def macroop SETNLE_M
+{
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNLE_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCSxOvZF,)
+    movi t1, t1, 0, flags=(CSxOvZF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETO_R
+{
+    movi reg, reg, 1, flags=(COF,)
+    movi reg, reg, 0, flags=(nCOF,)
+};
+
+def macroop SETO_M
+{
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(COF,)
+    movi t1, t1, 0, flags=(nCOF,)
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SETNO_R
+{
+    movi reg, reg, 1, flags=(nCOF,)
+    movi reg, reg, 0, flags=(COF,)
+};
+
+def macroop SETNO_M
+{
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SETNO_P
+{
+    rdip t7
+    movi t1, t1, 1, flags=(nCOF,)
+    movi t1, t1, 0, flags=(COF,)
+    st t1, ds, [0, t0, t7], disp
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_conversion/sign_extension.py b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
index e96eee694..6a2612c3c 100644
--- a/src/arch/x86/isa/insts/data_conversion/sign_extension.py
+++ b/src/arch/x86/isa/insts/data_conversion/sign_extension.py
@@ -53,7 +53,18 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
+microcode = '''
+def macroop CDQE_R {
+    sext reg, reg, "env.dataSize << 2"
+};
+
+def macroop CQO_R_R {
+    # A shift might be slower than, for example, an explicit sign extension,
+    # so it might be worthwhile to try to find an alternative.
+    mov regm, regm, reg
+    sra regm, regm, "env.dataSize * 8 - 1"
+};
+'''
 #let {{
 #    class CBW(Inst):
 #	"GenFault ${new UnimpInstFault}"
diff --git a/src/arch/x86/isa/insts/data_transfer/conditional_move.py b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
index 513e90c4e..17f8841f2 100644
--- a/src/arch/x86/isa/insts/data_transfer/conditional_move.py
+++ b/src/arch/x86/isa/insts/data_transfer/conditional_move.py
@@ -53,8 +53,292 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class CMOVcc(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop CMOVZ_R_R
+{
+    mov reg, reg, regm, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CZF,)
+};
+
+def macroop CMOVNZ_R_R
+{
+    mov reg, reg, regm, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVNZ_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCZF,)
+};
+
+def macroop CMOVB_R_R
+{
+    mov reg, reg, regm, flags=(CCF,)
+};
+
+def macroop CMOVB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCF,)
+};
+
+def macroop CMOVNB_R_R
+{
+    mov reg, reg, regm, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVNB_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCF,)
+};
+
+def macroop CMOVBE_R_R
+{
+    mov reg, reg, regm, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CCvZF,)
+};
+
+def macroop CMOVNBE_R_R
+{
+    mov reg, reg, regm, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVNBE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCCvZF,)
+};
+
+def macroop CMOVS_R_R
+{
+    mov reg, reg, regm, flags=(CSF,)
+};
+
+def macroop CMOVS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSF,)
+};
+
+def macroop CMOVNS_R_R
+{
+    mov reg, reg, regm, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVNS_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSF,)
+};
+
+def macroop CMOVP_R_R
+{
+    mov reg, reg, regm, flags=(CPF,)
+};
+
+def macroop CMOVP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CPF,)
+};
+
+def macroop CMOVNP_R_R
+{
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVNP_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, regm, flags=(nCPF,)
+};
+
+def macroop CMOVL_R_R
+{
+    mov reg, reg, regm, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOF,)
+};
+
+def macroop CMOVNL_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVNL_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOF,)
+};
+
+def macroop CMOVLE_R_R
+{
+    mov reg, reg, regm, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(CSxOvZF,)
+};
+
+def macroop CMOVNLE_R_R
+{
+    mov reg, reg, regm, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVNLE_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCSxOvZF,)
+};
+
+def macroop CMOVO_R_R
+{
+    mov reg, reg, regm, flags=(COF,)
+};
+
+def macroop CMOVO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(COF,)
+};
+
+def macroop CMOVNO_R_R
+{
+    mov reg, reg, regm, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_M
+{
+    ld t1, ds, [scale, index, base], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+
+def macroop CMOVNO_R_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    mov reg, reg, t1, flags=(nCOF,)
+};
+'''
diff --git a/src/arch/x86/isa/insts/data_transfer/stack_operations.py b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
index c381dc4f4..889e7b88b 100644
--- a/src/arch/x86/isa/insts/data_transfer/stack_operations.py
+++ b/src/arch/x86/isa/insts/data_transfer/stack_operations.py
@@ -62,6 +62,25 @@ def macroop POP_R {
     addi rsp, rsp, dsz
 };
 
+def macroop POP_M {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop POP_P {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    rdip t7
+    ld t1, ss, [0, t0, rsp]
+    addi rsp, rsp, dsz
+    st t1, ds, [0, t0, t7]
+};
+
 def macroop PUSH_R {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -70,6 +89,15 @@ def macroop PUSH_R {
     st reg, ss, [0, t0, rsp]
 };
 
+def macroop PUSH_I {
+    # Make the default data size of pops 64 bits in 64 bit mode
+    .adjust_env oszIn64Override
+
+    limm t1, imm
+    subi rsp, rsp, dsz
+    st t1, ss, [0, t0, rsp]
+};
+
 def macroop PUSH_M {
     # Make the default data size of pops 64 bits in 64 bit mode
     .adjust_env oszIn64Override
@@ -88,16 +116,32 @@ def macroop PUSH_P {
     subi rsp, rsp, dsz
     st t1, ss, [0, t0, rsp]
 };
+
+def macroop PUSHA {
+    st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
+    st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
+    subi rsp, rsp, "8 * env.dataSize"
+};
+
+def macroop POPA {
+    st rdi, ss, [0, t0, rsp], "0 * env.dataSize"
+    st rsi, ss, [0, t0, rsp], "1 * env.dataSize"
+    st rbp, ss, [0, t0, rsp], "2 * env.dataSize"
+    st rsp, ss, [0, t0, rsp], "3 * env.dataSize"
+    st rbx, ss, [0, t0, rsp], "4 * env.dataSize"
+    st rdx, ss, [0, t0, rsp], "5 * env.dataSize"
+    st rcx, ss, [0, t0, rsp], "6 * env.dataSize"
+    st rax, ss, [0, t0, rsp], "7 * env.dataSize"
+    addi rsp, rsp, "8 * env.dataSize"
+};
 '''
 #let {{
-#    class POPA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class POPAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHA(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class PUSHAD(Inst):
-#	"GenFault ${new UnimpInstFault}"
 #    class ENTER(Inst):
 #	"GenFault ${new UnimpInstFault}"
 #    class LEAVE(Inst):
diff --git a/src/arch/x86/isa/insts/logical.py b/src/arch/x86/isa/insts/logical.py
index f99638cac..bbc15f8fa 100644
--- a/src/arch/x86/isa/insts/logical.py
+++ b/src/arch/x86/isa/insts/logical.py
@@ -221,16 +221,27 @@ def macroop AND_P_R
     and t1, t1, reg
     st t1, ds, [scale, index, base], disp
 };
+
+def macroop NOT_R
+{
+    limm t1, -1
+    xor reg, reg, t1
+};
+
+def macroop NOT_M
+{
+    limm t1, -1
+    ld t2, ds, [scale, index, base], disp
+    xor t2, t2, t1
+    st t2, ds, [scale, index, base], disp
+};
+
+def macroop NOT_P
+{
+    limm t1, -1
+    rdip t7
+    ld t2, ds, [0, t0, t7], disp
+    xor t2, t2, t1
+    st t2, ds, [0, t0, t7], disp
+};
 '''
-#let {{
-#microcodeString = '''
-#    def macroop OR
-#    {
-#	Or reg reg regm
-#    };
-#    def macroop NOT
-#    {
-#	Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
-#    };
-#'''
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
index 0988f8815..538e641ab 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/rotate.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop ROL_R_I
 {
-    rol reg, reg, imm
+    roli reg, reg, imm
 };
 
 def macroop ROL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop ROL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rol t1, t1, imm
+    roli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_1_R
+{
+    roli reg, reg, 1
+};
+
+def macroop ROL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    roli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    roli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROL_R_R
+{
+    rol reg, reg, regm
+};
+
+def macroop ROL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rol t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rol t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop ROR_R_I
 {
-    ror reg, reg, imm
+    rori reg, reg, imm
 };
 
 def macroop ROR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop ROR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    ror t1, t1, imm
+    rori t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_1_R
+{
+    rori reg, reg, 1
+};
+
+def macroop ROR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rori t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rori t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop ROR_R_R
+{
+    ror reg, reg, regm
+};
+
+def macroop ROR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    ror t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop ROR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    ror t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCL_R_I
 {
-    rcl reg, reg, imm
+    rcli reg, reg, imm
 };
 
 def macroop RCL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,19 +190,59 @@ def macroop RCL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcl t1, t1, imm
+    rcli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_1_R
+{
+    rcli reg, reg, 1
+};
+
+def macroop RCL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCL_R_R
+{
+    rcl reg, reg, regm
+};
+
+def macroop RCL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop RCR_R_I
 {
-    rcr reg, reg, imm
+    rcri reg, reg, imm
 };
 
 def macroop RCR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -130,13 +250,47 @@ def macroop RCR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    rcr t1, t1, imm
+    rcri t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_1_R
+{
+    rcri reg, reg, 1
+};
+
+def macroop RCR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    rcri t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcri t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop RCR_R_R
+{
+    rcr reg, reg, regm
+};
+
+def macroop RCR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    rcr t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop RCR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    rcr t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class RCL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class RCR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/insts/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
index 5a04317d9..64eab3edc 100644
--- a/src/arch/x86/isa/insts/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/rotate_and_shift/shift.py
@@ -56,13 +56,13 @@
 microcode = '''
 def macroop SAL_R_I
 {
-    sll reg, reg, imm
+    slli reg, reg, imm
 };
 
 def macroop SAL_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -70,19 +70,59 @@ def macroop SAL_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sll t1, t1, imm
+    slli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_1_R
+{
+    slli reg, reg, 1
+};
+
+def macroop SAL_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    slli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    slli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAL_R_R
+{
+    sll reg, reg, regm
+};
+
+def macroop SAL_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sll t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAL_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sll t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SHR_R_I
 {
-    srl reg, reg, imm
+    srli reg, reg, imm
 };
 
 def macroop SHR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -90,19 +130,59 @@ def macroop SHR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    srl t1, t1, imm
+    srli t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_1_R
+{
+    srli reg, reg, 1
+};
+
+def macroop SHR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srli t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srli t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SHR_R_R
+{
+    srl reg, reg, regm
+};
+
+def macroop SHR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    srl t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SHR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srl t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 
 def macroop SAR_R_I
 {
-    sra reg, reg, imm
+    srai reg, reg, imm
 };
 
 def macroop SAR_M_I
 {
     ld t1, ds, [scale, index, base], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
     st t1, ds, [scale, index, base], disp
 };
 
@@ -110,21 +190,47 @@ def macroop SAR_P_I
 {
     rdip t7
     ld t1, ds, [0, t0, t7], disp
-    sra t1, t1, imm
+    srai t1, t1, imm
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_1_R
+{
+    srai reg, reg, 1
+};
+
+def macroop SAR_1_M
+{
+    ld t1, ds, [scale, index, base], disp
+    srai t1, t1, 1
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_1_P
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    srai t1, t1, 1
+    st t1, ds, [0, t0, t7], disp
+};
+
+def macroop SAR_R_R
+{
+    sra reg, reg, regm
+};
+
+def macroop SAR_M_R
+{
+    ld t1, ds, [scale, index, base], disp
+    sra t1, t1, reg
+    st t1, ds, [scale, index, base], disp
+};
+
+def macroop SAR_P_R
+{
+    rdip t7
+    ld t1, ds, [0, t0, t7], disp
+    sra t1, t1, reg
     st t1, ds, [0, t0, t7], disp
 };
 '''
-#let {{
-#    class SAL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SAR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHL(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHR(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHLD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SHRD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 8453a4fe9..4131246a4 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -196,18 +196,34 @@ let {{
             self.regUsed = False
             self.regm = "0"
             self.regmUsed = False
+            self.size = None
             self.addressSize = "ADDRSIZE"
             self.dataSize = "OPSIZE"
             self.stackSize = "STACKSIZE"
             self.doModRM = False
 
         def getAllocator(self):
+            if self.size == 'b':
+                self.dataSize = 1
+            elif self.size == 'd':
+                self.dataSize = 4
+            elif self.size == 'q':
+                self.dataSize = 8
+            elif self.size == 'v':
+                self.dataSize = "OPSIZE"
+            elif self.size == 'w':
+                self.dataSize = 2
+            elif self.size == 'z':
+                self.dataSize = "((OPSIZE == 8) ? 4 : OPSIZE)"
+            elif self.size:
+                raise Exception, "Unrecognized size type %s!" % self.size
             return '''EmulEnv(%(reg)s,
                               %(regm)s,
                               %(dataSize)s,
                               %(addressSize)s,
                               %(stackSize)s)''' % \
                 self.__dict__
+
         def addReg(self, reg):
             if not self.regUsed:
                 self.reg = reg
@@ -217,6 +233,13 @@ let {{
                 self.regmUsed = True
             else:
                 raise Exception, "EmulEnv is out of register specialization spots."
+        def setSize(self, size):
+            if not self.size:
+                self.size = size
+            else:
+                if self.size is not size:
+                    raise Exception, "Conflicting register sizes %s and %s!" %\
+                        (self.size, size)
 }};
 
 let {{
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index ccf519963..18cbc6082 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -123,24 +123,9 @@ def template MicroLoadExecute {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        unsigned flags = 0;
-        switch(dataSize)
-        {
-          case 1:
-            fault = xc->read(EA, (uint8_t&)Mem, flags);
-            break;
-          case 2:
-            fault = xc->read(EA, (uint16_t&)Mem, flags);
-            break;
-          case 4:
-            fault = xc->read(EA, (uint32_t&)Mem, flags);
-            break;
-          case 8:
-            fault = xc->read(EA, (uint64_t&)Mem, flags);
-            break;
-          default:
-            panic("Bad operand size!\n");
-        }
+        fault = read(xc, EA, Mem, 0);
+        int offset = EA & (dataSize - 1);
+        Mem = bits(Mem, (offset + dataSize) * 8 - 1,  offset * 8);
 
         if(fault == NoFault)
         {
@@ -167,24 +152,8 @@ def template MicroLoadInitiateAcc {{
         %(ea_code)s;
         DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
 
-        unsigned flags = 0;
-        switch(dataSize)
-        {
-          case 1:
-            fault = xc->read(EA, (uint8_t&)Mem, flags);
-            break;
-          case 2:
-            fault = xc->read(EA, (uint16_t&)Mem, flags);
-            break;
-          case 4:
-            fault = xc->read(EA, (uint32_t&)Mem, flags);
-            break;
-          case 8:
-            fault = xc->read(EA, (uint64_t&)Mem, flags);
-            break;
-          default:
-            panic("Bad operand size!\n");
-        }
+        int offset = EA & (dataSize - 1);
+        fault = read(xc, EA, Mem, offset);
 
         return fault;
     }
@@ -201,6 +170,8 @@ def template MicroLoadCompleteAcc {{
         %(op_rd)s;
 
         Mem = pkt->get<typeof(Mem)>();
+        int offset = pkt->flags;
+        Mem = bits(Mem, (offset + dataSize) * 8 - 1,  offset * 8);
         %(code)s;
 
         if(fault == NoFault)
@@ -230,30 +201,13 @@ def template MicroStoreExecute {{
 
         if(fault == NoFault)
         {
-            unsigned flags = 0;
-            uint64_t *res = 0;
-            switch(dataSize)
+            Mem = Mem << ((EA & (dataSize - 1)) * 8);
+            fault = write(xc, Mem, EA, 0);
+            if(fault == NoFault)
             {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, res);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, res);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, res);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, res);
-                break;
-              default:
-                panic("Bad operand size!\n");
+                %(op_wb)s;
             }
         }
-        if(fault == NoFault)
-        {
-            %(op_wb)s;
-        }
 
         return fault;
     }
@@ -275,30 +229,13 @@ def template MicroStoreInitiateAcc {{
 
         if(fault == NoFault)
         {
-            unsigned flags = 0;
-            uint64_t *res = 0;
-            switch(dataSize)
+            Mem = Mem << ((EA & (dataSize - 1)) * 8);
+            fault = write(xc, Mem, EA, 0);
+            if(fault == NoFault)
             {
-              case 1:
-                fault = xc->write((uint8_t&)Mem, EA, flags, res);
-                break;
-              case 2:
-                fault = xc->write((uint16_t&)Mem, EA, flags, res);
-                break;
-              case 4:
-                fault = xc->write((uint32_t&)Mem, EA, flags, res);
-                break;
-              case 8:
-                fault = xc->write((uint64_t&)Mem, EA, flags, res);
-                break;
-              default:
-                panic("Bad operand size!\n");
+                %(op_wb)s;
             }
         }
-        if(fault == NoFault)
-        {
-            %(op_wb)s;
-        }
         return fault;
     }
 }};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index dbbe11c90..bb34df7df 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -343,7 +343,7 @@ let {{
         immCode = matcher.sub("imm8", code)
 
         if subtract:
-            secondSrc = "-op2, true"
+            secondSrc = "~op2, true"
         else:
             secondSrc = "op2"
 
@@ -466,11 +466,11 @@ let {{
 
     # Shift instructions
     defineMicroRegOp('Sll', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
             ''')
     defineMicroRegOp('Srl', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             // Because what happens to the bits shift -in- on a right shift
             // is not defined in the C/C++ standard, we have to mask them out
             // to be sure they're zero.
@@ -478,7 +478,7 @@ let {{
             DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
             ''')
     defineMicroRegOp('Sra', '''
-            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+            uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             // Because what happens to the bits shift -in- on a right shift
             // is not defined in the C/C++ standard, we have to sign extend
             // them manually to be sure.
@@ -488,7 +488,7 @@ let {{
             ''')
     defineMicroRegOp('Ror', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
@@ -500,7 +500,7 @@ let {{
             ''')
     defineMicroRegOp('Rcr', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 CCFlagBits flags = ccFlagBits;
@@ -515,7 +515,7 @@ let {{
             ''')
     defineMicroRegOp('Rol', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 uint64_t top = SrcReg1 << shiftAmt;
@@ -528,7 +528,7 @@ let {{
             ''')
     defineMicroRegOp('Rcl', '''
             uint8_t shiftAmt =
-                (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
+                (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
             if(shiftAmt)
             {
                 CCFlagBits flags = ccFlagBits;
diff --git a/src/arch/x86/isa/specialize.isa b/src/arch/x86/isa/specialize.isa
index 5165ea206..a45c6e80f 100644
--- a/src/arch/x86/isa/specialize.isa
+++ b/src/arch/x86/isa/specialize.isa
@@ -114,7 +114,8 @@ let {{
             self.reg = match.group("reg")
             self.tag = match.group("tag")
             self.size = match.group("size")
-            self.rsize = match.group("rsize")
+            if not self.size:
+                self.size = match.group("rsize")
 
     ModRMRegIndex = "(MODRM_REG | (REX_R << 3))"
     ModRMRMIndex = "(MODRM_RM | (REX_B << 3))"
@@ -129,6 +130,10 @@ let {{
             opType = OpType(opTypes[0])
             opTypes.pop(0)
 
+            if opType.tag not in ("I", "J"):
+                if opType.size:
+                    env.setSize(opType.size)
+
             if opType.reg:
                 #Figure out what to do with fixed register operands
                 #This is the index to use, so we should stick it some place.
@@ -136,13 +141,6 @@ let {{
                     env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg)
                 else:
                     env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg)
-                if opType.size:
-                    if opType.rsize in ("l", "h", "b"):
-                        print "byte"
-                    elif opType.rsize == "x":
-                        print "word"
-                    else:
-                        print "Didn't recognize fixed register size %s!" % opType.rsize
                 Name += "_R"
             elif opType.tag == "B":
                 # This refers to registers whose index is encoded as part of the opcode
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 4c02ee35e..63bcfead9 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -99,12 +99,17 @@ namespace X86ISA
     const int ReturnAddressReg = 0;
     const int ReturnValueReg = INTREG_RAX;
     const int FramePointerReg = INTREG_RBP;
-    const int ArgumentReg0 = INTREG_RDI;
-    const int ArgumentReg1 = INTREG_RSI;
-    const int ArgumentReg2 = INTREG_RDX;
-    const int ArgumentReg3 = INTREG_RCX;
-    const int ArgumentReg4 = INTREG_R8W;
-    const int ArgumentReg5 = INTREG_R9W;
+    const int ArgumentReg[] = {
+        INTREG_RDI,
+        INTREG_RSI,
+        INTREG_RDX,
+        //This argument register is r10 for syscalls and rcx for C.
+        INTREG_R10W,
+        //INTREG_RCX,
+        INTREG_R8W,
+        INTREG_R9W
+    };
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
 
     // Some OS syscalls use a second register (rdx) to return a second
     // value
diff --git a/src/arch/x86/linux/linux.cc b/src/arch/x86/linux/linux.cc
index 59754d7b3..5e8d2de16 100644
--- a/src/arch/x86/linux/linux.cc
+++ b/src/arch/x86/linux/linux.cc
@@ -59,7 +59,7 @@
 #include <fcntl.h>
 
 // open(2) flags translation table
-OpenFlagTransTable X86Linux::openFlagTable[] = {
+OpenFlagTransTable X86Linux64::openFlagTable[] = {
 #ifdef _MSC_VER
   { TGT_O_RDONLY, _O_RDONLY },
   { TGT_O_WRONLY, _O_WRONLY },
@@ -93,6 +93,7 @@ OpenFlagTransTable X86Linux::openFlagTable[] = {
 #endif /* _MSC_VER */
 };
 
-const int X86Linux::NUM_OPEN_FLAGS =
-        (sizeof(X86Linux::openFlagTable)/sizeof(X86Linux::openFlagTable[0]));
+const int X86Linux64::NUM_OPEN_FLAGS =
+        sizeof(X86Linux64::openFlagTable) /
+        sizeof(X86Linux64::openFlagTable[0]);
 
diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh
index a276d4c0c..c1bb67260 100644
--- a/src/arch/x86/linux/linux.hh
+++ b/src/arch/x86/linux/linux.hh
@@ -60,7 +60,7 @@
 
 #include "kern/linux/linux.hh"
 
-class X86Linux : public Linux
+class X86Linux64 : public Linux
 {
   public:
 
@@ -104,6 +104,11 @@ class X86Linux : public Linux
     static const int NUM_OPEN_FLAGS;
 
     static const unsigned TGT_MAP_ANONYMOUS = 0x20;
+
+    typedef struct {
+        uint64_t iov_base; // void *
+        uint64_t iov_len;  // size_t
+    } tgt_iovec;
 };
 
 #endif
diff --git a/src/arch/x86/linux/syscalls.cc b/src/arch/x86/linux/syscalls.cc
index 30360e602..5c756ec7f 100644
--- a/src/arch/x86/linux/syscalls.cc
+++ b/src/arch/x86/linux/syscalls.cc
@@ -83,17 +83,17 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
 SyscallDesc X86LinuxProcess::syscallDescs[] = {
     /*   0 */ SyscallDesc("read", unimplementedFunc),
     /*   1 */ SyscallDesc("write", unimplementedFunc),
-    /*   2 */ SyscallDesc("open", openFunc<X86Linux>),
+    /*   2 */ SyscallDesc("open", openFunc<X86Linux64>),
     /*   3 */ SyscallDesc("close", unimplementedFunc),
     /*   4 */ SyscallDesc("stat", unimplementedFunc),
     /*   5 */ SyscallDesc("fstat", unimplementedFunc),
     /*   6 */ SyscallDesc("lstat", unimplementedFunc),
     /*   7 */ SyscallDesc("poll", unimplementedFunc),
     /*   8 */ SyscallDesc("lseek", unimplementedFunc),
-    /*   9 */ SyscallDesc("mmap", unimplementedFunc),
+    /*   9 */ SyscallDesc("mmap", mmapFunc<X86Linux64>),
     /*  10 */ SyscallDesc("mprotect", unimplementedFunc),
     /*  11 */ SyscallDesc("munmap", unimplementedFunc),
-    /*  12 */ SyscallDesc("brk", unimplementedFunc),
+    /*  12 */ SyscallDesc("brk", obreakFunc),
     /*  13 */ SyscallDesc("rt_sigaction", unimplementedFunc),
     /*  14 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
     /*  15 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
@@ -101,7 +101,7 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = {
     /*  17 */ SyscallDesc("pread64", unimplementedFunc),
     /*  18 */ SyscallDesc("pwrite64", unimplementedFunc),
     /*  19 */ SyscallDesc("readv", unimplementedFunc),
-    /*  20 */ SyscallDesc("writev", unimplementedFunc),
+    /*  20 */ SyscallDesc("writev", writevFunc<X86Linux64>),
     /*  21 */ SyscallDesc("access", unimplementedFunc),
     /*  22 */ SyscallDesc("pipe", unimplementedFunc),
     /*  23 */ SyscallDesc("select", unimplementedFunc),
@@ -183,13 +183,13 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = {
     /*  99 */ SyscallDesc("sysinfo", unimplementedFunc),
     /* 100 */ SyscallDesc("times", unimplementedFunc),
     /* 101 */ SyscallDesc("ptrace", unimplementedFunc),
-    /* 102 */ SyscallDesc("getuid", unimplementedFunc),
+    /* 102 */ SyscallDesc("getuid", getuidFunc),
     /* 103 */ SyscallDesc("syslog", unimplementedFunc),
-    /* 104 */ SyscallDesc("getgid", unimplementedFunc),
+    /* 104 */ SyscallDesc("getgid", getgidFunc),
     /* 105 */ SyscallDesc("setuid", unimplementedFunc),
     /* 106 */ SyscallDesc("setgid", unimplementedFunc),
-    /* 107 */ SyscallDesc("geteuid", unimplementedFunc),
-    /* 108 */ SyscallDesc("getegid", unimplementedFunc),
+    /* 107 */ SyscallDesc("geteuid", geteuidFunc),
+    /* 108 */ SyscallDesc("getegid", getegidFunc),
     /* 109 */ SyscallDesc("setpgid", unimplementedFunc),
     /* 110 */ SyscallDesc("getppid", unimplementedFunc),
     /* 111 */ SyscallDesc("getpgrp", unimplementedFunc),
diff --git a/src/arch/x86/predecoder.cc b/src/arch/x86/predecoder.cc
index 295ca10a4..7f8bc7abc 100644
--- a/src/arch/x86/predecoder.cc
+++ b/src/arch/x86/predecoder.cc
@@ -311,9 +311,19 @@ namespace X86ISA
             else
                 displacementSize = 0;
         }
+
+        // The "test" instruction in group 3 needs an immediate, even though
+        // the other instructions with the same actual opcode don't.
+        if (emi.opcode.num == 1 && (modRM.reg & 0x6) == 0) {
+           if (emi.opcode.op == 0xF6)
+               immediateSize = 1;
+           else if (emi.opcode.op == 0xF7)
+               immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
+        }
+
         //If there's an SIB, get that next.
         //There is no SIB in 16 bit mode.
-        if(modRM.rm == 4 && modRM.mod != 3) {
+        if (modRM.rm == 4 && modRM.mod != 3) {
                 // && in 32/64 bit mode)
             nextState = SIBState;
         } else if(displacementSize) {
@@ -339,9 +349,9 @@ namespace X86ISA
         emi.sib = nextByte;
         DPRINTF(Predecoder, "Found SIB byte %#x.\n", nextByte);
         consumeByte();
-        if(emi.modRM.mod == 0 && emi.sib.base == 5)
+        if (emi.modRM.mod == 0 && emi.sib.base == 5)
             displacementSize = 4;
-        if(displacementSize) {
+        if (displacementSize) {
             nextState = DisplacementState;
         } else if(immediateSize) {
             nextState = ImmediateState;
diff --git a/src/arch/x86/predecoder_tables.cc b/src/arch/x86/predecoder_tables.cc
index 6fe54b719..a8c719054 100644
--- a/src/arch/x86/predecoder_tables.cc
+++ b/src/arch/x86/predecoder_tables.cc
@@ -208,7 +208,7 @@ namespace X86ISA
 /*      4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
-/*      7 */ BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
+/*      7 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW,
 /*      9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
 /*      A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 ,
diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc
index 7deb54945..09962fdb6 100644
--- a/src/arch/x86/process.cc
+++ b/src/arch/x86/process.cc
@@ -338,8 +338,9 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
     initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
 
     //Set up the thread context to start running the process
-    threadContexts[0]->setIntReg(ArgumentReg0, argc);
-    threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    assert(NumArgumentRegs >= 2);
+    threadContexts[0]->setIntReg(ArgumentReg[0], argc);
+    threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
     threadContexts[0]->setIntReg(StackPointerReg, stack_min);
 
     Addr prog_entry = objFile->entryPoint();
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index cce13a072..adf47fa4d 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -72,7 +72,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
 if env['USE_CHECKER']:
     temp_cpu_list.append('CheckerCPU')
 
-# Generate header.  
+# Generate header.
 def gen_cpu_exec_signatures(target, source, env):
     f = open(str(target[0]), 'w')
     print >> f, '''
@@ -111,7 +111,6 @@ Source('base.cc')
 Source('cpuevent.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
-Source('op_class.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
 Source('static_inst.cc')
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index cf007a06b..3b8d85c9c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -42,7 +42,6 @@
 #include "cpu/thread_context.hh"
 #include "cpu/profile.hh"
 #include "sim/sim_exit.hh"
-#include "sim/param.hh"
 #include "sim/process.hh"
 #include "sim/sim_events.hh"
 #include "sim/system.hh"
@@ -455,6 +454,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
         functionEntryTick = curTick;
     }
 }
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 85df19348..25d41811e 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -46,7 +46,7 @@
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "cpu/static_inst.hh"
-#include "sim/param.hh"
+#include "enums/OpClass.hh"
 #include "sim/system.hh"
 
 #if FULL_SYSTEM
@@ -355,7 +355,7 @@ Trace::InstRecord::dump()
         outs << " : ";
 
         if (IsOn(ExecOpClass)) {
-            outs << opClassStrings[staticInst->opClass()] << " : ";
+            outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
         }
 
         if (IsOn(ExecResult) && data_status != DataInvalid) {
diff --git a/src/cpu/func_unit.cc b/src/cpu/func_unit.cc
index c20578a43..d7aeb5b37 100644
--- a/src/cpu/func_unit.cc
+++ b/src/cpu/func_unit.cc
@@ -32,7 +32,8 @@
 
 #include "base/misc.hh"
 #include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/OpDesc.hh"
+#include "params/FUDesc.hh"
 
 using namespace std;
 
@@ -116,56 +117,17 @@ FuncUnit::issueLatency(OpClass capability)
 //
 //  The operation-class description object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-    SimpleEnumParam<OpClass> opClass;
-    Param<unsigned>    opLat;
-    Param<unsigned>    issueLat;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-    INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
-    INIT_PARAM(opLat,        "cycles until result is available"),
-    INIT_PARAM(issueLat,     "cycles until another can be issued")
-
-END_INIT_SIM_OBJECT_PARAMS(OpDesc)
-
-
-CREATE_SIM_OBJECT(OpDesc)
+OpDesc *
+OpDescParams::create()
 {
-    return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
+    return new OpDesc(name, opClass, opLat, issueLat);
 }
 
-REGISTER_SIM_OBJECT("OpDesc", OpDesc)
-
-
 //
 //  The FuDesc object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-    SimObjectVectorParam<OpDesc *> opList;
-    Param<unsigned>                count;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-    INIT_PARAM(opList, "list of operation classes for this FU type"),
-    INIT_PARAM(count,  "number of these FU's available")
-
-END_INIT_SIM_OBJECT_PARAMS(FUDesc)
-
-
-CREATE_SIM_OBJECT(FUDesc)
+FUDesc *
+FUDescParams::create()
 {
-    return new FUDesc(getInstanceName(), opList, count);
+    return new FUDesc(name, opList, count);
 }
-
-REGISTER_SIM_OBJECT("FUDesc", FUDesc)
-
diff --git a/src/cpu/intr_control.cc b/src/cpu/intr_control.cc
index be0f6599b..e9f27e9ed 100644
--- a/src/cpu/intr_control.cc
+++ b/src/cpu/intr_control.cc
@@ -35,7 +35,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
-#include "sim/builder.hh"
+#include "params/IntrControl.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
@@ -76,21 +76,8 @@ IntrControl::clear(int cpu_id, int int_num, int index)
     temp->clear_interrupt(int_num, index);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-    SimObjectParam<System *> sys;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-    INIT_PARAM(sys, "the system we are part of")
-
-END_INIT_SIM_OBJECT_PARAMS(IntrControl)
-
-CREATE_SIM_OBJECT(IntrControl)
+IntrControl *
+IntrControlParams::create()
 {
-    return new IntrControl(getInstanceName(), sys);
+    return new IntrControl(name, sys);
 }
-
-REGISTER_SIM_OBJECT("IntrControl", IntrControl)
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 77816e8d1..86a33f44b 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -46,7 +46,7 @@
 #include "mem/packet.hh"
 //#include "mem/physical.hh"
 #include "mem/request.hh"
-#include "sim/builder.hh"
+#include "params/MemTest.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
 
@@ -410,53 +410,15 @@ MemTest::doRetry()
     }
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-//    SimObjectParam<BaseCache *> cache;
-//    SimObjectParam<PhysicalMemory *> main_mem;
-//    SimObjectParam<PhysicalMemory *> check_mem;
-    Param<unsigned> memory_size;
-    Param<unsigned> percent_reads;
-    Param<unsigned> percent_functional;
-    Param<unsigned> percent_uncacheable;
-    Param<unsigned> progress_interval;
-    Param<unsigned> percent_source_unaligned;
-    Param<unsigned> percent_dest_unaligned;
-    Param<Addr> trace_addr;
-    Param<Counter> max_loads;
-    Param<bool> atomic;
-
-END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-//    INIT_PARAM(cache, "L1 cache"),
-//    INIT_PARAM(main_mem, "hierarchical memory"),
-//    INIT_PARAM(check_mem, "check memory"),
-    INIT_PARAM(memory_size, "memory size"),
-    INIT_PARAM(percent_reads, "target read percentage"),
-    INIT_PARAM(percent_functional, "percentage of access that are functional"),
-    INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
-    INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
-    INIT_PARAM(percent_source_unaligned,
-               "percent of copy source address that are unaligned"),
-    INIT_PARAM(percent_dest_unaligned,
-               "percent of copy dest address that are unaligned"),
-    INIT_PARAM(trace_addr, "address to trace"),
-                              INIT_PARAM(max_loads, "terminate when we have reached this load count"),
-    INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
-
-END_INIT_SIM_OBJECT_PARAMS(MemTest)
-
-
-CREATE_SIM_OBJECT(MemTest)
+MemTest *
+MemTestParams::create()
 {
-    return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
-                       /*check_mem,*/ memory_size, percent_reads, percent_functional,
+    return new MemTest(name,
+#if 0
+                       cache->getInterface(), main_mem, check_mem,
+#endif
+                       memory_size, percent_reads, percent_functional,
                        percent_uncacheable, progress_interval,
                        percent_source_unaligned, percent_dest_unaligned,
                        trace_addr, max_loads, atomic);
 }
-
-REGISTER_SIM_OBJECT("MemTest", MemTest)
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 34754d3c5..58ee52a39 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -30,12 +30,13 @@
 
 #include <string>
 
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/alpha/cpu.hh"
 #include "cpu/o3/alpha/impl.hh"
 #include "cpu/o3/alpha/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
 {
@@ -45,245 +46,8 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    Param<int> clock;
-    Param<int> phase;
-    Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-SimObjectParam<AlphaISA::ITB *> itb;
-SimObjectParam<AlphaISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
 {
     DerivO3CPU *cpu;
 
@@ -294,8 +58,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
-         numThreads : workload.size();
+        (numThreads >= workload.size()) ? numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -307,7 +70,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
@@ -325,7 +88,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->workload = workload;
 #endif // FULL_SYSTEM
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +194,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 1754300d2..7f8f0547b 100644
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -293,14 +293,16 @@ template <class Impl>
 TheISA::IntReg
 AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
-    return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
+    assert(i < TheISA::NumArgumentRegs);
+    return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid);
 }
 
 template <class Impl>
 void
 AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
 {
-    this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
+    assert(i < TheISA::NumArgumentRegs);
+    this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 8b028e3a0..97425b08c 100644
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -34,7 +34,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/o3/alpha/dyn_inst.hh"
 #include "cpu/o3/alpha/impl.hh"
-#include "sim/builder.hh"
+#include "params/O3Checker.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -58,73 +58,11 @@ class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> >
 //
 //  CheckerCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-    Param<Tick> profile;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-    Param<int> clock;
-
-    Param<bool> defer_registration;
-    Param<bool> exitOnError;
-    Param<bool> updateOnError;
-    Param<bool> warnOnlyOnLoadError;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(profile, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(exitOnError, "exit on error"),
-    INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
-    INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
-                    "result errors", false),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(O3Checker)
-
-
-CREATE_SIM_OBJECT(O3Checker)
+O3Checker *
+O3CheckerParams::create()
 {
     O3Checker::Params *params = new O3Checker::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = 0;
     params->max_insts_all_threads = 0;
@@ -161,5 +99,3 @@ CREATE_SIM_OBJECT(O3Checker)
     O3Checker *cpu = new O3Checker(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("O3Checker", O3Checker)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2bf8f9832..cae6ae20c 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -32,22 +32,22 @@
 #include "config/full_system.hh"
 #include "config/use_checker.hh"
 
-#if FULL_SYSTEM
-#include "cpu/quiesce_event.hh"
-#include "sim/system.hh"
-#else
-#include "sim/process.hh"
-#endif
-
 #include "cpu/activity.hh"
 #include "cpu/simple_thread.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/cpu.hh"
-
+#include "enums/MemoryMode.hh"
 #include "sim/core.hh"
 #include "sim/stat_control.hh"
 
+#if FULL_SYSTEM
+#include "cpu/quiesce_event.hh"
+#include "sim/system.hh"
+#else
+#include "sim/process.hh"
+#endif
+
 #if USE_CHECKER
 #include "cpu/checker/cpu.hh"
 #endif
@@ -882,7 +882,7 @@ FullO3CPU<Impl>::resume()
         return;
 
 #if FULL_SYSTEM
-    assert(system->getMemoryMode() == System::Timing);
+    assert(system->getMemoryMode() == Enums::timing);
 #endif
 
     if (!tickEvent.scheduled())
diff --git a/src/cpu/o3/fu_pool.cc b/src/cpu/o3/fu_pool.cc
index 42e329aca..09d271b10 100644
--- a/src/cpu/o3/fu_pool.cc
+++ b/src/cpu/o3/fu_pool.cc
@@ -32,7 +32,7 @@
 
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/func_unit.hh"
-#include "sim/builder.hh"
+#include "params/FUPool.hh"
 
 using namespace std;
 
@@ -275,25 +275,8 @@ FUPool::takeOverFrom()
 //
 //  The FuPool object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
-    SimObjectVectorParam<FUDesc *> FUList;
-
-END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-    INIT_PARAM(FUList, "list of FU's for this pool")
-
-END_INIT_SIM_OBJECT_PARAMS(FUPool)
-
-
-CREATE_SIM_OBJECT(FUPool)
+FUPool *
+FUPoolParams::create()
 {
-    return new FUPool(getInstanceName(), FUList);
+    return new FUPool(name, FUList);
 }
-
-REGISTER_SIM_OBJECT("FUPool", FUPool)
-
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 99bffe1a6..47f019ebe 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -32,10 +32,10 @@
 #include <limits>
 #include <vector>
 
-#include "sim/core.hh"
-
 #include "cpu/o3/fu_pool.hh"
 #include "cpu/o3/inst_queue.hh"
+#include "enums/OpClass.hh"
+#include "sim/core.hh"
 
 template <class Impl>
 InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
@@ -259,12 +259,12 @@ InstructionQueue<Impl>::regStats()
     }
 */
     statIssuedInstType
-        .init(numThreads,Num_OpClasses)
+        .init(numThreads,Enums::Num_OpClass)
         .name(name() + ".ISSUE:FU_type")
         .desc("Type of FU issued")
         .flags(total | pdf | dist)
         ;
-    statIssuedInstType.ysubnames(opClassStrings);
+    statIssuedInstType.ysubnames(Enums::OpClassStrings);
 
     //
     //  How long did instructions for a particular FU type wait prior to issue
@@ -297,7 +297,7 @@ InstructionQueue<Impl>::regStats()
         .flags(pdf | dist)
         ;
     for (int i=0; i < Num_OpClasses; ++i) {
-        statFuBusy.subname(i, opClassStrings[i]);
+        statFuBusy.subname(i, Enums::OpClassStrings[i]);
     }
 
     fuBusy
diff --git a/src/cpu/o3/mips/cpu_builder.cc b/src/cpu/o3/mips/cpu_builder.cc
index c6acc0bfb..6a30ff099 100644
--- a/src/cpu/o3/mips/cpu_builder.cc
+++ b/src/cpu/o3/mips/cpu_builder.cc
@@ -31,12 +31,13 @@
 
 #include <string>
 
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/mips/cpu.hh"
 #include "cpu/o3/mips/impl.hh"
 #include "cpu/o3/mips/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
 {
@@ -46,229 +47,15 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-Param<int> clock;
-Param<int> phase;
-Param<int> numThreads;
-Param<int> cpu_id;
-Param<int> activity;
-
-SimObjectVectorParam<Process *> workload;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-Param<unsigned> cachePorts;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> dispatchWidth;
-Param<unsigned> issueWidth;
-Param<unsigned> wbWidth;
-Param<unsigned> wbDepth;
-SimObjectParam<FUPool *> fuPool;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-Param<Tick> trapLatency;
-
-Param<unsigned> backComSize;
-Param<unsigned> forwardComSize;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-    INIT_PARAM(workload, "Processes to run"),
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
 {
     DerivO3CPU *cpu;
 
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
-         numThreads : workload.size();
+        (numThreads >= workload.size()) ? numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -279,14 +66,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
 
     params->workload = workload;
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -389,6 +178,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/o3/mips/cpu_impl.hh b/src/cpu/o3/mips/cpu_impl.hh
index d1135f048..09d73b4a2 100644
--- a/src/cpu/o3/mips/cpu_impl.hh
+++ b/src/cpu/o3/mips/cpu_impl.hh
@@ -196,14 +196,16 @@ template <class Impl>
 TheISA::IntReg
 MipsO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
-    return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid);
+    assert(i < TheISA::NumArgumentRegs);
+    return this->readArchIntReg(MipsISA::ArgumentReg[i], tid);
 }
 
 template <class Impl>
 void
 MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
 {
-    this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid);
+    assert(i < TheISA::NumArgumentRegs);
+    this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc
index 35badce2c..35d9e2895 100644
--- a/src/cpu/o3/sparc/cpu_builder.cc
+++ b/src/cpu/o3/sparc/cpu_builder.cc
@@ -30,12 +30,14 @@
 
 #include <string>
 
+#include "config/full_system.hh"
+#include "config/use_checker.hh"
 #include "cpu/base.hh"
 #include "cpu/o3/sparc/cpu.hh"
 #include "cpu/o3/sparc/impl.hh"
 #include "cpu/o3/sparc/params.hh"
 #include "cpu/o3/fu_pool.hh"
-#include "sim/builder.hh"
+#include "params/DerivO3CPU.hh"
 
 class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
 {
@@ -45,245 +47,8 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
     { }
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    Param<int> clock;
-    Param<int> phase;
-    Param<int> numThreads;
-    Param<int> cpu_id;
-    Param<int> activity;
-
-#if FULL_SYSTEM
-    SimObjectParam<System *> system;
-    SimObjectParam<SparcISA::ITB *> itb;
-    SimObjectParam<SparcISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectVectorParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    SimObjectParam<BaseCPU *> checker;
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-    Param<unsigned> cachePorts;
-
-    Param<unsigned> decodeToFetchDelay;
-    Param<unsigned> renameToFetchDelay;
-    Param<unsigned> iewToFetchDelay;
-    Param<unsigned> commitToFetchDelay;
-    Param<unsigned> fetchWidth;
-
-    Param<unsigned> renameToDecodeDelay;
-    Param<unsigned> iewToDecodeDelay;
-    Param<unsigned> commitToDecodeDelay;
-    Param<unsigned> fetchToDecodeDelay;
-    Param<unsigned> decodeWidth;
-
-    Param<unsigned> iewToRenameDelay;
-    Param<unsigned> commitToRenameDelay;
-    Param<unsigned> decodeToRenameDelay;
-    Param<unsigned> renameWidth;
-
-    Param<unsigned> commitToIEWDelay;
-    Param<unsigned> renameToIEWDelay;
-    Param<unsigned> issueToExecuteDelay;
-    Param<unsigned> dispatchWidth;
-    Param<unsigned> issueWidth;
-    Param<unsigned> wbWidth;
-    Param<unsigned> wbDepth;
-    SimObjectParam<FUPool *> fuPool;
-
-    Param<unsigned> iewToCommitDelay;
-    Param<unsigned> renameToROBDelay;
-    Param<unsigned> commitWidth;
-    Param<unsigned> squashWidth;
-    Param<Tick> trapLatency;
-
-    Param<unsigned> backComSize;
-    Param<unsigned> forwardComSize;
-
-    Param<std::string> predType;
-    Param<unsigned> localPredictorSize;
-    Param<unsigned> localCtrBits;
-    Param<unsigned> localHistoryTableSize;
-    Param<unsigned> localHistoryBits;
-    Param<unsigned> globalPredictorSize;
-    Param<unsigned> globalCtrBits;
-    Param<unsigned> globalHistoryBits;
-    Param<unsigned> choicePredictorSize;
-    Param<unsigned> choiceCtrBits;
-
-    Param<unsigned> BTBEntries;
-    Param<unsigned> BTBTagSize;
-
-    Param<unsigned> RASSize;
-
-    Param<unsigned> LQEntries;
-    Param<unsigned> SQEntries;
-    Param<unsigned> LFSTSize;
-    Param<unsigned> SSITSize;
-
-    Param<unsigned> numPhysIntRegs;
-    Param<unsigned> numPhysFloatRegs;
-    Param<unsigned> numIQEntries;
-    Param<unsigned> numROBEntries;
-
-    Param<unsigned> smtNumFetchingThreads;
-    Param<std::string>   smtFetchPolicy;
-    Param<std::string>   smtLSQPolicy;
-    Param<unsigned> smtLSQThreshold;
-    Param<std::string>   smtIQPolicy;
-    Param<unsigned> smtIQThreshold;
-    Param<std::string>   smtROBPolicy;
-    Param<unsigned> smtROBThreshold;
-    Param<std::string>   smtCommitPolicy;
-
-    Param<unsigned> instShiftAmt;
-
-    Param<bool> defer_registration;
-
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM_DFLT(activity, "Initial activity count", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(dispatchWidth, "Dispatch width"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(wbWidth, "Writeback width"),
-    INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
-    INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-    INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
-
-    INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
-    INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
-
-CREATE_SIM_OBJECT(DerivO3CPU)
+DerivO3CPU *
+DerivO3CPUParams::create()
 {
     DerivO3CPU *cpu;
 
@@ -294,8 +59,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     // In non-full-system mode, we infer the number of threads from
     // the workload if it's not explicitly specified.
     int actual_num_threads =
-        (numThreads.isValid() && numThreads >= workload.size()) ?
-         numThreads : workload.size();
+        (numThreads >= workload.size()) ? numThreads : workload.size();
 
     if (workload.size() == 0) {
         fatal("Must specify at least one workload!");
@@ -307,7 +71,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->clock = clock;
     params->phase = phase;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
     params->cpu_id = cpu_id;
     params->activity = activity;
@@ -325,7 +89,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
     params->workload = workload;
 #endif // FULL_SYSTEM
 
+#if USE_CHECKER
     params->checker = checker;
+#endif
 
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -429,6 +195,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
-
diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 2e398577e..068057fc0 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -270,8 +270,9 @@ template <class Impl>
 TheISA::IntReg
 SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
+    assert(i < TheISA::NumArgumentRegs);
     TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
-            SparcISA::ArgumentReg0 + i);
+            SparcISA::ArgumentReg[i]);
     TheISA::IntReg val = this->readArchIntReg(idx, tid);
     if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3))
         val = bits(val, 31, 0);
@@ -282,8 +283,9 @@ template <class Impl>
 void
 SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
 {
+    assert(i < TheISA::NumArgumentRegs);
     TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
-            SparcISA::ArgumentReg0 + i);
+            SparcISA::ArgumentReg[i]);
     this->setArchIntReg(idx, val, tid);
 }
 
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 71819c904..8cbe10f91 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -25,43 +25,35 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Steve Reinhardt
- *          Nathan Binkert
+ * Authors: Nathan Binkert
  */
 
 #ifndef __CPU__OP_CLASS_HH__
 #define __CPU__OP_CLASS_HH__
 
-/**
- * @file
- * Definition of operation classes.
- */
+#include "enums/OpClass.hh"
 
-/**
- * Instruction operation classes.  These classes are used for
- * assigning instructions to functional units.
+/*
+ * Do a bunch of wonky stuff to maintain backward compatability so I
+ * don't have to change code in a zillion places.
  */
-enum OpClass {
-    No_OpClass = 0,	///< Instruction does not use a functional unit
-    IntAluOp,		///< Integer ALU operaton (add/sub/logical)
-    IntMultOp,		///< Integer multiply
-    IntDivOp,		///< Integer divide
-    FloatAddOp,		///< Floating point add/subtract
-    FloatCmpOp,		///< Floating point comparison
-    FloatCvtOp,		///< Floating point<->integer conversion
-    FloatMultOp,	///< Floating point multiply
-    FloatDivOp,		///< Floating point divide
-    FloatSqrtOp,	///< Floating point square root
-    MemReadOp,		///< Memory read port
-    MemWriteOp,		///< Memory write port
-    IprAccessOp,	///< Internal Processor Register read/write port
-    InstPrefetchOp,	///< Instruction prefetch port (on I-cache)
-    Num_OpClasses	///< Total number of operation classes
-};
+using Enums::OpClass;
+using Enums::No_OpClass;
+using Enums::Num_OpClass;
 
-/**
- * Array mapping OpClass enum values to strings.  Defined in op_class.cc.
- */
-extern const char *opClassStrings[Num_OpClasses];
+const OpClass IntAluOp = Enums::IntAlu;
+const OpClass IntMultOp = Enums::IntMult;
+const OpClass IntDivOp = Enums::IntDiv;
+const OpClass FloatAddOp = Enums::FloatAdd;
+const OpClass FloatCmpOp = Enums::FloatCmp;
+const OpClass FloatCvtOp = Enums::FloatCvt;
+const OpClass FloatMultOp = Enums::FloatMult;
+const OpClass FloatDivOp = Enums::FloatDiv;
+const OpClass FloatSqrtOp = Enums::FloatSqrt;
+const OpClass MemReadOp = Enums::MemRead;
+const OpClass MemWriteOp = Enums::MemWrite;
+const OpClass IprAccessOp = Enums::IprAccess;
+const OpClass InstPrefetchOp = Enums::InstPrefetch;
+const OpClass Num_OpClasses = Num_OpClass;
 
 #endif // __CPU__OP_CLASS_HH__
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index 9ad1e639f..f813e5df2 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -34,7 +34,7 @@
 #include "cpu/inst_seq.hh"
 #include "cpu/ozone/dyn_inst.hh"
 #include "cpu/ozone/ozone_impl.hh"
-#include "sim/builder.hh"
+#include "params/OzoneChecker.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -59,73 +59,11 @@ class OzoneChecker :
 //
 //  CheckerCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-    Param<Tick> profile;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-    Param<int> clock;
-
-    Param<bool> defer_registration;
-    Param<bool> exitOnError;
-    Param<bool> updateOnError;
-    Param<bool> warnOnlyOnLoadError;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(profile, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(exitOnError, "exit on error"),
-    INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
-    INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
-                    "result errors", false),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
-
-
-CREATE_SIM_OBJECT(OzoneChecker)
+OzoneChecker *
+OzoneCheckerParams::create()
 {
     OzoneChecker::Params *params = new OzoneChecker::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = 0;
     params->max_insts_all_threads = 0;
@@ -162,5 +100,3 @@ CREATE_SIM_OBJECT(OzoneChecker)
     OzoneChecker *cpu = new OzoneChecker(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 2432df55e..92b00af26 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -253,11 +253,17 @@ class OzoneCPU : public BaseCPU
 
 #if !FULL_SYSTEM
         TheISA::IntReg getSyscallArg(int i)
-        { return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
+        {
+            assert(i < TheISA::NumArgumentRegs);
+            return thread->renameTable[TheISA::ArgumentReg[i]]->readIntResult();
+        }
 
         // used to shift args for indirect syscall
         void setSyscallArg(int i, TheISA::IntReg val)
-        { thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
+        {
+            assert(i < TheISA::NumArgumentRegs);
+            thread->renameTable[TheISA::ArgumentReg[i]]->setIntResult(i);
+        }
 
         void setSyscallReturn(SyscallReturn return_value)
         { cpu->setSyscallReturn(return_value, thread->readTid()); }
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index e7ecfc496..60ee9c4f9 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -35,7 +35,7 @@
 #include "cpu/ozone/cpu.hh"
 #include "cpu/ozone/ozone_impl.hh"
 #include "cpu/ozone/simple_params.hh"
-#include "sim/builder.hh"
+#include "params/DerivOzoneCPU.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -52,271 +52,8 @@ class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
 //
 //  OzoneCPU Simulation Object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-    Param<int> clock;
-    Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-Param<Tick> profile;
-
-Param<bool> do_quiesce;
-Param<bool> do_checkpoint_insts;
-Param<bool> do_statistics_insts;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-Param<Tick> progress_interval;
-
-//SimObjectParam<BaseCache *> icache;
-//SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndLatency;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndLatency;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-Param<unsigned> maxOutstandingMemOps;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<bool> lsqLimits;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-//    INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-    INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
-
-//    INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-//    INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-    INIT_PARAM_DFLT(width, "Width", 1),
-    INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
-    INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
-    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
-    INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
-    INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
-    INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
-    INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-    INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(executeWidth, "Execute width"),
-    INIT_PARAM(executeIntWidth, "Integer execute width"),
-    INIT_PARAM(executeFloatWidth, "Floating point execute width"),
-    INIT_PARAM(executeBranchWidth, "Branch execute width"),
-    INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
-    INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
-    INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
-
-CREATE_SIM_OBJECT(DerivOzoneCPU)
+DerivOzoneCPU *
+DerivOzoneCPUParams::create()
 {
     DerivOzoneCPU *cpu;
 
@@ -339,7 +76,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     params->clock = clock;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
 
 #if FULL_SYSTEM
@@ -464,5 +201,3 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index e7214d2ba..df8e25fd0 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -36,7 +36,7 @@
 #include "cpu/ozone/simple_impl.hh"
 #include "cpu/ozone/simple_params.hh"
 #include "mem/cache/base_cache.hh"
-#include "sim/builder.hh"
+#include "sim/SimpleOzoneCPU.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 
@@ -55,258 +55,8 @@ class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
 //
 //  OzoneCPU Simulation Object
 //
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-    Param<int> clock;
-    Param<int> numThreads;
-
-#if FULL_SYSTEM
-SimObjectParam<System *> system;
-Param<int> cpu_id;
-SimObjectParam<TheISA::ITB *> itb;
-SimObjectParam<TheISA::DTB *> dtb;
-#else
-SimObjectVectorParam<Process *> workload;
-//SimObjectParam<PageTable *> page_table;
-#endif // FULL_SYSTEM
-
-SimObjectParam<FunctionalMemory *> mem;
-
-SimObjectParam<BaseCPU *> checker;
-
-Param<Counter> max_insts_any_thread;
-Param<Counter> max_insts_all_threads;
-Param<Counter> max_loads_any_thread;
-Param<Counter> max_loads_all_threads;
-
-SimObjectParam<BaseCache *> icache;
-SimObjectParam<BaseCache *> dcache;
-
-Param<unsigned> cachePorts;
-Param<unsigned> width;
-Param<unsigned> frontEndWidth;
-Param<unsigned> backEndWidth;
-Param<unsigned> backEndSquashLatency;
-Param<unsigned> backEndLatency;
-Param<unsigned> maxInstBufferSize;
-Param<unsigned> numPhysicalRegs;
-
-Param<unsigned> decodeToFetchDelay;
-Param<unsigned> renameToFetchDelay;
-Param<unsigned> iewToFetchDelay;
-Param<unsigned> commitToFetchDelay;
-Param<unsigned> fetchWidth;
-
-Param<unsigned> renameToDecodeDelay;
-Param<unsigned> iewToDecodeDelay;
-Param<unsigned> commitToDecodeDelay;
-Param<unsigned> fetchToDecodeDelay;
-Param<unsigned> decodeWidth;
-
-Param<unsigned> iewToRenameDelay;
-Param<unsigned> commitToRenameDelay;
-Param<unsigned> decodeToRenameDelay;
-Param<unsigned> renameWidth;
-
-Param<unsigned> commitToIEWDelay;
-Param<unsigned> renameToIEWDelay;
-Param<unsigned> issueToExecuteDelay;
-Param<unsigned> issueWidth;
-Param<unsigned> executeWidth;
-Param<unsigned> executeIntWidth;
-Param<unsigned> executeFloatWidth;
-Param<unsigned> executeBranchWidth;
-Param<unsigned> executeMemoryWidth;
-
-Param<unsigned> iewToCommitDelay;
-Param<unsigned> renameToROBDelay;
-Param<unsigned> commitWidth;
-Param<unsigned> squashWidth;
-
-Param<std::string> predType;
-Param<unsigned> localPredictorSize;
-Param<unsigned> localCtrBits;
-Param<unsigned> localHistoryTableSize;
-Param<unsigned> localHistoryBits;
-Param<unsigned> globalPredictorSize;
-Param<unsigned> globalCtrBits;
-Param<unsigned> globalHistoryBits;
-Param<unsigned> choicePredictorSize;
-Param<unsigned> choiceCtrBits;
-
-Param<unsigned> BTBEntries;
-Param<unsigned> BTBTagSize;
-
-Param<unsigned> RASSize;
-
-Param<unsigned> LQEntries;
-Param<unsigned> SQEntries;
-Param<unsigned> LFSTSize;
-Param<unsigned> SSITSize;
-
-Param<unsigned> numPhysIntRegs;
-Param<unsigned> numPhysFloatRegs;
-Param<unsigned> numIQEntries;
-Param<unsigned> numROBEntries;
-
-Param<bool> decoupledFrontEnd;
-Param<int> dispatchWidth;
-Param<int> wbWidth;
-
-Param<unsigned> smtNumFetchingThreads;
-Param<std::string>   smtFetchPolicy;
-Param<std::string>   smtLSQPolicy;
-Param<unsigned> smtLSQThreshold;
-Param<std::string>   smtIQPolicy;
-Param<unsigned> smtIQThreshold;
-Param<std::string>   smtROBPolicy;
-Param<unsigned> smtROBThreshold;
-Param<std::string>   smtCommitPolicy;
-
-Param<unsigned> instShiftAmt;
-
-Param<bool> defer_registration;
-
-Param<bool> function_trace;
-Param<Tick> function_trace_start;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM(numThreads, "number of HW thread contexts"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(system, "System object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-    INIT_PARAM(itb, "Instruction translation buffer"),
-    INIT_PARAM(dtb, "Data translation buffer"),
-#else
-    INIT_PARAM(workload, "Processes to run"),
-//    INIT_PARAM(page_table, "Page table"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM_DFLT(mem, "Memory", NULL),
-
-    INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
-
-    INIT_PARAM_DFLT(max_insts_any_thread,
-                    "Terminate when any thread reaches this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_insts_all_threads,
-                    "Terminate when all threads have reached"
-                    "this inst count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_any_thread,
-                    "Terminate when any thread reaches this load count",
-                    0),
-    INIT_PARAM_DFLT(max_loads_all_threads,
-                    "Terminate when all threads have reached this load"
-                    "count",
-                    0),
-
-    INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
-    INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
-
-    INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
-    INIT_PARAM_DFLT(width, "Width", 1),
-    INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
-    INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
-    INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
-    INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
-    INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
-    INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
-
-    INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
-    INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
-    INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
-               "delay"),
-    INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
-    INIT_PARAM(fetchWidth, "Fetch width"),
-    INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
-    INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
-               "delay"),
-    INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
-    INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
-    INIT_PARAM(decodeWidth, "Decode width"),
-
-    INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
-               "delay"),
-    INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
-    INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
-    INIT_PARAM(renameWidth, "Rename width"),
-
-    INIT_PARAM(commitToIEWDelay, "Commit to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(renameToIEWDelay, "Rename to "
-               "Issue/Execute/Writeback delay"),
-    INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
-               "to the IEW stage)"),
-    INIT_PARAM(issueWidth, "Issue width"),
-    INIT_PARAM(executeWidth, "Execute width"),
-    INIT_PARAM(executeIntWidth, "Integer execute width"),
-    INIT_PARAM(executeFloatWidth, "Floating point execute width"),
-    INIT_PARAM(executeBranchWidth, "Branch execute width"),
-    INIT_PARAM(executeMemoryWidth, "Memory execute width"),
-
-    INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
-               "delay"),
-    INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
-    INIT_PARAM(commitWidth, "Commit width"),
-    INIT_PARAM(squashWidth, "Squash width"),
-
-    INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
-    INIT_PARAM(localPredictorSize, "Size of local predictor"),
-    INIT_PARAM(localCtrBits, "Bits per counter"),
-    INIT_PARAM(localHistoryTableSize, "Size of local history table"),
-    INIT_PARAM(localHistoryBits, "Bits for the local history"),
-    INIT_PARAM(globalPredictorSize, "Size of global predictor"),
-    INIT_PARAM(globalCtrBits, "Bits per counter"),
-    INIT_PARAM(globalHistoryBits, "Bits of history"),
-    INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
-    INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
-
-    INIT_PARAM(BTBEntries, "Number of BTB entries"),
-    INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
-
-    INIT_PARAM(RASSize, "RAS size"),
-
-    INIT_PARAM(LQEntries, "Number of load queue entries"),
-    INIT_PARAM(SQEntries, "Number of store queue entries"),
-    INIT_PARAM(LFSTSize, "Last fetched store table size"),
-    INIT_PARAM(SSITSize, "Store set ID table size"),
-
-    INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
-    INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
-               "registers"),
-    INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
-    INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
-
-    INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
-    INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
-    INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
-
-    INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
-    INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
-    INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
-    INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
-    INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
-    INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
-    INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
-    INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
-
-    INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
-
-CREATE_SIM_OBJECT(SimpleOzoneCPU)
+SimpleOzoneCPU *
+SimpleOzoneCPUParams::create()
 {
     SimpleOzoneCPU *cpu;
 
@@ -329,7 +79,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
 
     params->clock = clock;
 
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = actual_num_threads;
 
 #if FULL_SYSTEM
@@ -447,6 +197,3 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
 
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
-
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 01eb4873e..054f67d69 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -36,7 +36,7 @@
 #include "cpu/simple/atomic.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/AtomicSimpleCPU.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -184,7 +184,7 @@ void
 AtomicSimpleCPU::resume()
 {
     if (_status != SwitchedOut && _status != Idle) {
-        assert(system->getMemoryMode() == System::Atomic);
+        assert(system->getMemoryMode() == Enums::atomic);
 
         changeState(SimObject::Running);
         if (thread->status() == ThreadContext::Active) {
@@ -548,79 +548,11 @@ AtomicSimpleCPU::tick()
 //
 //  AtomicSimpleCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    Param<int> clock;
-    Param<int> phase;
-
-    Param<bool> defer_registration;
-    Param<int> width;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-    Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(width, "cpu width"),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
-    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
-
-
-CREATE_SIM_OBJECT(AtomicSimpleCPU)
+AtomicSimpleCPU *
+AtomicSimpleCPUParams::create()
 {
     AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -645,12 +577,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
 #else
-    params->process = workload;
+    if (workload.size() != 1)
+        panic("only one workload allowed");
+    params->process = workload[0];
 #endif
 
     AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
-
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9285aa7b5..4359ebebf 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -47,7 +47,6 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 0c03815b5..b1cb80949 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -35,7 +35,7 @@
 #include "cpu/simple/timing.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/TimingSimpleCPU.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -158,7 +158,7 @@ void
 TimingSimpleCPU::resume()
 {
     if (_status != SwitchedOut && _status != Idle) {
-        assert(system->getMemoryMode() == System::Timing);
+        assert(system->getMemoryMode() == Enums::timing);
 
         // Delete the old event if it existed.
         if (fetchEvent) {
@@ -707,79 +707,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
 //
 //  TimingSimpleCPU Simulation Object
 //
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-    Param<Counter> max_insts_any_thread;
-    Param<Counter> max_insts_all_threads;
-    Param<Counter> max_loads_any_thread;
-    Param<Counter> max_loads_all_threads;
-    Param<Tick> progress_interval;
-    SimObjectParam<System *> system;
-    Param<int> cpu_id;
-
-#if FULL_SYSTEM
-    SimObjectParam<TheISA::ITB *> itb;
-    SimObjectParam<TheISA::DTB *> dtb;
-    Param<Tick> profile;
-
-    Param<bool> do_quiesce;
-    Param<bool> do_checkpoint_insts;
-    Param<bool> do_statistics_insts;
-#else
-    SimObjectParam<Process *> workload;
-#endif // FULL_SYSTEM
-
-    Param<int> clock;
-    Param<int> phase;
-
-    Param<bool> defer_registration;
-    Param<int> width;
-    Param<bool> function_trace;
-    Param<Tick> function_trace_start;
-    Param<bool> simulate_stalls;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-    INIT_PARAM(max_insts_any_thread,
-               "terminate when any thread reaches this inst count"),
-    INIT_PARAM(max_insts_all_threads,
-               "terminate when all threads have reached this inst count"),
-    INIT_PARAM(max_loads_any_thread,
-               "terminate when any thread reaches this load count"),
-    INIT_PARAM(max_loads_all_threads,
-               "terminate when all threads have reached this load count"),
-    INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu_id, "processor ID"),
-
-#if FULL_SYSTEM
-    INIT_PARAM(itb, "Instruction TLB"),
-    INIT_PARAM(dtb, "Data TLB"),
-    INIT_PARAM(profile, ""),
-    INIT_PARAM(do_quiesce, ""),
-    INIT_PARAM(do_checkpoint_insts, ""),
-    INIT_PARAM(do_statistics_insts, ""),
-#else
-    INIT_PARAM(workload, "processes to run"),
-#endif // FULL_SYSTEM
-
-    INIT_PARAM(clock, "clock speed"),
-    INIT_PARAM_DFLT(phase, "clock phase", 0),
-    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
-    INIT_PARAM(width, "cpu width"),
-    INIT_PARAM(function_trace, "Enable function trace"),
-    INIT_PARAM(function_trace_start, "Cycle to start function trace"),
-    INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
-
-END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
-
-
-CREATE_SIM_OBJECT(TimingSimpleCPU)
+TimingSimpleCPU *
+TimingSimpleCPUParams::create()
 {
     TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
-    params->name = getInstanceName();
+    params->name = name;
     params->numberOfThreads = 1;
     params->max_insts_any_thread = max_insts_any_thread;
     params->max_insts_all_threads = max_insts_all_threads;
@@ -802,12 +734,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->do_checkpoint_insts = do_checkpoint_insts;
     params->do_statistics_insts = do_statistics_insts;
 #else
-    params->process = workload;
+    if (workload.size() != 1)
+        panic("only one workload allowed");
+    params->process = workload[0];
 #endif
 
     TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
     return cpu;
 }
-
-REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
-
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index c20fe3d90..6c6d5f842 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -377,15 +377,17 @@ class SimpleThread : public ThreadState
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
+        assert(i < TheISA::NumArgumentRegs);
         return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i));
+                    TheISA::ArgumentReg[i]));
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
+        assert(i < TheISA::NumArgumentRegs);
         regs.setIntReg(TheISA::flattenIntIndex(getTC(),
-                    TheISA::ArgumentReg0 + i), val);
+                    TheISA::ArgumentReg[i]), val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc
index 0f2944f07..33da3d870 100644
--- a/src/cpu/trace/opt_cpu.cc
+++ b/src/cpu/trace/opt_cpu.cc
@@ -38,8 +38,7 @@
 
 #include "cpu/trace/opt_cpu.hh"
 #include "cpu/trace/reader/mem_trace_reader.hh"
-
-#include "sim/builder.hh"
+#include "params/OptCPU.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
@@ -211,31 +210,8 @@ OptCPU::TickEvent::description()
 }
 
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
-    SimObjectParam<MemTraceReader *> data_trace;
-    Param<int> size;
-    Param<int> block_size;
-Param<int> assoc;
-
-END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-    INIT_PARAM_DFLT(data_trace, "memory trace", NULL),
-    INIT_PARAM(size, "cache size"),
-    INIT_PARAM(block_size, "block size"),
-    INIT_PARAM(assoc,"associativity")
-
-END_INIT_SIM_OBJECT_PARAMS(OptCPU)
-
-CREATE_SIM_OBJECT(OptCPU)
+OptCPU *
+OptCPUParams::create()
 {
-    return new OptCPU(getInstanceName(),
-                      data_trace,
-                      block_size,
-                      size,
-                      assoc);
+    return new OptCPU(name, data_trace, block_size, size, assoc);
 }
-
-REGISTER_SIM_OBJECT("OptCPU", OptCPU)
diff --git a/src/cpu/trace/reader/ibm_reader.cc b/src/cpu/trace/reader/ibm_reader.cc
index 87e13f307..e300385d6 100644
--- a/src/cpu/trace/reader/ibm_reader.cc
+++ b/src/cpu/trace/reader/ibm_reader.cc
@@ -34,9 +34,9 @@
  */
 #include <sstream>
 
-#include "cpu/trace/reader/ibm_reader.hh"
-#include "sim/builder.hh"
 #include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/ibm_reader.hh"
+#include "params/IBMReader.hh"
 
 using namespace std;
 
@@ -100,23 +100,8 @@ IBMReader::getNextReq(MemReqPtr &req)
     return 0;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(IBMReader)
-
-
-CREATE_SIM_OBJECT(IBMReader)
+IBMReader *
+IBMReaderParams::create()
 {
-    return new IBMReader(getInstanceName(), filename);
+    return new IBMReader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("IBMReader", IBMReader)
diff --git a/src/cpu/trace/reader/itx_reader.cc b/src/cpu/trace/reader/itx_reader.cc
index e4738eed8..f27b82ff1 100644
--- a/src/cpu/trace/reader/itx_reader.cc
+++ b/src/cpu/trace/reader/itx_reader.cc
@@ -34,9 +34,9 @@
  */
 #include <sstream>
 
-#include "cpu/trace/reader/itx_reader.hh"
-#include "sim/builder.hh"
 #include "base/misc.hh" // for fatal
+#include "cpu/trace/reader/itx_reader.hh"
+#include "params/ITXReader.hh"
 
 using namespace std;
 
@@ -186,23 +186,8 @@ ITXReader::getNextReq(MemReqPtr &req)
     return 0;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(ITXReader)
-
-
-CREATE_SIM_OBJECT(ITXReader)
+ITXReader *
+ITXReaderParams::create()
 {
-    return new ITXReader(getInstanceName(), filename);
+    return new ITXReader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("ITXReader", ITXReader)
diff --git a/src/cpu/trace/reader/m5_reader.cc b/src/cpu/trace/reader/m5_reader.cc
index 8efcb022b..4e714a058 100644
--- a/src/cpu/trace/reader/m5_reader.cc
+++ b/src/cpu/trace/reader/m5_reader.cc
@@ -36,7 +36,7 @@
 #include "cpu/trace/reader/m5_reader.hh"
 #include "mem/trace/m5_format.hh"
 #include "mem/mem_cmd.hh"
-#include "sim/builder.hh"
+#include "params/M5Reader.hh"
 
 using namespace std;
 
@@ -77,23 +77,8 @@ M5Reader::getNextReq(MemReqPtr &req)
     return ref.cycle;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
-    Param<string> filename;
-
-END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-    INIT_PARAM(filename, "trace file")
-
-END_INIT_SIM_OBJECT_PARAMS(M5Reader)
-
-
-CREATE_SIM_OBJECT(M5Reader)
+M5Reader *
+M5ReaderParams::create()
 {
-    return new M5Reader(getInstanceName(), filename);
+    return new M5Reader(name, filename);
 }
-
-REGISTER_SIM_OBJECT("M5Reader", M5Reader)
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 32ed6c7d7..e5739b2ce 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -40,7 +40,7 @@
 #include "cpu/trace/reader/mem_trace_reader.hh"
 #include "mem/base_mem.hh" // For PARAM constructor
 #include "mem/mem_interface.hh"
-#include "sim/builder.hh"
+#include "params/TraceCPU.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
@@ -151,31 +151,11 @@ TraceCPU::TickEvent::description()
     return "TraceCPU tick";
 }
 
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-    SimObjectParam<BaseMem *> icache;
-    SimObjectParam<BaseMem *> dcache;
-    SimObjectParam<MemTraceReader *> data_trace;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-    INIT_PARAM_DFLT(icache, "instruction cache", NULL),
-    INIT_PARAM_DFLT(dcache, "data cache", NULL),
-    INIT_PARAM_DFLT(data_trace, "data trace", NULL)
-
-END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
-
-CREATE_SIM_OBJECT(TraceCPU)
+TraceCPU *
+TraceCPUParams::create()
 {
-    return new TraceCPU(getInstanceName(),
+    return new TraceCPU(name,
                         (icache) ? icache->getInterface() : NULL,
                         (dcache) ? dcache->getInterface() : NULL,
                         data_trace);
 }
-
-REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
-
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 587087640..c978470ca 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -180,6 +180,8 @@ class SinicPciData(PciConfigData):
 
 class Sinic(EtherDevBase):
     type = 'Sinic'
+    cxx_namespace = 'Sinic'
+    cxx_class = 'Device'
 
     rx_max_copy = Param.MemorySize('1514B', "rx max copy")
     tx_max_copy = Param.MemorySize('16kB', "tx max copy")
@@ -197,4 +199,7 @@ class Sinic(EtherDevBase):
 
 class SinicInt(EtherInt):
     type = 'SinicInt'
+    cxx_namespace = 'Sinic'
+    cxx_class = 'Interface'
+
     device = Param.Sinic("Ethernet device of this interface")
diff --git a/src/dev/SConscript b/src/dev/SConscript
index 2e0d75650..88ebee573 100644
--- a/src/dev/SConscript
+++ b/src/dev/SConscript
@@ -50,7 +50,7 @@ if env['FULL_SYSTEM']:
     Source('etherint.cc')
     Source('etherlink.cc')
     Source('etherpkt.cc')
-    Source('ethertap.cc')	
+    Source('ethertap.cc')
     Source('i8254xGBe.cc')
     Source('ide_ctrl.cc')
     Source('ide_disk.cc')
@@ -63,6 +63,6 @@ if env['FULL_SYSTEM']:
     Source('platform.cc')
     Source('simconsole.cc')
     Source('simple_disk.cc')
-    #Source('sinic.cc')
+    Source('sinic.cc')
     Source('uart.cc')
     Source('uart8250.cc')
diff --git a/src/dev/alpha/console.cc b/src/dev/alpha/console.cc
index 55549a154..84425945b 100644
--- a/src/dev/alpha/console.cc
+++ b/src/dev/alpha/console.cc
@@ -51,15 +51,15 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
-#include "sim/builder.hh"
+#include "params/AlphaConsole.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
 using namespace AlphaISA;
 
-AlphaConsole::AlphaConsole(Params *p)
-    : BasicPioDevice(p), disk(p->disk),
-      console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
+AlphaConsole::AlphaConsole(const Params *p)
+    : BasicPioDevice(p), disk(p->disk), console(p->sim_console),
+      system(p->system), cpu(p->cpu)
 {
 
     pioSize = sizeof(struct AlphaAccess);
@@ -303,43 +303,8 @@ AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
     alphaAccess->unserialize(cp, section);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
-
-    SimObjectParam<SimConsole *> sim_console;
-    SimObjectParam<SimpleDisk *> disk;
-    Param<Addr> pio_addr;
-    SimObjectParam<AlphaSystem *> system;
-    SimObjectParam<BaseCPU *> cpu;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
-    INIT_PARAM(sim_console, "The Simulator Console"),
-    INIT_PARAM(disk, "Simple Disk"),
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(cpu, "Processor"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
-
-CREATE_SIM_OBJECT(AlphaConsole)
+AlphaConsole *
+AlphaConsoleParams::create()
 {
-    AlphaConsole::Params *p = new AlphaConsole::Params;
-    p->name = getInstanceName();
-    p->platform = platform;
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->cons = sim_console;
-    p->disk = disk;
-    p->alpha_sys = system;
-    p->system = system;
-    p->cpu = cpu;
-    return new AlphaConsole(p);
+    return new AlphaConsole(this);
 }
-
-REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
diff --git a/src/dev/alpha/console.hh b/src/dev/alpha/console.hh
index b8d21ad5d..e77a7fad6 100644
--- a/src/dev/alpha/console.hh
+++ b/src/dev/alpha/console.hh
@@ -38,6 +38,7 @@
 #include "base/range.hh"
 #include "dev/alpha/access.h"
 #include "dev/io_device.hh"
+#include "params/AlphaConsole.hh"
 #include "sim/host.hh"
 #include "sim/sim_object.hh"
 
@@ -98,20 +99,14 @@ class AlphaConsole : public BasicPioDevice
     BaseCPU *cpu;
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        SimConsole *cons;
-        SimpleDisk *disk;
-        AlphaSystem *alpha_sys;
-        BaseCPU *cpu;
-    };
-  protected:
-    const Params *params() const {return (const Params *)_params; }
+    typedef AlphaConsoleParams Params;
+    AlphaConsole(const Params *p);
 
-  public:
-
-    /** Standard Constructor */
-    AlphaConsole(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual void startup();
 
diff --git a/src/dev/alpha/tsunami.cc b/src/dev/alpha/tsunami.cc
index 608e88846..bac2a8682 100644
--- a/src/dev/alpha/tsunami.cc
+++ b/src/dev/alpha/tsunami.cc
@@ -42,7 +42,7 @@
 #include "dev/alpha/tsunami_pchip.hh"
 #include "dev/alpha/tsunami_io.hh"
 #include "dev/alpha/tsunami.hh"
-#include "sim/builder.hh"
+#include "params/Tsunami.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -114,23 +114,8 @@ Tsunami::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
-    INIT_PARAM(system, "system"),
-    INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(Tsunami)
-
-CREATE_SIM_OBJECT(Tsunami)
+Tsunami *
+TsunamiParams::create()
 {
-    return new Tsunami(getInstanceName(), system, intrctrl);
+    return new Tsunami(name, system, intrctrl);
 }
-
-REGISTER_SIM_OBJECT("Tsunami", Tsunami)
diff --git a/src/dev/alpha/tsunami_cchip.cc b/src/dev/alpha/tsunami_cchip.cc
index c10ca1eef..891fe17da 100644
--- a/src/dev/alpha/tsunami_cchip.cc
+++ b/src/dev/alpha/tsunami_cchip.cc
@@ -47,14 +47,14 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/TsunamiCChip.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiCChip::TsunamiCChip(Params *p)
+TsunamiCChip::TsunamiCChip(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami)
 {
     pioSize = 0x10000000;
@@ -521,36 +521,8 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(drir);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
-
-CREATE_SIM_OBJECT(TsunamiCChip)
+TsunamiCChip *
+TsunamiCChipParams::create()
 {
-    TsunamiCChip::Params *p = new TsunamiCChip::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->tsunami = tsunami;
-    return new TsunamiCChip(p);
+    return new TsunamiCChip(this);
 }
-
-REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)
diff --git a/src/dev/alpha/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh
index 004c3cd29..1265c2e80 100644
--- a/src/dev/alpha/tsunami_cchip.hh
+++ b/src/dev/alpha/tsunami_cchip.hh
@@ -35,10 +35,10 @@
 #ifndef __TSUNAMI_CCHIP_HH__
 #define __TSUNAMI_CCHIP_HH__
 
-#include "dev/alpha/tsunami.hh"
 #include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
 #include "dev/io_device.hh"
-
+#include "params/TsunamiCChip.hh"
 
 /**
  * Tsunami CChip CSR Emulation. This device includes all the interrupt
@@ -79,20 +79,19 @@ class TsunamiCChip : public BasicPioDevice
     uint64_t itint;
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        Tsunami *tsunami;
-    };
-  protected:
-    const Params *params() const {return (const Params *)_params; }
-
-  public:
+    typedef TsunamiCChipParams Params;
     /**
      * Initialize the Tsunami CChip by setting all of the
      * device register to 0.
      * @param p params struct
      */
-    TsunamiCChip(Params *p);
+    TsunamiCChip(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
 
diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc
index f59a06fba..e1ca1c84c 100644
--- a/src/dev/alpha/tsunami_io.cc
+++ b/src/dev/alpha/tsunami_io.cc
@@ -40,6 +40,7 @@
 #include <string>
 #include <vector>
 
+#include "base/time.hh"
 #include "base/trace.hh"
 #include "dev/pitreg.h"
 #include "dev/rtcreg.h"
@@ -50,27 +51,23 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
-                    bool bcd, Tick i)
-    : _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd)
+TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
+                    const TsunamiIO::Params *p)
+    : _name(n), event(tsunami, p->frequency), addr(0)
 {
     memset(clock_data, 0, sizeof(clock_data));
     stat_regA = RTCA_32768HZ | RTCA_1024HZ;
     stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
 
-    struct tm tm;
-    parseTime(t, &tm);
+    year = p->time.tm_year;
 
-    year = tm.tm_year;
-
-    if (year_is_bcd) {
+    if (p->year_is_bcd) {
         // The datasheet says that the year field can be either BCD or
         // years since 1900.  Linux seems to be happy with years since
         // 1900.
@@ -81,16 +78,16 @@ TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
     }
 
     // Unix is 0-11 for month, data seet says start at 1
-    mon = tm.tm_mon + 1;
-    mday = tm.tm_mday;
-    hour = tm.tm_hour;
-    min = tm.tm_min;
-    sec = tm.tm_sec;
+    mon = p->time.tm_mon + 1;
+    mday = p->time.tm_mday;
+    hour = p->time.tm_hour;
+    min = p->time.tm_min;
+    sec = p->time.tm_sec;
 
     // Datasheet says 1 is sunday
-    wday = tm.tm_wday + 1;
+    wday = p->time.tm_wday + 1;
 
-    DPRINTFN("Real-time clock set to %s", asctime(&tm));
+    DPRINTFN("Real-time clock set to %s", asctime(&p->time));
 }
 
 void
@@ -437,10 +434,9 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
     return "tsunami 8254 Interval timer";
 }
 
-TsunamiIO::TsunamiIO(Params *p)
+TsunamiIO::TsunamiIO(const Params *p)
     : BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
-      rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd,
-          p->frequency)
+      rtc(p->name + ".rtc", p->tsunami, p)
 {
     pioSize = 0x100;
 
@@ -656,45 +652,8 @@ TsunamiIO::unserialize(Checkpoint *cp, const string &section)
     rtc.unserialize("rtc", cp, section);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Tick> frequency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    VectorParam<int> time;
-    Param<bool> year_is_bcd;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(frequency, "clock interrupt frequency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(time, "System time to use (0 for actual time"),
-    INIT_PARAM(year_is_bcd, ""),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
-
-CREATE_SIM_OBJECT(TsunamiIO)
+TsunamiIO *
+TsunamiIOParams::create()
 {
-    TsunamiIO::Params *p = new TsunamiIO::Params;
-    p->frequency = frequency;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->init_time = time;
-    p->year_is_bcd = year_is_bcd;
-    p->tsunami = tsunami;
-    return new TsunamiIO(p);
+    return new TsunamiIO(this);
 }
-
-REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)
diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh
index f4fa62a68..5083604f8 100644
--- a/src/dev/alpha/tsunami_io.hh
+++ b/src/dev/alpha/tsunami_io.hh
@@ -37,9 +37,10 @@
 #ifndef __DEV_TSUNAMI_IO_HH__
 #define __DEV_TSUNAMI_IO_HH__
 
-#include "dev/io_device.hh"
 #include "base/range.hh"
 #include "dev/alpha/tsunami.hh"
+#include "dev/io_device.hh"
+#include "params/TsunamiIO.hh"
 #include "sim/eventq.hh"
 
 /**
@@ -85,9 +86,6 @@ class TsunamiIO : public BasicPioDevice
         /** Current RTC register address/index */
         int addr;
 
-        /** should the year be interpreted as BCD? */
-        bool year_is_bcd;
-
         /** Data for real-time clock function */
         union {
             uint8_t clock_data[10];
@@ -114,7 +112,7 @@ class TsunamiIO : public BasicPioDevice
 
       public:
         RTC(const std::string &name, Tsunami* tsunami,
-            const std::vector<int> &t, bool bcd, Tick i);
+            const TsunamiIOParams *params);
 
         /** RTC address port: write address of RTC RAM data to access */
         void writeAddr(const uint8_t data);
@@ -313,23 +311,19 @@ class TsunamiIO : public BasicPioDevice
      */
     Tick frequency() const;
 
-    struct Params : public BasicPioDevice::Params
-    {
-        Tick frequency;
-        Tsunami *tsunami;
-        std::vector<int> init_time;
-        bool year_is_bcd;
-    };
-
-  protected:
-    const Params *params() const { return (const Params*)_params; }
-
   public:
+    typedef TsunamiIOParams Params;
     /**
      * Initialize all the data for devices supported by Tsunami I/O.
      * @param p pointer to Params struct
      */
-    TsunamiIO(Params *p);
+    TsunamiIO(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
diff --git a/src/dev/alpha/tsunami_pchip.cc b/src/dev/alpha/tsunami_pchip.cc
index be164e5b9..83bcf8e65 100644
--- a/src/dev/alpha/tsunami_pchip.cc
+++ b/src/dev/alpha/tsunami_pchip.cc
@@ -43,14 +43,13 @@
 #include "dev/alpha/tsunami.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 //Should this be AlphaISA?
 using namespace TheISA;
 
-TsunamiPChip::TsunamiPChip(Params *p)
+TsunamiPChip::TsunamiPChip(const Params *p)
 : BasicPioDevice(p)
 {
     pioSize = 0x1000;
@@ -332,36 +331,8 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
 }
 
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<Tsunami *> tsunami;
-
-END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(tsunami, "Tsunami")
-
-END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
-
-CREATE_SIM_OBJECT(TsunamiPChip)
+TsunamiPChip *
+TsunamiPChipParams::create()
 {
-    TsunamiPChip::Params *p = new TsunamiPChip::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->tsunami = tsunami;
-    return new TsunamiPChip(p);
+    return new TsunamiPChip(this);
 }
-
-REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh
index 1632a36d4..53050565f 100644
--- a/src/dev/alpha/tsunami_pchip.hh
+++ b/src/dev/alpha/tsunami_pchip.hh
@@ -35,9 +35,10 @@
 #ifndef __TSUNAMI_PCHIP_HH__
 #define __TSUNAMI_PCHIP_HH__
 
-#include "dev/alpha/tsunami.hh"
 #include "base/range.hh"
+#include "dev/alpha/tsunami.hh"
 #include "dev/io_device.hh"
+#include "params/TsunamiPChip.hh"
 
 /**
  * A very simple implementation of the Tsunami PCI interface chips.
@@ -61,19 +62,18 @@ class TsunamiPChip : public BasicPioDevice
     uint64_t tba[4];
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        Tsunami *tsunami;
-    };
-  protected:
-    const Params *params() const { return (const Params*)_params; }
-
-  public:
+    typedef TsunamiPChipParams Params;
     /**
      * Register the PChip with the mmu and init all wsba, wsm, and tba to 0
      * @param p pointer to the parameters struct
      */
-    TsunamiPChip(Params *p);
+    TsunamiPChip(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /**
      * Translate a PCI bus address to a memory address for DMA.
diff --git a/src/dev/baddev.cc b/src/dev/baddev.cc
index a2d2650cb..6cdee0310 100644
--- a/src/dev/baddev.cc
+++ b/src/dev/baddev.cc
@@ -40,14 +40,14 @@
 #include "dev/baddev.hh"
 #include "dev/platform.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/BadDevice.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
 
 BadDevice::BadDevice(Params *p)
-    : BasicPioDevice(p), devname(p->device_name)
+    : BasicPioDevice(p), devname(p->devicename)
 {
     pioSize = 0x10;
 }
@@ -66,36 +66,8 @@ BadDevice::write(PacketPtr pkt)
     M5_DUMMY_RETURN
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
-
-    Param<string> devicename;
-    Param<Addr> pio_addr;
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> pio_latency;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
-    INIT_PARAM(devicename, "Name of device to error on"),
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
-
-END_INIT_SIM_OBJECT_PARAMS(BadDevice)
-
-CREATE_SIM_OBJECT(BadDevice)
+BadDevice *
+BadDeviceParams::create()
 {
-    BadDevice::Params *p = new BadDevice::Params;
-    p->name =getInstanceName();
-    p->platform = platform;
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->system = system;
-    p->device_name = devicename;
-    return new BadDevice(p);
+    return new BadDevice(this);
 }
-
-REGISTER_SIM_OBJECT("BadDevice", BadDevice)
diff --git a/src/dev/baddev.hh b/src/dev/baddev.hh
index 040fff8e5..9cf592c0e 100644
--- a/src/dev/baddev.hh
+++ b/src/dev/baddev.hh
@@ -38,7 +38,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
-
+#include "params/BadDevice.hh"
 
 /**
  * BadDevice
@@ -52,12 +52,14 @@ class BadDevice : public BasicPioDevice
     std::string devname;
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        std::string device_name;
-    };
+    typedef BadDeviceParams Params;
+
   protected:
-    const Params *params() const { return (const Params *)_params; }
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
   public:
      /**
diff --git a/src/dev/disk_image.cc b/src/dev/disk_image.cc
index f70d2ccdb..1cccf3a0f 100644
--- a/src/dev/disk_image.cc
+++ b/src/dev/disk_image.cc
@@ -45,7 +45,8 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "sim/builder.hh"
+#include "params/CowDiskImage.hh"
+#include "params/RawDiskImage.hh"
 #include "sim/sim_exit.hh"
 #include "sim/byteswap.hh"
 
@@ -143,30 +144,12 @@ RawDiskImage::write(const uint8_t *data, off_t offset)
     return stream.tellp() - pos;
 }
 
-DEFINE_SIM_OBJECT_CLASS_NAME("DiskImage", DiskImage)
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
-    Param<string> image_file;
-    Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
-    INIT_PARAM(image_file, "disk image file"),
-    INIT_PARAM_DFLT(read_only, "read only image", false)
-
-END_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
-
-
-CREATE_SIM_OBJECT(RawDiskImage)
+RawDiskImage *
+RawDiskImageParams::create()
 {
-    return new RawDiskImage(getInstanceName(), image_file, read_only);
+    return new RawDiskImage(name, image_file, read_only);
 }
 
-REGISTER_SIM_OBJECT("RawDiskImage", RawDiskImage)
-
 ////////////////////////////////////////////////////////////////////////
 //
 // Copy on Write Disk image
@@ -440,33 +423,12 @@ CowDiskImage::unserialize(Checkpoint *cp, const string &section)
     open(cowFilename);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
-
-    SimObjectParam<DiskImage *> child;
-    Param<string> image_file;
-    Param<int> table_size;
-    Param<bool> read_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
-    INIT_PARAM(child, "child image"),
-    INIT_PARAM_DFLT(image_file, "disk image file", ""),
-    INIT_PARAM_DFLT(table_size, "initial table size", 65536),
-    INIT_PARAM_DFLT(read_only, "don't write back to the copy-on-write file",
-                    true)
-
-END_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
-
-
-CREATE_SIM_OBJECT(CowDiskImage)
+CowDiskImage *
+CowDiskImageParams::create()
 {
     if (((string)image_file).empty())
-        return new CowDiskImage(getInstanceName(), child, table_size);
+        return new CowDiskImage(name, child, table_size);
     else
-        return new CowDiskImage(getInstanceName(), child, table_size,
+        return new CowDiskImage(name, child, table_size,
                                 image_file, read_only);
 }
-
-REGISTER_SIM_OBJECT("CowDiskImage", CowDiskImage)
diff --git a/src/dev/etherbus.cc b/src/dev/etherbus.cc
index cedb3cd4d..3e59229ad 100644
--- a/src/dev/etherbus.cc
+++ b/src/dev/etherbus.cc
@@ -42,7 +42,7 @@
 #include "dev/etherdump.hh"
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherBus.hh"
 #include "sim/core.hh"
 
 using namespace std;
@@ -103,25 +103,8 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
     return true;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
-
-    Param<bool> loopback;
-    Param<double> speed;
-    SimObjectParam<EtherDump *> packet_dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
-    INIT_PARAM(loopback, "send the packet back to the sending interface"),
-    INIT_PARAM(speed, "bus speed in ticks per byte"),
-    INIT_PARAM(packet_dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherBus)
-
-CREATE_SIM_OBJECT(EtherBus)
+EtherBus *
+EtherBusParams::create()
 {
-    return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
+    return new EtherBus(name, speed, loopback, dump);
 }
-
-REGISTER_SIM_OBJECT("EtherBus", EtherBus)
diff --git a/src/dev/etherdump.cc b/src/dev/etherdump.cc
index 04463f3ee..7dcf1ca97 100644
--- a/src/dev/etherdump.cc
+++ b/src/dev/etherdump.cc
@@ -40,7 +40,7 @@
 #include "base/misc.hh"
 #include "base/output.hh"
 #include "dev/etherdump.hh"
-#include "sim/builder.hh"
+#include "params/EtherDump.hh"
 #include "sim/core.hh"
 
 using std::string;
@@ -116,23 +116,8 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
     stream.flush();
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
-
-    Param<string> file;
-    Param<int> maxlen;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
-    INIT_PARAM(file, "file to dump packets to"),
-    INIT_PARAM(maxlen, "max portion of packet data to dump")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherDump)
-
-CREATE_SIM_OBJECT(EtherDump)
+EtherDump *
+EtherDumpParams::create()
 {
-    return new EtherDump(getInstanceName(), simout.resolve(file), maxlen);
+    return new EtherDump(name, simout.resolve(file), maxlen);
 }
-
-REGISTER_SIM_OBJECT("EtherDump", EtherDump)
diff --git a/src/dev/etherint.cc b/src/dev/etherint.cc
index 3f81591e9..e9f830702 100644
--- a/src/dev/etherint.cc
+++ b/src/dev/etherint.cc
@@ -30,7 +30,6 @@
 
 #include "dev/etherint.hh"
 #include "base/misc.hh"
-#include "sim/param.hh"
 #include "sim/sim_object.hh"
 
 void
@@ -42,6 +41,3 @@ EtherInt::setPeer(EtherInt *p)
 
     peer = p;
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("EtherInt", EtherInt)
-
diff --git a/src/dev/etherlink.cc b/src/dev/etherlink.cc
index 5d30e1744..8c54da678 100644
--- a/src/dev/etherlink.cc
+++ b/src/dev/etherlink.cc
@@ -44,7 +44,7 @@
 #include "dev/etherint.hh"
 #include "dev/etherlink.hh"
 #include "dev/etherpkt.hh"
-#include "sim/builder.hh"
+#include "params/EtherLink.hh"
 #include "sim/serialize.hh"
 #include "sim/system.hh"
 #include "sim/core.hh"
@@ -272,32 +272,8 @@ LinkDelayEvent::createForUnserialize(Checkpoint *cp, const string &section)
 
 REGISTER_SERIALIZEABLE("LinkDelayEvent", LinkDelayEvent)
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
-
-    SimObjectParam<EtherInt *> int1;
-    SimObjectParam<EtherInt *> int2;
-    Param<double> speed;
-    Param<Tick> delay;
-    Param<Tick> delay_var;
-    SimObjectParam<EtherDump *> dump;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
-    INIT_PARAM(int1, "interface 1"),
-    INIT_PARAM(int2, "interface 2"),
-    INIT_PARAM(speed, "link speed in bits per second"),
-    INIT_PARAM(delay, "transmit delay of packets in us"),
-    INIT_PARAM(delay_var, "Difference in amount of time to traverse wire"),
-    INIT_PARAM(dump, "object to dump network packets to")
-
-END_INIT_SIM_OBJECT_PARAMS(EtherLink)
-
-CREATE_SIM_OBJECT(EtherLink)
+EtherLink *
+EtherLinkParams::create()
 {
-    return new EtherLink(getInstanceName(), int1, int2, speed, delay, delay_var,
-                         dump);
+    return new EtherLink(name, int1, int2, speed, delay, delay_var, dump);
 }
-
-REGISTER_SIM_OBJECT("EtherLink", EtherLink)
diff --git a/src/dev/ethertap.cc b/src/dev/ethertap.cc
index 65089a8b2..0b6ab97fc 100644
--- a/src/dev/ethertap.cc
+++ b/src/dev/ethertap.cc
@@ -50,7 +50,7 @@
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
 #include "dev/ethertap.hh"
-#include "sim/builder.hh"
+#include "params/EtherTap.hh"
 
 using namespace std;
 
@@ -313,28 +313,10 @@ EtherTap::unserialize(Checkpoint *cp, const std::string &section)
 
 //=====================================================================
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
-
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<EtherDump *> dump;
-    Param<unsigned> port;
-    Param<unsigned> bufsz;
-
-END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL),
-    INIT_PARAM_DFLT(port, "tap port", 3500),
-    INIT_PARAM_DFLT(bufsz, "tap buffer size", 10000)
-
-END_INIT_SIM_OBJECT_PARAMS(EtherTap)
-
-
-CREATE_SIM_OBJECT(EtherTap)
+EtherTap *
+EtherTapParams::create()
 {
-    EtherTap *tap = new EtherTap(getInstanceName(), dump, port, bufsz);
+    EtherTap *tap = new EtherTap(name, dump, port, bufsz);
 
     if (peer) {
         tap->setPeer(peer);
@@ -343,5 +325,3 @@ CREATE_SIM_OBJECT(EtherTap)
 
     return tap;
 }
-
-REGISTER_SIM_OBJECT("EtherTap", EtherTap)
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 7ea4c704b..d75e37a8a 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -40,17 +40,18 @@
  * @todo really there are multiple dma engines.. we should implement them.
  */
 
+#include <algorithm>
+
 #include "base/inet.hh"
 #include "base/trace.hh"
 #include "dev/i8254xGBe.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IGbE.hh"
+#include "params/IGbEInt.hh"
 #include "sim/stats.hh"
 #include "sim/system.hh"
 
-#include <algorithm>
-
 using namespace iGbReg;
 using namespace Net;
 
@@ -1446,24 +1447,10 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
     rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<IGbE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
-
-CREATE_SIM_OBJECT(IGbEInt)
+IGbEInt *
+IGbEIntParams::create()
 {
-    IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
+    IGbEInt *dev_int = new IGbEInt(name, device);
 
     EtherInt *p = (EtherInt *)peer;
     if (p) {
@@ -1474,80 +1461,8 @@ CREATE_SIM_OBJECT(IGbEInt)
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    Param<std::string> hardware_address;
-    Param<bool> use_flow_control;
-    Param<int> rx_fifo_size;
-    Param<int> tx_fifo_size;
-    Param<int> rx_desc_cache_size;
-    Param<int> tx_desc_cache_size;
-    Param<Tick> clock;
-
-
-END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
-    INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
-    INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
-    INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
-    INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
-    INIT_PARAM(clock,"Clock rate for the device to tick at")
-
-END_INIT_SIM_OBJECT_PARAMS(IGbE)
-
-
-CREATE_SIM_OBJECT(IGbE)
+IGbE *
+IGbEParams::create()
 {
-    IGbE::Params *params = new IGbE::Params;
-
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->hardware_address = hardware_address;
-    params->use_flow_control = use_flow_control;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-    params->rx_desc_cache_size = rx_desc_cache_size;
-    params->tx_desc_cache_size = tx_desc_cache_size;
-    params->clock = clock;
-
-
-    return new IGbE(params);
+    return new IGbE(this);
 }
-
-REGISTER_SIM_OBJECT("IGbE", IGbE)
diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh
index b6da53b09..caffb8c4d 100644
--- a/src/dev/i8254xGBe.hh
+++ b/src/dev/i8254xGBe.hh
@@ -45,6 +45,7 @@
 #include "dev/i8254xGBe_defs.hh"
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
+#include "params/IGbE.hh"
 #include "sim/eventq.hh"
 
 class IGbEInt;
@@ -585,19 +586,14 @@ class IGbE : public PciDev
     TxDescCache txDescCache;
 
   public:
-    struct Params : public PciDev::Params
+    typedef IGbEParams Params;
+    const Params *
+    params() const
     {
-        Net::EthAddr hardware_address;
-        bool use_flow_control;
-        int rx_fifo_size;
-        int tx_fifo_size;
-        int rx_desc_cache_size;
-        int tx_desc_cache_size;
-        Tick clock;
-    };
-
+        return dynamic_cast<const Params *>(_params);
+    }
     IGbE(Params *params);
-    ~IGbE() {;}
+    ~IGbE() {}
 
     Tick clock;
     inline Tick cycles(int numCycles) const { return numCycles * clock; }
@@ -612,9 +608,6 @@ class IGbE : public PciDev
 
     void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
 
-
-    const Params *params() const {return (const Params *)_params; }
-
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
     virtual unsigned int drain(Event *de);
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index 07764aaba..6d7f1baf1 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -44,7 +44,7 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/IdeController.hh"
 #include "sim/sim_object.hh"
 #include "sim/byteswap.hh"
 
@@ -746,58 +746,8 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
                       sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    SimObjectVectorParam<IdeDisk *> disks;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(disks, "IDE disks attached to this controller")
-
-END_INIT_SIM_OBJECT_PARAMS(IdeController)
-
-CREATE_SIM_OBJECT(IdeController)
+IdeController *
+IdeControllerParams::create()
 {
-    IdeController::Params *params = new IdeController::Params;
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->disks = disks;
-    return new IdeController(params);
+    return new IdeController(this);
 }
-
-REGISTER_SIM_OBJECT("IdeController", IdeController)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/dev/ide_ctrl.hh b/src/dev/ide_ctrl.hh
index 291446d1c..f22d83e9c 100644
--- a/src/dev/ide_ctrl.hh
+++ b/src/dev/ide_ctrl.hh
@@ -40,6 +40,7 @@
 #include "dev/pcidev.hh"
 #include "dev/pcireg.h"
 #include "dev/io_device.hh"
+#include "params/IdeController.hh"
 
 #define BMIC0    0x0  // Bus master IDE command register
 #define BMIS0    0x2  // Bus master IDE status register
@@ -193,14 +194,8 @@ class IdeController : public PciDev
     bool isDiskSelected(IdeDisk *diskPtr);
 
   public:
-    struct Params : public PciDev::Params
-    {
-        /** Array of disk objects */
-        std::vector<IdeDisk *> disks;
-    };
+    typedef IdeControllerParams Params;
     const Params *params() const { return (const Params *)_params; }
-
-  public:
     IdeController(Params *p);
     ~IdeController();
 
diff --git a/src/dev/ide_disk.cc b/src/dev/ide_disk.cc
index 9fa0cedde..cfd743a13 100644
--- a/src/dev/ide_disk.cc
+++ b/src/dev/ide_disk.cc
@@ -38,18 +38,16 @@
 #include <deque>
 #include <string>
 
+#include "arch/isa_traits.hh"
 #include "base/chunk_generator.hh"
 #include "base/cprintf.hh" // csprintf
 #include "base/trace.hh"
 #include "dev/disk_image.hh"
-#include "dev/ide_disk.hh"
 #include "dev/ide_ctrl.hh"
-#include "dev/alpha/tsunami.hh"
-#include "dev/alpha/tsunami_pchip.hh"
-#include "sim/builder.hh"
-#include "sim/sim_object.hh"
+#include "dev/ide_disk.hh"
+#include "params/IdeDisk.hh"
 #include "sim/core.hh"
-#include "arch/isa_traits.hh"
+#include "sim/sim_object.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -1116,32 +1114,8 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
     UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-enum DriveID { master, slave };
-static const char *DriveID_strings[] = { "master", "slave" };
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-    SimObjectParam<DiskImage *> image;
-    SimpleEnumParam<DriveID> driveID;
-    Param<int> delay;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-    INIT_PARAM(image, "Disk image"),
-    INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
-    INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
-
-END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
-
-
-CREATE_SIM_OBJECT(IdeDisk)
+IdeDisk *
+IdeDiskParams::create()
 {
-    return new IdeDisk(getInstanceName(), image, driveID, delay);
+    return new IdeDisk(name, image, driveID, delay);
 }
-
-REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc
index 85d78ee8d..527397ed8 100644
--- a/src/dev/io_device.cc
+++ b/src/dev/io_device.cc
@@ -32,7 +32,6 @@
 #include "base/chunk_generator.hh"
 #include "base/trace.hh"
 #include "dev/io_device.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 
@@ -55,6 +54,10 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
 }
 
 
+PioDevice::PioDevice(const Params *p)
+    : MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
+{}
+
 PioDevice::~PioDevice()
 {
     if (pioPort)
@@ -82,6 +85,11 @@ PioDevice::drain(Event *de)
     return count;
 }
 
+BasicPioDevice::BasicPioDevice(const Params *p)
+    : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
+      pioDelay(p->pio_latency)
+{}
+
 void
 BasicPioDevice::addressRanges(AddrRangeList &range_list)
 {
@@ -147,7 +155,7 @@ DmaPort::recvTiming(PacketPtr pkt)
     return true;
 }
 
-DmaDevice::DmaDevice(Params *p)
+DmaDevice::DmaDevice(const Params *p)
     : PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay),
       maxBackoffDelay(p->max_backoff_delay)
 { }
@@ -260,8 +268,8 @@ DmaPort::sendDma()
     assert(transmitList.size());
     PacketPtr pkt = transmitList.front();
 
-    System::MemoryMode state = sys->getMemoryMode();
-    if (state == System::Timing) {
+    Enums::MemoryMode state = sys->getMemoryMode();
+    if (state == Enums::timing) {
         if (backoffEvent.scheduled() || inRetry) {
             DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n");
             return;
@@ -288,7 +296,7 @@ DmaPort::sendDma()
                     backoffTime+curTick);
             backoffEvent.schedule(backoffTime+curTick);
         }
-    } else if (state == System::Atomic) {
+    } else if (state == Enums::atomic) {
         transmitList.pop_front();
 
         Tick lat;
@@ -328,5 +336,3 @@ DmaDevice::~DmaDevice()
     if (dmaPort)
         delete dmaPort;
 }
-
-
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index 25bd2de8d..e65400ca2 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -35,6 +35,9 @@
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
+#include "params/BasicPioDevice.hh"
+#include "params/DmaDevice.hh"
+#include "params/PioDevice.hh"
 #include "sim/sim_object.hh"
 
 class Event;
@@ -186,29 +189,16 @@ class PioDevice : public MemObject
     virtual Tick write(PacketPtr pkt) = 0;
 
   public:
-    /** Params struct which is extended through each device based on
-     * the parameters it needs. Since we are re-writing everything, we
-     * might as well start from the bottom this time. */
-    struct Params
-    {
-        std::string name;
-        Platform *platform;
-        System *system;
-    };
-
-  protected:
-    Params *_params;
-
-  public:
-    const Params *params() const { return _params; }
-
-    PioDevice(Params *p)
-              : MemObject(p->name),  platform(p->platform), sys(p->system),
-              pioPort(NULL), _params(p)
-              {}
-
+    typedef PioDeviceParams Params;
+    PioDevice(const Params *p);
     virtual ~PioDevice();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
     virtual void init();
 
     virtual unsigned int drain(Event *de);
@@ -229,13 +219,6 @@ class PioDevice : public MemObject
 
 class BasicPioDevice : public PioDevice
 {
-  public:
-    struct Params :  public PioDevice::Params
-    {
-        Addr pio_addr;
-        Tick pio_delay;
-    };
-
   protected:
     /** Address that the device listens to. */
     Addr pioAddr;
@@ -247,10 +230,14 @@ class BasicPioDevice : public PioDevice
     Tick pioDelay;
 
   public:
-    BasicPioDevice(Params *p)
-        : PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
-          pioDelay(p->pio_delay)
-    {}
+    typedef BasicPioDeviceParams Params;
+    BasicPioDevice(const Params *p);
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /** return the address ranges that this device responds to.
      * @param range_list range list to populate with ranges
@@ -261,22 +248,22 @@ class BasicPioDevice : public PioDevice
 
 class DmaDevice : public PioDevice
 {
-  public:
-    struct Params :  public PioDevice::Params
-    {
-        Tick min_backoff_delay;
-        Tick max_backoff_delay;
-    };
-
    protected:
     DmaPort *dmaPort;
     Tick minBackoffDelay;
     Tick maxBackoffDelay;
 
   public:
-    DmaDevice(Params *p);
+    typedef DmaDeviceParams Params;
+    DmaDevice(const Params *p);
     virtual ~DmaDevice();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
     void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
     {
         dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 5cd0afb36..9d62aecba 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -36,7 +36,6 @@
 #include "dev/isa_fake.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -44,23 +43,23 @@ using namespace std;
 IsaFake::IsaFake(Params *p)
     : BasicPioDevice(p)
 {
-    if (!params()->retBadAddr)
+    if (!p->ret_bad_addr)
         pioSize = p->pio_size;
 
-    retData8 = params()->retData8;
-    retData16 = params()->retData16;
-    retData32 = params()->retData32;
-    retData64 = params()->retData64;
+    retData8 = p->ret_data8;
+    retData16 = p->ret_data16;
+    retData32 = p->ret_data32;
+    retData64 = p->ret_data64;
 }
 
 Tick
 IsaFake::read(PacketPtr pkt)
 {
 
-    if (params()->warnAccess != "")
+    if (params()->warn_access != "")
         warn("Device %s accessed by read to address %#x size=%d\n",
                 name(), pkt->getAddr(), pkt->getSize());
-    if (params()->retBadAddr) {
+    if (params()->ret_bad_addr) {
         DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n",
                 pkt->getAddr(), pkt->getSize());
         pkt->setBadAddress();
@@ -92,7 +91,7 @@ IsaFake::read(PacketPtr pkt)
 Tick
 IsaFake::write(PacketPtr pkt)
 {
-    if (params()->warnAccess != "") {
+    if (params()->warn_access != "") {
         uint64_t data;
         switch (pkt->getSize()) {
           case sizeof(uint64_t):
@@ -113,7 +112,7 @@ IsaFake::write(PacketPtr pkt)
         warn("Device %s accessed by write to address %#x size=%d data=%#x\n",
                 name(), pkt->getAddr(), pkt->getSize(), data);
     }
-    if (params()->retBadAddr) {
+    if (params()->ret_bad_addr) {
         DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
         pkt->setBadAddress();
@@ -121,7 +120,7 @@ IsaFake::write(PacketPtr pkt)
         DPRINTF(Tsunami, "write - va=%#x size=%d \n",
                 pkt->getAddr(), pkt->getSize());
 
-        if (params()->updateData) {
+        if (params()->update_data) {
             switch (pkt->getSize()) {
               case sizeof(uint64_t):
                 retData64 = pkt->get<uint64_t>();
@@ -144,57 +143,8 @@ IsaFake::write(PacketPtr pkt)
     return pioDelay;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Addr> pio_size;
-    Param<bool> ret_bad_addr;
-    Param<bool> update_data;
-    Param<std::string> warn_access;
-    Param<uint8_t> ret_data8;
-    Param<uint16_t> ret_data16;
-    Param<uint32_t> ret_data32;
-    Param<uint64_t> ret_data64;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(IsaFake)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(pio_size, "Size of address range"),
-    INIT_PARAM(ret_bad_addr, "Return pkt status BadAddr"),
-    INIT_PARAM(update_data, "Update returned data"),
-    INIT_PARAM(warn_access, "Warn if this device is touched"),
-    INIT_PARAM(ret_data8, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data16, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data32, "Data to return if not bad addr"),
-    INIT_PARAM(ret_data64, "Data to return if not bad addr"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(IsaFake)
-
-CREATE_SIM_OBJECT(IsaFake)
+IsaFake *
+IsaFakeParams::create()
 {
-    IsaFake::Params *p = new IsaFake::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->pio_size = pio_size;
-    p->retBadAddr = ret_bad_addr;
-    p->updateData = update_data;
-    p->warnAccess = warn_access;
-    p->retData8= ret_data8;
-    p->retData16 = ret_data16;
-    p->retData32 = ret_data32;
-    p->retData64 = ret_data64;
-    p->platform = platform;
-    p->system = system;
-    return new IsaFake(p);
+    return new IsaFake(this);
 }
-
-REGISTER_SIM_OBJECT("IsaFake", IsaFake)
diff --git a/src/dev/isa_fake.hh b/src/dev/isa_fake.hh
index dc2ad48e8..5f54b1af3 100644
--- a/src/dev/isa_fake.hh
+++ b/src/dev/isa_fake.hh
@@ -35,13 +35,14 @@
 #ifndef __ISA_FAKE_HH__
 #define __ISA_FAKE_HH__
 
+#include <string>
+
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/alpha/tsunami.hh"
+#include "params/IsaFake.hh"
 #include "mem/packet.hh"
 
-#include <string>
-
 /**
  * IsaFake is a device that returns, BadAddr, 1 or 0 on all reads and
  *  rites. It is meant to be placed at an address range
@@ -51,27 +52,19 @@
  */
 class IsaFake : public BasicPioDevice
 {
-  public:
-    struct Params : public BasicPioDevice::Params
-    {
-        Addr pio_size;
-        bool retBadAddr;
-        bool updateData;
-        uint8_t retData8;
-        uint16_t retData16;
-        uint32_t retData32;
-        uint64_t retData64;
-        std::string warnAccess;
-    };
   protected:
-    const Params *params() const { return (const Params*)_params; }
     uint8_t retData8;
     uint16_t retData16;
     uint32_t retData32;
     uint64_t retData64;
 
-
   public:
+    typedef IsaFakeParams Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
     /**
       * The constructor for Tsunmami Fake just registers itself with the MMU.
       * @param p params structure
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index 17f7b433b..28e1100ae 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -43,7 +43,8 @@
 #include "dev/pciconfigall.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/NSGigE.hh"
+#include "params/NSGigEInt.hh"
 #include "sim/debug.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
@@ -118,7 +119,7 @@ NSGigE::NSGigE(Params *p)
 
 
     regsReset();
-    memcpy(&rom.perfectMatch, p->eaddr.bytes(), ETH_ADDR_LEN);
+    memcpy(&rom.perfectMatch, p->hardware_address.bytes(), ETH_ADDR_LEN);
 
     memset(&rxDesc32, 0, sizeof(rxDesc32));
     memset(&txDesc32, 0, sizeof(txDesc32));
@@ -2773,23 +2774,10 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
     }
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
-
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<NSGigE *> device;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
-
-CREATE_SIM_OBJECT(NSGigEInt)
+NSGigEInt *
+NSGigEIntParams::create()
 {
-    NSGigEInt *dev_int = new NSGigEInt(getInstanceName(), device);
+    NSGigEInt *dev_int = new NSGigEInt(name, device);
 
     EtherInt *p = (EtherInt *)peer;
     if (p) {
@@ -2800,121 +2788,8 @@ CREATE_SIM_OBJECT(NSGigEInt)
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-
-    Param<Tick> clock;
-    Param<bool> dma_desc_free;
-    Param<bool> dma_data_free;
-    Param<Tick> dma_read_delay;
-    Param<Tick> dma_write_delay;
-    Param<Tick> dma_read_factor;
-    Param<Tick> dma_write_factor;
-    Param<bool> dma_no_allocate;
-    Param<Tick> intr_delay;
-
-    Param<Tick> rx_delay;
-    Param<Tick> tx_delay;
-    Param<uint32_t> rx_fifo_size;
-    Param<uint32_t> tx_fifo_size;
-
-    Param<bool> rx_filter;
-    Param<string> hardware_address;
-    Param<bool> rx_thread;
-    Param<bool> tx_thread;
-    Param<bool> rss;
-
-END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(clock, "State machine cycle time"),
-
-    INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
-    INIT_PARAM(dma_data_free, "DMA of Data is free"),
-    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
-    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
-    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
-    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-    INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
-    INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
-
-    INIT_PARAM(rx_delay, "Receive Delay"),
-    INIT_PARAM(tx_delay, "Transmit Delay"),
-    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
-
-    INIT_PARAM(rx_filter, "Enable Receive Filter"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(rx_thread, ""),
-    INIT_PARAM(tx_thread, ""),
-    INIT_PARAM(rss, "")
-
-END_INIT_SIM_OBJECT_PARAMS(NSGigE)
-
-
-CREATE_SIM_OBJECT(NSGigE)
+NSGigE *
+NSGigEParams::create()
 {
-    NSGigE::Params *params = new NSGigE::Params;
-
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-
-    params->clock = clock;
-    params->dma_desc_free = dma_desc_free;
-    params->dma_data_free = dma_data_free;
-    params->dma_read_delay = dma_read_delay;
-    params->dma_write_delay = dma_write_delay;
-    params->dma_read_factor = dma_read_factor;
-    params->dma_write_factor = dma_write_factor;
-    params->dma_no_allocate = dma_no_allocate;
-    params->pio_delay = pio_latency;
-    params->intr_delay = intr_delay;
-
-    params->rx_delay = rx_delay;
-    params->tx_delay = tx_delay;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-
-    params->rx_filter = rx_filter;
-    params->eaddr = hardware_address;
-    params->rx_thread = rx_thread;
-    params->tx_thread = tx_thread;
-    params->rss = rss;
-
-    return new NSGigE(params);
+    return new NSGigE(this);
 }
-
-REGISTER_SIM_OBJECT("NSGigE", NSGigE)
diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index a40fe3b29..de18571d6 100644
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -45,6 +45,7 @@
 #include "dev/ns_gige_reg.h"
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
+#include "params/NSGigE.hh"
 #include "sim/eventq.hh"
 
 // Hash filtering constants
@@ -349,31 +350,10 @@ class NSGigE : public PciDev
     NSGigEInt *interface;
 
   public:
-    struct Params : public PciDev::Params
-    {
-        Tick clock;
-        Tick intr_delay;
-        Tick tx_delay;
-        Tick rx_delay;
-        bool dma_desc_free;
-        bool dma_data_free;
-        Tick dma_read_delay;
-        Tick dma_write_delay;
-        Tick dma_read_factor;
-        Tick dma_write_factor;
-        bool rx_filter;
-        Net::EthAddr eaddr;
-        uint32_t tx_fifo_size;
-        uint32_t rx_fifo_size;
-        bool rx_thread;
-        bool tx_thread;
-        bool rss;
-        bool dma_no_allocate;
-    };
-
+    typedef NSGigEParams Params;
+    const Params *params() const { return (const Params *)_params; }
     NSGigE(Params *params);
     ~NSGigE();
-    const Params *params() const { return (const Params *)_params; }
 
     virtual Tick writeConfig(PacketPtr pkt);
 
diff --git a/src/dev/pciconfigall.cc b/src/dev/pciconfigall.cc
index b07ee1a49..884fab7ac 100644
--- a/src/dev/pciconfigall.cc
+++ b/src/dev/pciconfigall.cc
@@ -39,7 +39,7 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigAll.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -95,27 +95,8 @@ PciConfigAll::addressRanges(AddrRangeList &range_list)
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
-
-    Param<Tick> pio_latency;
-    Param<int> bus;
-    Param<Addr> size;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(bus, "Bus that this object handles config space for"),
-    INIT_PARAM(size, "The size of config space"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
-
-CREATE_SIM_OBJECT(PciConfigAll)
+PciConfigAll *
+PciConfigAllParams::create()
 {
     PciConfigAll::Params *p = new PciConfigAll::Params;
     p->pio_delay = pio_latency;
@@ -127,6 +108,4 @@ CREATE_SIM_OBJECT(PciConfigAll)
     return new PciConfigAll(p);
 }
 
-REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)
-
 #endif // DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc
index 06806f841..9efee2835 100644
--- a/src/dev/pcidev.cc
+++ b/src/dev/pcidev.cc
@@ -48,9 +48,8 @@
 #include "dev/alpha/tsunamireg.h"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
+#include "params/PciConfigData.hh"
 #include "sim/byteswap.hh"
-#include "sim/param.hh"
 #include "sim/core.hh"
 
 using namespace std;
@@ -83,8 +82,8 @@ PciDev::PciConfigPort::getDeviceAddressRanges(AddrRangeList &resp,
 
 
 PciDev::PciDev(Params *p)
-    : DmaDevice(p), plat(p->platform), configData(p->configData),
-      pioDelay(p->pio_delay), configDelay(p->config_delay),
+    : DmaDevice(p), plat(p->platform), configData(p->configdata),
+      pioDelay(p->pio_latency), configDelay(p->config_latency),
       configPort(NULL)
 {
     // copy the config data from the PciConfigData object
@@ -96,7 +95,7 @@ PciDev::PciDev(Params *p)
 
     memset(BARAddrs, 0, sizeof(BARAddrs));
 
-    plat->registerPciDevice(0, p->deviceNum, p->functionNum,
+    plat->registerPciDevice(0, p->pci_dev, p->pci_func,
             letoh(configData->config.interruptLine));
 }
 
@@ -135,21 +134,21 @@ PciDev::readConfig(PacketPtr pkt)
         pkt->set<uint8_t>(config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint8_t>());
         break;
       case sizeof(uint16_t):
         pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint16_t>());
         break;
       case sizeof(uint32_t):
         pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
         DPRINTF(PCIDEV,
             "readConfig:  dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint32_t>());
         break;
       default:
@@ -199,7 +198,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint8_t>());
         break;
       case sizeof(uint16_t):
@@ -216,7 +215,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint16_t>());
         break;
       case sizeof(uint32_t):
@@ -276,7 +275,7 @@ PciDev::writeConfig(PacketPtr pkt)
         }
         DPRINTF(PCIDEV,
             "writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
-            params()->deviceNum, params()->functionNum, offset,
+            params()->pci_dev, params()->pci_func, offset,
             (uint32_t)pkt->get<uint32_t>());
         break;
       default:
@@ -305,113 +304,38 @@ PciDev::unserialize(Checkpoint *cp, const std::string &section)
 
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-    Param<uint16_t> VendorID;
-    Param<uint16_t> DeviceID;
-    Param<uint16_t> Command;
-    Param<uint16_t> Status;
-    Param<uint8_t> Revision;
-    Param<uint8_t> ProgIF;
-    Param<uint8_t> SubClassCode;
-    Param<uint8_t> ClassCode;
-    Param<uint8_t> CacheLineSize;
-    Param<uint8_t> LatencyTimer;
-    Param<uint8_t> HeaderType;
-    Param<uint8_t> BIST;
-    Param<uint32_t> BAR0;
-    Param<uint32_t> BAR1;
-    Param<uint32_t> BAR2;
-    Param<uint32_t> BAR3;
-    Param<uint32_t> BAR4;
-    Param<uint32_t> BAR5;
-    Param<uint32_t> CardbusCIS;
-    Param<uint16_t> SubsystemVendorID;
-    Param<uint16_t> SubsystemID;
-    Param<uint32_t> ExpansionROM;
-    Param<uint8_t> InterruptLine;
-    Param<uint8_t> InterruptPin;
-    Param<uint8_t> MinimumGrant;
-    Param<uint8_t> MaximumLatency;
-    Param<uint32_t> BAR0Size;
-    Param<uint32_t> BAR1Size;
-    Param<uint32_t> BAR2Size;
-    Param<uint32_t> BAR3Size;
-    Param<uint32_t> BAR4Size;
-    Param<uint32_t> BAR5Size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PciConfigData)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-    INIT_PARAM(VendorID, "Vendor ID"),
-    INIT_PARAM(DeviceID, "Device ID"),
-    INIT_PARAM_DFLT(Command, "Command Register", 0x00),
-    INIT_PARAM_DFLT(Status, "Status Register", 0x00),
-    INIT_PARAM_DFLT(Revision, "Device Revision", 0x00),
-    INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00),
-    INIT_PARAM(SubClassCode, "Sub-Class Code"),
-    INIT_PARAM(ClassCode, "Class Code"),
-    INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00),
-    INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00),
-    INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00),
-    INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00),
-    INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00),
-    INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00),
-    INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00),
-    INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00),
-    INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00),
-    INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00),
-    INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00),
-    INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00),
-    INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00),
-    INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00),
-    INIT_PARAM(InterruptLine, "Interrupt Line Register"),
-    INIT_PARAM(InterruptPin, "Interrupt Pin Register"),
-    INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00),
-    INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00),
-    INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00),
-    INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00),
-    INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00),
-    INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00),
-    INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00),
-    INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00)
-
-END_INIT_SIM_OBJECT_PARAMS(PciConfigData)
-
-CREATE_SIM_OBJECT(PciConfigData)
+PciConfigData *
+PciConfigDataParams::create()
 {
-    PciConfigData *data = new PciConfigData(getInstanceName());
-
-    data->config.vendor = htole(VendorID.returnValue());
-    data->config.device = htole(DeviceID.returnValue());
-    data->config.command = htole(Command.returnValue());
-    data->config.status = htole(Status.returnValue());
-    data->config.revision = htole(Revision.returnValue());
-    data->config.progIF = htole(ProgIF.returnValue());
-    data->config.subClassCode = htole(SubClassCode.returnValue());
-    data->config.classCode = htole(ClassCode.returnValue());
-    data->config.cacheLineSize = htole(CacheLineSize.returnValue());
-    data->config.latencyTimer = htole(LatencyTimer.returnValue());
-    data->config.headerType = htole(HeaderType.returnValue());
-    data->config.bist = htole(BIST.returnValue());
-
-    data->config.baseAddr[0] = htole(BAR0.returnValue());
-    data->config.baseAddr[1] = htole(BAR1.returnValue());
-    data->config.baseAddr[2] = htole(BAR2.returnValue());
-    data->config.baseAddr[3] = htole(BAR3.returnValue());
-    data->config.baseAddr[4] = htole(BAR4.returnValue());
-    data->config.baseAddr[5] = htole(BAR5.returnValue());
-    data->config.cardbusCIS = htole(CardbusCIS.returnValue());
-    data->config.subsystemVendorID = htole(SubsystemVendorID.returnValue());
-    data->config.subsystemID = htole(SubsystemID.returnValue());
-    data->config.expansionROM = htole(ExpansionROM.returnValue());
-    data->config.interruptLine = htole(InterruptLine.returnValue());
-    data->config.interruptPin = htole(InterruptPin.returnValue());
-    data->config.minimumGrant = htole(MinimumGrant.returnValue());
-    data->config.maximumLatency = htole(MaximumLatency.returnValue());
+    PciConfigData *data = new PciConfigData(name);
+
+    data->config.vendor = htole(VendorID);
+    data->config.device = htole(DeviceID);
+    data->config.command = htole(Command);
+    data->config.status = htole(Status);
+    data->config.revision = htole(Revision);
+    data->config.progIF = htole(ProgIF);
+    data->config.subClassCode = htole(SubClassCode);
+    data->config.classCode = htole(ClassCode);
+    data->config.cacheLineSize = htole(CacheLineSize);
+    data->config.latencyTimer = htole(LatencyTimer);
+    data->config.headerType = htole(HeaderType);
+    data->config.bist = htole(BIST);
+
+    data->config.baseAddr[0] = htole(BAR0);
+    data->config.baseAddr[1] = htole(BAR1);
+    data->config.baseAddr[2] = htole(BAR2);
+    data->config.baseAddr[3] = htole(BAR3);
+    data->config.baseAddr[4] = htole(BAR4);
+    data->config.baseAddr[5] = htole(BAR5);
+    data->config.cardbusCIS = htole(CardbusCIS);
+    data->config.subsystemVendorID = htole(SubsystemVendorID);
+    data->config.subsystemID = htole(SubsystemID);
+    data->config.expansionROM = htole(ExpansionROM);
+    data->config.interruptLine = htole(InterruptLine);
+    data->config.interruptPin = htole(InterruptPin);
+    data->config.minimumGrant = htole(MinimumGrant);
+    data->config.maximumLatency = htole(MaximumLatency);
 
     data->BARSize[0] = BAR0Size;
     data->BARSize[1] = BAR1Size;
@@ -424,13 +348,9 @@ CREATE_SIM_OBJECT(PciConfigData)
         uint32_t barsize = data->BARSize[i];
         if (barsize != 0 && !isPowerOf2(barsize)) {
             fatal("%s: BAR %d size %d is not a power of 2\n",
-                  getInstanceName(), i, data->BARSize[i]);
+                  name, i, data->BARSize[i]);
         }
     }
 
     return data;
 }
-
-REGISTER_SIM_OBJECT("PciConfigData", PciConfigData)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh
index 5ddbe84a0..a08092689 100644
--- a/src/dev/pcidev.hh
+++ b/src/dev/pcidev.hh
@@ -42,6 +42,7 @@
 #include "dev/io_device.hh"
 #include "dev/pcireg.h"
 #include "dev/platform.hh"
+#include "params/PciDevice.hh"
 #include "sim/byteswap.hh"
 
 #define BAR_IO_MASK 0x3
@@ -105,32 +106,12 @@ class PciDev : public DmaDevice
     };
 
   public:
-    struct Params : public DmaDevice::Params
+    typedef PciDeviceParams Params;
+    const Params *
+    params() const
     {
-        /**
-         * A pointer to the object that contains the first 64 bytes of
-         * config space
-         */
-        PciConfigData *configData;
-
-        /** The bus number we are on */
-        uint32_t busNum;
-
-        /** The device number we have */
-        uint32_t deviceNum;
-
-        /** The function number */
-        uint32_t functionNum;
-
-        /** The latency for pio accesses. */
-        Tick pio_delay;
-
-        /** The latency for a config access. */
-        Tick config_delay;
-    };
-
-  public:
-    const Params *params() const { return (const Params *)_params; }
+        return dynamic_cast<const Params *>(_params);
+    }
 
   protected:
     /** The current config space. Unlike the PciConfigData this is
@@ -266,8 +247,8 @@ class PciDev : public DmaDevice
         if (if_name == "config") {
             if (configPort != NULL)
                 panic("pciconfig port already connected to.");
-            configPort = new PciConfigPort(this, params()->busNum,
-                    params()->deviceNum, params()->functionNum,
+            configPort = new PciConfigPort(this, params()->pci_bus,
+                    params()->pci_dev, params()->pci_func,
                     params()->platform);
             return configPort;
         }
diff --git a/src/dev/platform.cc b/src/dev/platform.cc
index b2b8695a7..c8922432b 100644
--- a/src/dev/platform.cc
+++ b/src/dev/platform.cc
@@ -31,7 +31,6 @@
 
 #include "base/misc.hh"
 #include "dev/platform.hh"
-#include "sim/builder.hh"
 #include "sim/sim_exit.hh"
 
 using namespace std;
@@ -79,7 +78,3 @@ Platform::registerPciDevice(uint8_t bus, uint8_t dev, uint8_t func, uint8_t intr
 
     intLines.set(intr);
 }
-
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Platform", Platform)
-
diff --git a/src/dev/simconsole.cc b/src/dev/simconsole.cc
index c6ff9c1c6..7ce462bd0 100644
--- a/src/dev/simconsole.cc
+++ b/src/dev/simconsole.cc
@@ -52,7 +52,7 @@
 #include "dev/platform.hh"
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
-#include "sim/builder.hh"
+#include "params/SimConsole.hh"
 
 using namespace std;
 
@@ -325,38 +325,17 @@ SimConsole::out(char c)
 
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
-
-    SimObjectParam<IntrControl *> intr_control;
-    Param<string> output;
-    Param<int> port;
-    Param<bool> append_name;
-    Param<int> number;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimConsole)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
-    INIT_PARAM(intr_control, "interrupt controller"),
-    INIT_PARAM(output, "file to dump output to"),
-    INIT_PARAM(port, ""),
-    INIT_PARAM_DFLT(append_name, "append name() to filename", true),
-    INIT_PARAM_DFLT(number, "console number", 0)
-
-END_INIT_SIM_OBJECT_PARAMS(SimConsole)
-
-CREATE_SIM_OBJECT(SimConsole)
+SimConsole *
+SimConsoleParams::create()
 {
     string filename = output;
     ostream *stream = NULL;
 
     if (!filename.empty()) {
         if (append_name)
-            filename += "." + getInstanceName();
+            filename += "." + name;
         stream = simout.find(filename);
     }
 
-    return new SimConsole(getInstanceName(), stream, number, port);
+    return new SimConsole(name, stream, number, port);
 }
-
-REGISTER_SIM_OBJECT("SimConsole", SimConsole)
diff --git a/src/dev/simple_disk.cc b/src/dev/simple_disk.cc
index e29bfa726..4b6d37286 100644
--- a/src/dev/simple_disk.cc
+++ b/src/dev/simple_disk.cc
@@ -45,7 +45,7 @@
 #include "dev/disk_image.hh"
 #include "dev/simple_disk.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
+#include "params/SimpleDisk.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -91,23 +91,8 @@ SimpleDisk::write(Addr addr, baddr_t block, int count)
 #endif
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<DiskImage *> disk;
-
-END_DECLARE_SIM_OBJECT_PARAMS(SimpleDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(disk, "Disk Image")
-
-END_INIT_SIM_OBJECT_PARAMS(SimpleDisk)
-
-CREATE_SIM_OBJECT(SimpleDisk)
+SimpleDisk *
+SimpleDiskParams::create()
 {
-    return new SimpleDisk(getInstanceName(), system, disk);
+    return new SimpleDisk(name, system, disk);
 }
-
-REGISTER_SIM_OBJECT("SimpleDisk", SimpleDisk)
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index e13fdb0bc..ed5ab428c 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -32,6 +32,7 @@
 #include <limits>
 #include <string>
 
+#include "arch/vtophys.hh"
 #include "base/inet.hh"
 #include "cpu/thread_context.hh"
 #include "cpu/intr_control.hh"
@@ -39,12 +40,10 @@
 #include "dev/sinic.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/debug.hh"
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 #include "sim/stats.hh"
-#include "arch/vtophys.hh"
 
 using namespace Net;
 using namespace TheISA;
@@ -754,7 +753,7 @@ Device::reset()
     regs.TxFifoSize = params()->tx_fifo_size;
     regs.RxFifoMark = params()->rx_fifo_threshold;
     regs.TxFifoMark = params()->tx_fifo_threshold;
-    regs.HwAddr = params()->eaddr;
+    regs.HwAddr = params()->hardware_address;
 
     rxList.clear();
     rxBusy.clear();
@@ -1596,172 +1595,23 @@ Device::unserialize(Checkpoint *cp, const std::string &section)
 
 /* namespace Sinic */ }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-    SimObjectParam<EtherInt *> peer;
-    SimObjectParam<Sinic::Device *> device;
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-    INIT_PARAM_DFLT(peer, "peer interface", NULL),
-    INIT_PARAM(device, "Ethernet device of this interface")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicInterface)
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicInterface)
+Sinic::Interface *
+SinicIntParams::create()
 {
-    Sinic::Interface *dev_int = new Sinic::Interface(getInstanceName(), device);
+    using namespace Sinic;
+
+    Interface *dev_int = new Interface(name, device);
 
-    EtherInt *p = (EtherInt *)peer;
-    if (p) {
-        dev_int->setPeer(p);
-        p->setPeer(dev_int);
+    if (peer) {
+        dev_int->setPeer(peer);
+        peer->setPeer(dev_int);
     }
 
     return dev_int;
 }
 
-REGISTER_SIM_OBJECT_WNS(Sinic, "SinicInt", SinicInterface)
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-    SimObjectParam<System *> system;
-    SimObjectParam<Platform *> platform;
-    Param<Tick> min_backoff_delay;
-    Param<Tick> max_backoff_delay;
-    SimObjectParam<PciConfigData *> configdata;
-    Param<uint32_t> pci_bus;
-    Param<uint32_t> pci_dev;
-    Param<uint32_t> pci_func;
-    Param<Tick> pio_latency;
-    Param<Tick> config_latency;
-    Param<Tick> intr_delay;
-
-    Param<Tick> clock;
-    Param<Tick> dma_read_delay;
-    Param<Tick> dma_read_factor;
-    Param<Tick> dma_write_delay;
-    Param<Tick> dma_write_factor;
-
-    Param<Tick> rx_delay;
-    Param<Tick> tx_delay;
-    Param<uint32_t> rx_max_copy;
-    Param<uint32_t> tx_max_copy;
-    Param<uint32_t> rx_max_intr;
-    Param<uint32_t> rx_fifo_size;
-    Param<uint32_t> tx_fifo_size;
-    Param<uint32_t> rx_fifo_threshold;
-    Param<uint32_t> rx_fifo_low_mark;
-    Param<uint32_t> tx_fifo_high_mark;
-    Param<uint32_t> tx_fifo_threshold;
-
-    Param<bool> rx_filter;
-    Param<std::string> hardware_address;
-    Param<bool> rx_thread;
-    Param<bool> tx_thread;
-    Param<bool> rss;
-    Param<uint32_t> virtual_count;
-    Param<bool> zero_copy;
-    Param<bool> delay_copy;
-    Param<bool> virtual_addr;
-
-END_DECLARE_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-    INIT_PARAM(system, "System pointer"),
-    INIT_PARAM(platform, "Platform pointer"),
-    INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
-    INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
-    INIT_PARAM(configdata, "PCI Config data"),
-    INIT_PARAM(pci_bus, "PCI bus ID"),
-    INIT_PARAM(pci_dev, "PCI device number"),
-    INIT_PARAM(pci_func, "PCI function code"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
-    INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
-    INIT_PARAM(intr_delay, "Interrupt Delay"),
-    INIT_PARAM(clock, "State machine cycle time"),
-
-    INIT_PARAM(dma_read_delay, "fixed delay for dma reads"),
-    INIT_PARAM(dma_read_factor, "multiplier for dma reads"),
-    INIT_PARAM(dma_write_delay, "fixed delay for dma writes"),
-    INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
-
-    INIT_PARAM(rx_delay, "Receive Delay"),
-    INIT_PARAM(tx_delay, "Transmit Delay"),
-    INIT_PARAM(rx_max_copy, "rx max copy"),
-    INIT_PARAM(tx_max_copy, "rx max copy"),
-    INIT_PARAM(rx_max_intr, "rx max intr"),
-    INIT_PARAM(rx_fifo_size, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_size, "max size in bytes of txFifo"),
-    INIT_PARAM(rx_fifo_threshold, "max size in bytes of rxFifo"),
-    INIT_PARAM(rx_fifo_low_mark, "max size in bytes of rxFifo"),
-    INIT_PARAM(tx_fifo_high_mark, "max size in bytes of txFifo"),
-    INIT_PARAM(tx_fifo_threshold, "max size in bytes of txFifo"),
-
-    INIT_PARAM(rx_filter, "Enable Receive Filter"),
-    INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
-    INIT_PARAM(rx_thread, ""),
-    INIT_PARAM(tx_thread, ""),
-    INIT_PARAM(rss, ""),
-    INIT_PARAM(virtual_count, ""),
-    INIT_PARAM(zero_copy, ""),
-    INIT_PARAM(delay_copy, ""),
-    INIT_PARAM(virtual_addr, "")
-
-END_INIT_SIM_OBJECT_PARAMS_WNS(Sinic, SinicDevice)
-
-
-CREATE_SIM_OBJECT_WNS(Sinic, SinicDevice)
+Sinic::Device *
+SinicParams::create()
 {
-    Sinic::Sinic::Device::Params *params = new Device::Params;
-    params->name = getInstanceName();
-    params->platform = platform;
-    params->system = system;
-    params->min_backoff_delay = min_backoff_delay;
-    params->max_backoff_delay = max_backoff_delay;
-    params->configData = configdata;
-    params->busNum = pci_bus;
-    params->deviceNum = pci_dev;
-    params->functionNum = pci_func;
-    params->pio_delay = pio_latency;
-    params->config_delay = config_latency;
-    params->intr_delay = intr_delay;
-    params->clock = clock;
-
-    params->dma_read_delay = dma_read_delay;
-    params->dma_read_factor = dma_read_factor;
-    params->dma_write_delay = dma_write_delay;
-    params->dma_write_factor = dma_write_factor;
-
-    params->tx_delay = tx_delay;
-    params->rx_delay = rx_delay;
-    params->rx_max_copy = rx_max_copy;
-    params->tx_max_copy = tx_max_copy;
-    params->rx_max_intr = rx_max_intr;
-    params->rx_fifo_size = rx_fifo_size;
-    params->tx_fifo_size = tx_fifo_size;
-    params->rx_fifo_threshold = rx_fifo_threshold;
-    params->rx_fifo_low_mark = rx_fifo_low_mark;
-    params->tx_fifo_high_mark = tx_fifo_high_mark;
-    params->tx_fifo_threshold = tx_fifo_threshold;
-
-    params->rx_filter = rx_filter;
-    params->eaddr = hardware_address;
-    params->rx_thread = rx_thread;
-    params->tx_thread = tx_thread;
-    params->rss = rss;
-    params->virtual_count = virtual_count;
-    params->zero_copy = zero_copy;
-    params->delay_copy = delay_copy;
-    params->virtual_addr = virtual_addr;
-
-    return new Sinic::Device(params);
+    return new Sinic::Device(this);
 }
-
-REGISTER_SIM_OBJECT_WNS(Sinic, "Sinic", SinicDevice)
-
diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh
index 3904c2a8a..ab5d0d258 100644
--- a/src/dev/sinic.hh
+++ b/src/dev/sinic.hh
@@ -39,6 +39,8 @@
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
 #include "dev/sinicreg.hh"
+#include "params/Sinic.hh"
+#include "params/SinicInt.hh"
 #include "sim/eventq.hh"
 
 namespace Sinic {
@@ -80,12 +82,8 @@ class Base : public PciDev
  * Construction/Destruction/Parameters
  */
   public:
-    struct Params : public PciDev::Params
-    {
-        Tick clock;
-        Tick intr_delay;
-    };
-
+    typedef SinicParams Params;
+    const Params *params() const { return (const Params *)_params; }
     Base(Params *p);
 };
 
@@ -313,43 +311,8 @@ class Device : public Base
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-/**
- * Construction/Destruction/Parameters
- */
-  public:
-    struct Params : public Base::Params
-    {
-        Tick tx_delay;
-        Tick rx_delay;
-        bool rx_filter;
-        Net::EthAddr eaddr;
-        uint32_t rx_max_copy;
-        uint32_t tx_max_copy;
-        uint32_t rx_max_intr;
-        uint32_t rx_fifo_size;
-        uint32_t tx_fifo_size;
-        uint32_t rx_fifo_threshold;
-        uint32_t rx_fifo_low_mark;
-        uint32_t tx_fifo_high_mark;
-        uint32_t tx_fifo_threshold;
-        Tick dma_read_delay;
-        Tick dma_read_factor;
-        Tick dma_write_delay;
-        Tick dma_write_factor;
-        bool rx_thread;
-        bool tx_thread;
-        bool rss;
-        uint32_t virtual_count;
-        bool zero_copy;
-        bool delay_copy;
-        bool virtual_addr;
-    };
-
-  protected:
-    const Params *params() const { return (const Params *)_params; }
-
   public:
-    Device(Params *params);
+    Device(Params *p);
     ~Device();
 };
 
diff --git a/src/dev/sparc/dtod.cc b/src/dev/sparc/dtod.cc
index 22df873b6..81132ac65 100644
--- a/src/dev/sparc/dtod.cc
+++ b/src/dev/sparc/dtod.cc
@@ -37,26 +37,25 @@
 #include <string>
 #include <vector>
 
+#include "base/time.hh"
 #include "base/trace.hh"
 #include "dev/sparc/dtod.hh"
 #include "dev/platform.hh"
 #include "mem/packet_access.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/system.hh"
 
 using namespace std;
 using namespace TheISA;
 
-DumbTOD::DumbTOD(Params *p)
+DumbTOD::DumbTOD(const Params *p)
     : BasicPioDevice(p)
 {
-    struct tm tm;
+    struct tm tm = p->time;
     char *tz;
 
     pioSize = 0x08;
 
-    parseTime(p->init_time, &tm);
     tz = getenv("TZ");
     setenv("TZ", "", 1);
     tzset();
@@ -103,37 +102,8 @@ DumbTOD::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(todTime);
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    VectorParam<int> time;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DumbTOD)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(time, "")
-
-END_INIT_SIM_OBJECT_PARAMS(DumbTOD)
-
-CREATE_SIM_OBJECT(DumbTOD)
+DumbTOD *
+DumbTODParams::create()
 {
-    DumbTOD::Params *p = new DumbTOD::Params;
-    p->name =getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->init_time = time;
-    return new DumbTOD(p);
+    return new DumbTOD(this);
 }
-
-REGISTER_SIM_OBJECT("DumbTOD", DumbTOD)
diff --git a/src/dev/sparc/dtod.hh b/src/dev/sparc/dtod.hh
index ddf9fcc96..35dda42dd 100644
--- a/src/dev/sparc/dtod.hh
+++ b/src/dev/sparc/dtod.hh
@@ -40,7 +40,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
-
+#include "params/DumbTOD.hh"
 
 /**
  * DumbTOD simply returns some idea of time when read.  Until we finish with
@@ -52,15 +52,14 @@ class DumbTOD : public BasicPioDevice
     uint64_t todTime;
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        std::vector<int> init_time;
-    };
-  protected:
-    const Params *params() const { return (const Params *)_params; }
+    typedef DumbTODParams Params;
+    DumbTOD(const Params *p);
 
-  public:
-    DumbTOD(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
diff --git a/src/dev/sparc/iob.cc b/src/dev/sparc/iob.cc
index b27f45eba..d0182770f 100644
--- a/src/dev/sparc/iob.cc
+++ b/src/dev/sparc/iob.cc
@@ -45,11 +45,10 @@
 #include "dev/platform.hh"
 #include "mem/port.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/faults.hh"
 #include "sim/system.hh"
 
-Iob::Iob(Params *p)
+Iob::Iob(const Params *p)
     : PioDevice(p), ic(p->platform->intrctrl)
 {
     iobManAddr = ULL(0x9800000000);
@@ -371,31 +370,8 @@ Iob::unserialize(Checkpoint *cp, const std::string &section)
     };
 }
 
-
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Iob)
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-END_DECLARE_SIM_OBJECT_PARAMS(Iob)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Iob)
-
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Iob)
-
-CREATE_SIM_OBJECT(Iob)
+Iob *
+IobParams::create()
 {
-    Iob::Params *p = new Iob::Params;
-    p->name = getInstanceName();
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    return new Iob(p);
+    return new Iob(this);
 }
-
-REGISTER_SIM_OBJECT("Iob", Iob)
diff --git a/src/dev/sparc/iob.hh b/src/dev/sparc/iob.hh
index c05c4f2ef..b2fd6cbf6 100644
--- a/src/dev/sparc/iob.hh
+++ b/src/dev/sparc/iob.hh
@@ -39,6 +39,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/disk_image.hh"
+#include "params/Iob.hh"
 
 class IntrControl;
 
@@ -123,24 +124,22 @@ class Iob : public PioDevice
     void readIob(PacketPtr pkt);
     void readJBus(PacketPtr pkt);
 
-
   public:
-    struct Params : public PioDevice::Params
-    {
-        Tick pio_delay;
-    };
-  protected:
-    const Params *params() const { return (const Params*)_params; }
+    typedef IobParams Params;
+    Iob(const Params *p);
 
-  public:
-    Iob(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
     void generateIpi(Type type, int cpu_id, int vector);
     void receiveDeviceInterrupt(DeviceId devid);
-    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1);
-
+    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
+                              uint64_t d1);
 
     void addressRanges(AddrRangeList &range_list);
 
diff --git a/src/dev/sparc/mm_disk.cc b/src/dev/sparc/mm_disk.cc
index bbb773c48..f0d51eef4 100644
--- a/src/dev/sparc/mm_disk.cc
+++ b/src/dev/sparc/mm_disk.cc
@@ -40,11 +40,10 @@
 #include "dev/platform.hh"
 #include "mem/port.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "sim/system.hh"
 
-MmDisk::MmDisk(Params *p)
+MmDisk::MmDisk(const Params *p)
     : BasicPioDevice(p), image(p->image), curSector((off_t)-1), dirty(false)
 {
     std::memset(&diskData, 0, SectorSize);
@@ -171,39 +170,8 @@ MmDisk::serialize(std::ostream &os)
     }
 }
 
-
-
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    Param<Addr> pio_size;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<System *> system;
-    SimObjectParam<DiskImage *> image;
-END_DECLARE_SIM_OBJECT_PARAMS(MmDisk)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM(pio_latency, "Programmed IO latency"),
-    INIT_PARAM(pio_size, "Size of address range"),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(system, "system object"),
-    INIT_PARAM(image, "disk image")
-
-END_INIT_SIM_OBJECT_PARAMS(MmDisk)
-
-CREATE_SIM_OBJECT(MmDisk)
+MmDisk *
+MmDiskParams::create()
 {
-    MmDisk::Params *p = new MmDisk::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->system = system;
-    p->image = image;
-    return new MmDisk(p);
+    return new MmDisk(this);
 }
-
-REGISTER_SIM_OBJECT("MmDisk", MmDisk)
diff --git a/src/dev/sparc/mm_disk.hh b/src/dev/sparc/mm_disk.hh
index 30028d2b6..41ec0cc59 100644
--- a/src/dev/sparc/mm_disk.hh
+++ b/src/dev/sparc/mm_disk.hh
@@ -39,6 +39,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/disk_image.hh"
+#include "params/MmDisk.hh"
 
 class MmDisk : public BasicPioDevice
 {
@@ -49,15 +50,14 @@ class MmDisk : public BasicPioDevice
     uint8_t diskData[SectorSize];
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        DiskImage *image;
-    };
-  protected:
-    const Params *params() const { return (const Params*)_params; }
+    typedef MmDiskParams Params;
+    MmDisk(const Params *p);
 
-  public:
-    MmDisk(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
diff --git a/src/dev/sparc/t1000.cc b/src/dev/sparc/t1000.cc
index 3a2f881f1..692e0cfe1 100644
--- a/src/dev/sparc/t1000.cc
+++ b/src/dev/sparc/t1000.cc
@@ -39,7 +39,7 @@
 #include "cpu/intr_control.hh"
 #include "dev/simconsole.hh"
 #include "dev/sparc/t1000.hh"
-#include "sim/builder.hh"
+#include "params/T1000.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -101,23 +101,8 @@ T1000::calcConfigAddr(int bus, int dev, int func)
     M5_DUMMY_RETURN
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(T1000)
-
-    SimObjectParam<System *> system;
-    SimObjectParam<IntrControl *> intrctrl;
-
-END_DECLARE_SIM_OBJECT_PARAMS(T1000)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(T1000)
-
-    INIT_PARAM(system, "system"),
-    INIT_PARAM(intrctrl, "interrupt controller")
-
-END_INIT_SIM_OBJECT_PARAMS(T1000)
-
-CREATE_SIM_OBJECT(T1000)
+T1000 *
+T1000Params::create()
 {
-    return new T1000(getInstanceName(), system, intrctrl);
+    return new T1000(name, system, intrctrl);
 }
-
-REGISTER_SIM_OBJECT("T1000", T1000)
diff --git a/src/dev/uart.cc b/src/dev/uart.cc
index 1c781f76d..c9a2ae964 100644
--- a/src/dev/uart.cc
+++ b/src/dev/uart.cc
@@ -35,19 +35,14 @@
 #include "dev/simconsole.hh"
 #include "dev/uart.hh"
 #include "dev/platform.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 
-Uart::Uart(Params *p)
-    : BasicPioDevice(p), platform(p->platform), cons(p->cons)
+Uart::Uart(const Params *p)
+    : BasicPioDevice(p), platform(p->platform), cons(p->sim_console)
 {
-
     status = 0;
 
     // set back pointers
     cons->uart = this;
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)
-
diff --git a/src/dev/uart.hh b/src/dev/uart.hh
index f0ae0854c..f5d5e2855 100644
--- a/src/dev/uart.hh
+++ b/src/dev/uart.hh
@@ -37,6 +37,7 @@
 
 #include "base/range.hh"
 #include "dev/io_device.hh"
+#include "params/Uart.hh"
 
 class SimConsole;
 class Platform;
@@ -44,7 +45,6 @@ class Platform;
 const int RX_INT = 0x1;
 const int TX_INT = 0x2;
 
-
 class Uart : public BasicPioDevice
 {
 
@@ -54,28 +54,25 @@ class Uart : public BasicPioDevice
     SimConsole *cons;
 
   public:
-    struct Params : public BasicPioDevice::Params
-    {
-        SimConsole *cons;
-    };
+    typedef UartParams Params;
+    Uart(const Params *p);
 
-    Uart(Params *p);
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
 
     /**
      * Inform the uart that there is data available.
      */
     virtual void dataAvailable() = 0;
 
-
     /**
      * Return if we have an interrupt pending
      * @return interrupt status
      */
     bool intStatus() { return status ? true : false; }
-
-  protected:
-    const Params *params() const {return (const Params *)_params; }
-
 };
 
 #endif // __UART_HH__
diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc
index 358dda0d8..e14b0871e 100644
--- a/src/dev/uart8250.cc
+++ b/src/dev/uart8250.cc
@@ -43,7 +43,6 @@
 #include "dev/platform.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
-#include "sim/builder.hh"
 
 using namespace std;
 using namespace TheISA;
@@ -100,12 +99,11 @@ Uart8250::IntrEvent::scheduleIntr()
 }
 
 
-Uart8250::Uart8250(Params *p)
+Uart8250::Uart8250(const Params *p)
     : Uart(p), IER(0), DLAB(0), LCR(0), MCR(0), lastTxInt(0),
       txIntrEvent(this, TX_INT), rxIntrEvent(this, RX_INT)
 {
     pioSize = 8;
-
 }
 
 Tick
@@ -336,37 +334,8 @@ Uart8250::unserialize(Checkpoint *cp, const std::string &section)
         txIntrEvent.schedule(txintrwhen);
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
-
-    Param<Addr> pio_addr;
-    Param<Tick> pio_latency;
-    SimObjectParam<Platform *> platform;
-    SimObjectParam<SimConsole *> sim_console;
-    SimObjectParam<System *> system;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Uart8250)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
-    INIT_PARAM(pio_addr, "Device Address"),
-    INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000),
-    INIT_PARAM(platform, "platform"),
-    INIT_PARAM(sim_console, "The Simulator Console"),
-    INIT_PARAM(system, "system object")
-
-END_INIT_SIM_OBJECT_PARAMS(Uart8250)
-
-CREATE_SIM_OBJECT(Uart8250)
+Uart8250 *
+Uart8250Params::create()
 {
-    Uart8250::Params *p = new Uart8250::Params;
-    p->name = getInstanceName();
-    p->pio_addr = pio_addr;
-    p->pio_delay = pio_latency;
-    p->platform = platform;
-    p->cons = sim_console;
-    p->system = system;
-    return new Uart8250(p);
+    return new Uart8250(this);
 }
-
-REGISTER_SIM_OBJECT("Uart8250", Uart8250)
-
diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh
index c9c878aed..32b16c17c 100644
--- a/src/dev/uart8250.hh
+++ b/src/dev/uart8250.hh
@@ -38,7 +38,7 @@
 #include "base/range.hh"
 #include "dev/io_device.hh"
 #include "dev/uart.hh"
-
+#include "params/Uart8250.hh"
 
 /* UART8250 Interrupt ID Register
  *  bit 0    Interrupt Pending 0 = true, 1 = false
@@ -70,8 +70,6 @@ class Platform;
 
 class Uart8250 : public Uart
 {
-
-
   protected:
     uint8_t IER, DLAB, LCR, MCR;
     Tick lastTxInt;
@@ -92,13 +90,18 @@ class Uart8250 : public Uart
     IntrEvent rxIntrEvent;
 
   public:
-    Uart8250(Params *p);
+    typedef Uart8250Params Params;
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+    Uart8250(const Params *p);
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
     virtual void addressRanges(AddrRangeList &range_list);
 
-
     /**
      * Inform the uart that there is data available.
      */
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index a7703be7c..70fb4d688 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -690,7 +690,7 @@ class Tru64 : public OperatingSystem
 
         tc->clearArchRegs();
 
-        tc->setIntReg(TheISA::ArgumentReg0, gtoh(attrp->registers.a0));
+        tc->setIntReg(TheISA::ArgumentReg[0], gtoh(attrp->registers.a0));
         tc->setIntReg(27/*t12*/, gtoh(attrp->registers.pc));
         tc->setIntReg(TheISA::StackPointerReg, gtoh(attrp->registers.sp));
         tc->setMiscRegNoEffect(AlphaISA::MISCREG_UNIQ, uniq_val);
diff --git a/src/kern/tru64/tru64_events.cc b/src/kern/tru64/tru64_events.cc
index 4db5df067..c84b25dab 100644
--- a/src/kern/tru64/tru64_events.cc
+++ b/src/kern/tru64/tru64_events.cc
@@ -51,7 +51,7 @@ BadAddrEvent::process(ThreadContext *tc)
     // annotation for vmunix::badaddr in:
     // simos/simulation/apps/tcl/osf/tlaser.tcl
 
-    uint64_t a0 = tc->readIntReg(ArgumentReg0);
+    uint64_t a0 = tc->readIntReg(ArgumentReg[0]);
 
     AddrRangeList resp;
     bool snoop;
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index 269cf4403..e2e858494 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -27,7 +27,6 @@
 # Authors: Ron Dreslinski
 
 from m5.SimObject import SimObject
-from m5.SimObject import SimObject
 
 class MemObject(SimObject):
     type = 'MemObject'
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index d6adb05d1..6cfa5a2ac 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -39,7 +39,7 @@
 
 #include "base/trace.hh"
 #include "mem/bridge.hh"
-#include "sim/builder.hh"
+#include "params/Bridge.hh"
 
 Bridge::BridgePort::BridgePort(const std::string &_name,
                                Bridge *_bridge, BridgePort *_otherPort,
@@ -359,50 +359,8 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
     snoop = false;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-   Param<int> req_size_a;
-   Param<int> req_size_b;
-   Param<int> resp_size_a;
-   Param<int> resp_size_b;
-   Param<Tick> delay;
-   Param<Tick> nack_delay;
-   Param<bool> write_ack;
-   Param<bool> fix_partial_write_a;
-   Param<bool> fix_partial_write_b;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bridge)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-    INIT_PARAM(req_size_a, "The size of the queue for requests coming into side a"),
-    INIT_PARAM(req_size_b, "The size of the queue for requests coming into side b"),
-    INIT_PARAM(resp_size_a, "The size of the queue for responses coming into side a"),
-    INIT_PARAM(resp_size_b, "The size of the queue for responses coming into side b"),
-    INIT_PARAM(delay, "The miminum delay to cross this bridge"),
-    INIT_PARAM(nack_delay, "The minimum delay to nack a packet"),
-    INIT_PARAM(write_ack, "Acknowledge any writes that are received."),
-    INIT_PARAM(fix_partial_write_a, "Fixup any partial block writes that are received"),
-    INIT_PARAM(fix_partial_write_b, "Fixup any partial block writes that are received")
-
-END_INIT_SIM_OBJECT_PARAMS(Bridge)
-
-CREATE_SIM_OBJECT(Bridge)
+Bridge *
+BridgeParams::create()
 {
-    Bridge::Params *p = new Bridge::Params;
-    p->name = getInstanceName();
-    p->req_size_a = req_size_a;
-    p->req_size_b = req_size_b;
-    p->resp_size_a = resp_size_a;
-    p->resp_size_b = resp_size_b;
-    p->delay = delay;
-    p->nack_delay = nack_delay;
-    p->write_ack = write_ack;
-    p->fix_partial_write_a = fix_partial_write_a;
-    p->fix_partial_write_b = fix_partial_write_b;
-    return new Bridge(p);
+    return new Bridge(this);
 }
-
-REGISTER_SIM_OBJECT("Bridge", Bridge)
-
-
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index acae2f126..d3bbf2ddf 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -45,6 +45,7 @@
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/port.hh"
+#include "params/Bridge.hh"
 #include "sim/eventq.hh"
 
 class Bridge : public MemObject
@@ -191,19 +192,7 @@ class Bridge : public MemObject
     bool ackWrites;
 
   public:
-    struct Params
-    {
-        std::string name;
-        int req_size_a;
-        int req_size_b;
-        int resp_size_a;
-        int resp_size_b;
-        Tick delay;
-        Tick nack_delay;
-        bool write_ack;
-        bool fix_partial_write_a;
-        bool fix_partial_write_b;
-    };
+    typedef BridgeParams Params;
 
   protected:
     Params *_params;
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 1fad13c5a..518c9dbfa 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/Bus.hh"
 
 Port *
 Bus::getPort(const std::string &if_name, int idx)
@@ -599,28 +599,8 @@ Bus::startup()
         tickNextIdle = (curTick / clock) * clock + clock;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-    Param<int> bus_id;
-    Param<int> clock;
-    Param<int> width;
-    Param<bool> responder_set;
-    Param<int> block_size;
-
-END_DECLARE_SIM_OBJECT_PARAMS(Bus)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
-    INIT_PARAM(bus_id, "a globally unique bus id"),
-    INIT_PARAM(clock, "bus clock speed"),
-    INIT_PARAM(width, "width of the bus (bits)"),
-    INIT_PARAM(responder_set, "Is a default responder set by the user"),
-    INIT_PARAM(block_size, "Default blocksize if no device has one")
-END_INIT_SIM_OBJECT_PARAMS(Bus)
-
-CREATE_SIM_OBJECT(Bus)
+Bus *
+BusParams::create()
 {
-    return new Bus(getInstanceName(), bus_id, clock, width, responder_set,
-            block_size);
+    return new Bus(name, bus_id, clock, width, responder_set, block_size);
 }
-
-REGISTER_SIM_OBJECT("Bus", Bus)
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 65418b68d..4c9592a1b 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -36,13 +36,13 @@
 #include <vector>
 
 // Must be included first to determine which caches we want
+#include "enums/Prefetch.hh"
 #include "mem/config/cache.hh"
 #include "mem/config/prefetch.hh"
-
 #include "mem/cache/base_cache.hh"
 #include "mem/cache/cache.hh"
 #include "mem/bus.hh"
-#include "sim/builder.hh"
+#include "params/BaseCache.hh"
 
 // Tag Templates
 #if defined(USE_CACHE_LRU)
@@ -80,100 +80,16 @@
 using namespace std;
 using namespace TheISA;
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-    Param<int> size;
-    Param<int> assoc;
-    Param<int> block_size;
-    Param<int> latency;
-    Param<int> mshrs;
-    Param<int> tgts_per_mshr;
-    Param<int> write_buffers;
-    Param<bool> prioritizeRequests;
-    Param<Addr> trace_addr;
-    Param<int> hash_delay;
-#if defined(USE_CACHE_IIC)
-    SimObjectParam<Repl *> repl;
-#endif
-    Param<int> subblock_size;
-    Param<Counter> max_miss_count;
-    VectorParam<Range<Addr> > addr_range;
-//    SimObjectParam<MemTraceWriter *> mem_trace;
-    Param<bool> split;
-    Param<int> split_size;
-    Param<bool> lifo;
-    Param<bool> two_queue;
-    Param<bool> prefetch_miss;
-    Param<bool> prefetch_access;
-    Param<int> prefetcher_size;
-    Param<bool> prefetch_past_page;
-    Param<bool> prefetch_serial_squash;
-    Param<Tick> prefetch_latency;
-    Param<int> prefetch_degree;
-    Param<string> prefetch_policy;
-    Param<bool> prefetch_cache_check_push;
-    Param<bool> prefetch_use_cpu_id;
-    Param<bool> prefetch_data_accesses_only;
-
-END_DECLARE_SIM_OBJECT_PARAMS(BaseCache)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-    INIT_PARAM(size, "capacity in bytes"),
-    INIT_PARAM(assoc, "associativity"),
-    INIT_PARAM(block_size, "block size in bytes"),
-    INIT_PARAM(latency, "hit latency in CPU cycles"),
-    INIT_PARAM(mshrs, "number of MSHRs (max outstanding requests)"),
-    INIT_PARAM(tgts_per_mshr, "max number of accesses per MSHR"),
-    INIT_PARAM_DFLT(write_buffers, "number of write buffers", 8),
-    INIT_PARAM_DFLT(prioritizeRequests, "always service demand misses first",
-                    false),
-    INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
-
-    INIT_PARAM_DFLT(hash_delay, "time in cycles of hash access",1),
-#if defined(USE_CACHE_IIC)
-    INIT_PARAM_DFLT(repl, "replacement policy",NULL),
-#endif
-    INIT_PARAM_DFLT(subblock_size,
-                    "Size of subblock in IIC used for compression",
-                    0),
-    INIT_PARAM_DFLT(max_miss_count,
-                    "The number of misses to handle before calling exit",
-                    0),
-    INIT_PARAM_DFLT(addr_range, "The address range in bytes",
-                    vector<Range<Addr> >(1,RangeIn((Addr)0, MaxAddr))),
-//    INIT_PARAM_DFLT(mem_trace, "Memory trace to write accesses to", NULL),
-    INIT_PARAM_DFLT(split, "Whether this is a partitioned cache", false),
-    INIT_PARAM_DFLT(split_size, "the number of \"ways\" belonging to the LRU partition", 0),
-    INIT_PARAM_DFLT(lifo, "whether you are using a LIFO repl. policy", false),
-    INIT_PARAM_DFLT(two_queue, "whether the lifo should have two queue replacement", false),
-    INIT_PARAM_DFLT(prefetch_miss, "wheter you are using the hardware prefetcher from Miss stream", false),
-    INIT_PARAM_DFLT(prefetch_access, "wheter you are using the hardware prefetcher from Access stream", false),
-    INIT_PARAM_DFLT(prefetcher_size, "Number of entries in the harware prefetch queue", 100),
-    INIT_PARAM_DFLT(prefetch_past_page, "Allow prefetches to cross virtual page boundaries", false),
-    INIT_PARAM_DFLT(prefetch_serial_squash, "Squash prefetches with a later time on a subsequent miss", false),
-    INIT_PARAM_DFLT(prefetch_latency, "Latency of the prefetcher", 10),
-    INIT_PARAM_DFLT(prefetch_degree, "Degree of the prefetch depth", 1),
-    INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"),
-    INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true),
-    INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true),
-    INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false)
-END_INIT_SIM_OBJECT_PARAMS(BaseCache)
-
-
 #define BUILD_CACHE(TAGS, tags)                                      \
     do {                                                                \
-        BasePrefetcher *pf;                                           \
-        if (pf_policy == "tagged") {                                    \
+        BasePrefetcher *pf;                                             \
+        if (prefetch_policy == Enums::tagged) {                         \
             BUILD_TAGGED_PREFETCHER(TAGS);                              \
         }                                                               \
-        else if (pf_policy == "stride") {                               \
+        else if (prefetch_policy == Enums::stride) {                    \
             BUILD_STRIDED_PREFETCHER(TAGS);                             \
         }                                                               \
-        else if (pf_policy == "ghb") {                                  \
+        else if (prefetch_policy == Enums::ghb) {                       \
             BUILD_GHB_PREFETCHER(TAGS);                                 \
         }                                                               \
         else {                                                          \
@@ -184,7 +100,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
                                    true,                                \
                                    prefetch_miss);                      \
         Cache<TAGS> *retval =                                        \
-            new Cache<TAGS>(getInstanceName(), params);              \
+            new Cache<TAGS>(name, params);                              \
         return retval;                                                  \
     } while (0)
 
@@ -314,11 +230,10 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache)
 #define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses Tagged)")
 #endif
 
-CREATE_SIM_OBJECT(BaseCache)
+BaseCache *
+BaseCacheParams::create()
 {
-    string name = getInstanceName();
     int numSets = size / (assoc * block_size);
-    string pf_policy = prefetch_policy;
     if (subblock_size == 0) {
         subblock_size = block_size;
     }
@@ -329,24 +244,21 @@ CREATE_SIM_OBJECT(BaseCache)
                                   max_miss_count);
 
     //Warnings about prefetcher policy
-    if (pf_policy == "none" && (prefetch_miss || prefetch_access)) {
-        panic("With no prefetcher, you shouldn't prefetch from"
-              " either miss or access stream\n");
+    if (prefetch_policy == Enums::none) {
+        if (prefetch_miss || prefetch_access)
+            panic("With no prefetcher, you shouldn't prefetch from"
+                  " either miss or access stream\n");
     }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && !(prefetch_miss || prefetch_access)) {
-        warn("With this prefetcher you should chose a prefetch"
-             " stream (miss or access)\nNo Prefetching will occur\n");
-    }
-    if ((pf_policy == "tagged" || pf_policy == "stride" ||
-         pf_policy == "ghb") && prefetch_miss && prefetch_access) {
-        panic("Can't do prefetches from both miss and access"
-              " stream\n");
-    }
-    if (pf_policy != "tagged" && pf_policy != "stride" &&
-        pf_policy != "ghb"    && pf_policy != "none") {
-        panic("Unrecognized form of a prefetcher: %s, try using"
-              "['none','stride','tagged','ghb']\n", pf_policy);
+
+    if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
+        prefetch_policy == Enums::ghb) {
+
+        if (!prefetch_miss && !prefetch_access)
+            warn("With this prefetcher you should chose a prefetch"
+                 " stream (miss or access)\nNo Prefetching will occur\n");
+
+        if (prefetch_miss && prefetch_access)
+            panic("Can't do prefetches from both miss and access stream");
     }
 
 #if defined(USE_CACHE_IIC)
@@ -367,8 +279,3 @@ CREATE_SIM_OBJECT(BaseCache)
     BUILD_CACHES;
     return NULL;
 }
-
-REGISTER_SIM_OBJECT("BaseCache", BaseCache)
-
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 3fcaec4fa..a65c44f22 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -40,4 +40,3 @@ Source('split_lru.cc')
 
 SimObject('Repl.py')
 Source('repl/gen.cc')
-Source('repl/repl.cc')
diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/repl/gen.cc
index ec1c2aaf3..7d1566300 100644
--- a/src/mem/cache/tags/repl/gen.cc
+++ b/src/mem/cache/tags/repl/gen.cc
@@ -39,7 +39,7 @@
 #include "base/misc.hh"
 #include "mem/cache/tags/iic.hh"
 #include "mem/cache/tags/repl/gen.hh"
-#include "sim/builder.hh"
+#include "params/GenRepl.hh"
 #include "sim/host.hh"
 
 using namespace std;
@@ -247,31 +247,8 @@ GenRepl::findTagPtr(unsigned long index)
     return false;
 }
 
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-    Param<int> num_pools;
-    Param<int> fresh_res;
-    Param<int> pool_res;
-
-END_DECLARE_SIM_OBJECT_PARAMS(GenRepl)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-    INIT_PARAM(num_pools, "capacity in bytes"),
-    INIT_PARAM(fresh_res, "associativity"),
-    INIT_PARAM(pool_res, "block size in bytes")
-
-END_INIT_SIM_OBJECT_PARAMS(GenRepl)
-
-
-CREATE_SIM_OBJECT(GenRepl)
+GenRepl *
+GenReplParams::create()
 {
-    return new GenRepl(getInstanceName(), num_pools, fresh_res, pool_res);
+    return new GenRepl(name, num_pools, fresh_res, pool_res);
 }
-
-REGISTER_SIM_OBJECT("GenRepl", GenRepl)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
diff --git a/src/mem/dram.cc b/src/mem/dram.cc
index 394c70db6..75146f9ed 100644
--- a/src/mem/dram.cc
+++ b/src/mem/dram.cc
@@ -99,11 +99,10 @@ Kluwer Academic, pages 291-310, March, 2000.
  * Definition of a DRAM like main memory.
  */
 
+#include <cstdlib>
+#include <string>
 
 #include "mem/dram.hh"
-#include "sim/builder.hh"
-#include <stdlib.h>
-#include <string>
 
 extern int maxThreadsPerCPU;
 
@@ -174,7 +173,7 @@ extern int maxThreadsPerCPU;
 
 
 
-DRAMMemory::DRAMMemory(Params *p)
+DRAMMemory::DRAMMemory(const Params *p)
     : PhysicalMemory(p), cpu_ratio(p->cpu_ratio), bus_width(p->bus_width),
       mem_type(p->mem_type), mem_actpolicy(p->mem_actpolicy),
       memctrladdr_type(p->memctrladdr_type), act_lat(p->act_lat),
@@ -197,7 +196,7 @@ DRAMMemory::DRAMMemory(Params *p)
       memctrlpipe_enable(false), time_last_access(0)
 {
     warn("This DRAM module has not been tested with the new memory system at all!");
-        bank_size = (params()->addrRange.size() + 1) / num_banks;
+        bank_size = (p->range.size() + 1) / num_banks;
         num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */
         active_row = new int[num_banks];
         last_bank = num_banks+1;
@@ -2666,81 +2665,8 @@ else
 return precharge;
 }
 
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    Param<std::string> file;
-    Param<Range<Addr> > range;
-    Param<Tick> latency;
-    /* additional params for dram protocol*/
-    Param<int> cpu_ratio;
-    Param<std::string> mem_type;
-    Param<std::string> mem_actpolicy;
-    Param<std::string> memctrladdr_type;
-    Param<int> bus_width;
-    Param<int> act_lat;
-    Param<int> cas_lat;
-    Param<int> war_lat;
-    Param<int> pre_lat;
-    Param<int> dpl_lat;
-    Param<int> trc_lat;
-    Param<int> num_banks;
-    Param<int> num_cpus;
-
-END_DECLARE_SIM_OBJECT_PARAMS(DRAMMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-    INIT_PARAM_DFLT(file, "memory mapped file", ""),
-    INIT_PARAM(range, "Device Address Range"),
-    INIT_PARAM(latency, "Memory access latency"),
-
-    /* additional params for dram protocol*/
-    INIT_PARAM_DFLT(cpu_ratio,"ratio between CPU speed and memory bus speed",5),
-    INIT_PARAM_DFLT(mem_type,"type of DRAM","SDRAM"),
-    INIT_PARAM_DFLT(mem_actpolicy,"open / closed page policy","open"),
-    INIT_PARAM_DFLT(memctrladdr_type,"interleaved or direct mapping","interleaved"),
-    INIT_PARAM_DFLT(bus_width,"memory access bus width",16),
-    INIT_PARAM_DFLT(act_lat,"RAS to CAS delay",2),
-    INIT_PARAM_DFLT(cas_lat,"CAS delay",1),
-    INIT_PARAM_DFLT(war_lat,"write after read delay",2),
-    INIT_PARAM_DFLT(pre_lat,"precharge delay",2),
-    INIT_PARAM_DFLT(dpl_lat,"data in to precharge delay",2),
-    INIT_PARAM_DFLT(trc_lat,"row cycle delay",6),
-    INIT_PARAM_DFLT(num_banks,"Number of Banks",4),
-    INIT_PARAM_DFLT(num_cpus,"Number of CPUs connected to DRAM",4)
-
-END_INIT_SIM_OBJECT_PARAMS(DRAMMemory)
-
-CREATE_SIM_OBJECT(DRAMMemory)
+DRAMMemory *
+DRAMMemoryParams::create()
 {
-    DRAMMemory::Params *p = new DRAMMemory::Params;
-    p->name = getInstanceName();
-    p->addrRange = range;
-    p->latency = latency;
-
-    /* additional params for dram */
-    p->cpu_ratio = cpu_ratio;
-    p->bus_width = bus_width;
-    p->mem_type = mem_type;
-    p->mem_actpolicy = mem_actpolicy;
-    p->memctrladdr_type = memctrladdr_type;
-    p->act_lat = act_lat;
-    p->cas_lat = cas_lat;
-    p->war_lat = war_lat;
-    p->pre_lat = pre_lat;
-    p->dpl_lat = dpl_lat;
-    p->trc_lat = trc_lat;
-    p->num_banks = num_banks;
-    p->num_cpus = num_cpus;
-
-    return new DRAMMemory(p);
+    return new DRAMMemory(this);
 }
-
-REGISTER_SIM_OBJECT("DRAMMemory", DRAMMemory)
-
-#endif // DOXYGEN_SHOULD_SKIP_THIS
-
-
diff --git a/src/mem/dram.hh b/src/mem/dram.hh
index 9d2f60ee8..352ca96ae 100644
--- a/src/mem/dram.hh
+++ b/src/mem/dram.hh
@@ -38,6 +38,7 @@
 
 #include "base/statistics.hh"
 #include "mem/physical.hh"
+#include "params/DRAMMemory.hh"
 
 class DRAMMemory : public PhysicalMemory
 {
@@ -144,28 +145,16 @@ class DRAMMemory : public PhysicalMemory
     int prechargeBanksAround(int bank);
 
   public:
-    struct Params : public PhysicalMemory::Params
+    typedef DRAMMemoryParams Params;
+    DRAMMemory(const Params *p);
+
+    const Params *
+    params() const
     {
-        /* additional params for dram protocol*/
-        int cpu_ratio;
-        int bus_width;
-
-        std::string mem_type; /* DRDRAM, SDRAM */
-        std::string mem_actpolicy; /* closed, open */
-        std::string memctrladdr_type; /* interleaved, anythingelse */
-
-        int act_lat;
-        int cas_lat;
-        int war_lat;
-        int pre_lat;
-        int dpl_lat;
-        int trc_lat;
-        int num_banks;
-        int num_cpus;
-
-    };
+        return dynamic_cast<const Params *>(_params);
+    }
+
     virtual void regStats();
-    DRAMMemory(Params *p);
 };
 
 #endif// __MEM_DRAM_HH__
diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc
index ef31cf999..b40709eb2 100644
--- a/src/mem/mem_object.cc
+++ b/src/mem/mem_object.cc
@@ -29,16 +29,19 @@
  */
 
 #include "mem/mem_object.hh"
-#include "sim/param.hh"
+
+MemObject::MemObject(const Params *params)
+    : SimObject(params)
+{
+}
 
 MemObject::MemObject(const std::string &name)
     : SimObject(name)
 {
 }
+
 void
 MemObject::deletePortRefs(Port *p)
 {
     panic("This object does not support port deletion\n");
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("MemObject", MemObject)
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
index ec6fa2b2a..79e555cda 100644
--- a/src/mem/mem_object.hh
+++ b/src/mem/mem_object.hh
@@ -36,8 +36,9 @@
 #ifndef __MEM_MEM_OBJECT_HH__
 #define __MEM_MEM_OBJECT_HH__
 
-#include "sim/sim_object.hh"
 #include "mem/port.hh"
+#include "params/MemObject.hh"
+#include "sim/sim_object.hh"
 
 /**
  * The base MemoryObject class, allows for an accesor function to a
@@ -46,8 +47,16 @@
 class MemObject : public SimObject
 {
   public:
+    typedef MemObjectParams Params;
+    MemObject(const Params *params);
     MemObject(const std::string &name);
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
   public:
     /** Additional function to return the Port of a memory object. */
     virtual Port *getPort(const std::string &if_name, int idx = -1) = 0;
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index b29a07078..a00d743cd 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -43,7 +43,6 @@
 #include "base/intmath.hh"
 #include "base/trace.hh"
 #include "mem/page_table.hh"
-#include "sim/builder.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 2742eca51..b96fb8a56 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -44,23 +44,21 @@
 #include "config/full_system.hh"
 #include "mem/packet_access.hh"
 #include "mem/physical.hh"
-#include "sim/builder.hh"
 #include "sim/eventq.hh"
 #include "sim/host.hh"
 
 using namespace std;
 using namespace TheISA;
 
-PhysicalMemory::PhysicalMemory(Params *p)
-    : MemObject(p->name), pmemAddr(NULL), lat(p->latency), _params(p)
+PhysicalMemory::PhysicalMemory(const Params *p)
+    : MemObject(p), pmemAddr(NULL), lat(p->latency)
 {
-    if (params()->addrRange.size() % TheISA::PageBytes != 0)
+    if (params()->range.size() % TheISA::PageBytes != 0)
         panic("Memory Size not divisible by page size\n");
 
     int map_flags = MAP_ANON | MAP_PRIVATE;
-    pmemAddr =
-        (uint8_t *)mmap(NULL, params()->addrRange.size(),
-                        PROT_READ | PROT_WRITE, map_flags, -1, 0);
+    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
+                               PROT_READ | PROT_WRITE, map_flags, -1, 0);
 
     if (pmemAddr == (void *)MAP_FAILED) {
         perror("mmap");
@@ -68,8 +66,8 @@ PhysicalMemory::PhysicalMemory(Params *p)
     }
 
     //If requested, initialize all the memory to 0
-    if(params()->zero)
-        memset(pmemAddr, 0, params()->addrRange.size());
+    if (p->zero)
+        memset(pmemAddr, 0, p->range.size());
 
     pagePtr = 0;
 }
@@ -90,7 +88,7 @@ PhysicalMemory::init()
 PhysicalMemory::~PhysicalMemory()
 {
     if (pmemAddr)
-        munmap((char*)pmemAddr, params()->addrRange.size());
+        munmap((char*)pmemAddr, params()->range.size());
     //Remove memPorts?
 }
 
@@ -384,7 +382,7 @@ PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop)
 {
     snoop = false;
     resp.clear();
-    resp.push_back(RangeSize(start(), params()->addrRange.size()));
+    resp.push_back(RangeSize(start(), params()->range.size()));
 }
 
 int
@@ -446,7 +444,8 @@ PhysicalMemory::serialize(ostream &os)
         fatal("Insufficient memory to allocate compression state for %s\n",
                 filename);
 
-    if (gzwrite(compressedMem, pmemAddr, params()->addrRange.size()) != params()->addrRange.size()) {
+    if (gzwrite(compressedMem, pmemAddr, params()->range.size()) !=
+        params()->range.size()) {
         fatal("Write failed on physical memory checkpoint file '%s'\n",
               filename);
     }
@@ -488,10 +487,10 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
     // unmap file that was mmaped in the constructor
     // This is done here to make sure that gzip and open don't muck with our
     // nice large space of memory before we reallocate it
-    munmap((char*)pmemAddr, params()->addrRange.size());
+    munmap((char*)pmemAddr, params()->range.size());
 
-    pmemAddr = (uint8_t *)mmap(NULL, params()->addrRange.size(), PROT_READ | PROT_WRITE,
-                                MAP_ANON | MAP_PRIVATE, -1, 0);
+    pmemAddr = (uint8_t *)mmap(NULL, params()->range.size(),
+        PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
 
     if (pmemAddr == (void *)MAP_FAILED) {
         perror("mmap");
@@ -504,12 +503,14 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
         fatal("Unable to malloc memory to read file %s\n", filename);
 
     /* Only copy bytes that are non-zero, so we don't give the VM system hell */
-    while (curSize < params()->addrRange.size()) {
+    while (curSize < params()->range.size()) {
         bytesRead = gzread(compressedMem, tempPage, chunkSize);
-        if (bytesRead != chunkSize && bytesRead != params()->addrRange.size() - curSize)
+        if (bytesRead != chunkSize &&
+            bytesRead != params()->range.size() - curSize)
             fatal("Read failed on physical memory checkpoint file '%s'"
                   " got %d bytes, expected %d or %d bytes\n",
-                  filename, bytesRead, chunkSize, params()->addrRange.size()-curSize);
+                  filename, bytesRead, chunkSize,
+                  params()->range.size() - curSize);
 
         assert(bytesRead % sizeof(long) == 0);
 
@@ -531,33 +532,8 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
 
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-    Param<string> file;
-    Param<Range<Addr> > range;
-    Param<Tick> latency;
-    Param<bool> zero;
-
-END_DECLARE_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-    INIT_PARAM_DFLT(file, "memory mapped file", ""),
-    INIT_PARAM(range, "Device Address Range"),
-    INIT_PARAM(latency, "Memory access latency"),
-    INIT_PARAM(zero, "Zero initialize memory")
-
-END_INIT_SIM_OBJECT_PARAMS(PhysicalMemory)
-
-CREATE_SIM_OBJECT(PhysicalMemory)
+PhysicalMemory *
+PhysicalMemoryParams::create()
 {
-    PhysicalMemory::Params *p = new PhysicalMemory::Params;
-    p->name = getInstanceName();
-    p->addrRange = range;
-    p->latency = latency;
-    p->zero = zero;
-    return new PhysicalMemory(p);
+    return new PhysicalMemory(this);
 }
-
-REGISTER_SIM_OBJECT("PhysicalMemory", PhysicalMemory)
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index 8b13d32c1..b06cc90f8 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -34,13 +34,15 @@
 #ifndef __PHYSICAL_MEMORY_HH__
 #define __PHYSICAL_MEMORY_HH__
 
+#include <map>
+#include <string>
+
 #include "base/range.hh"
 #include "mem/mem_object.hh"
 #include "mem/packet.hh"
 #include "mem/tport.hh"
+#include "params/PhysicalMemory.hh"
 #include "sim/eventq.hh"
-#include <map>
-#include <string>
 
 //
 // Functional model for a contiguous block of physical memory. (i.e. RAM)
@@ -149,25 +151,20 @@ class PhysicalMemory : public MemObject
 
   public:
     Addr new_page();
-    uint64_t size() { return params()->addrRange.size(); }
-    uint64_t start() { return params()->addrRange.start; }
-
-    struct Params
-    {
-        std::string name;
-        Range<Addr> addrRange;
-        Tick latency;
-        bool zero;
-    };
-
-  protected:
-    Params *_params;
+    uint64_t size() { return params()->range.size(); }
+    uint64_t start() { return params()->range.start; }
 
   public:
-    const Params *params() const { return _params; }
-    PhysicalMemory(Params *p);
+    typedef PhysicalMemoryParams Params;
+    PhysicalMemory(const Params *p);
     virtual ~PhysicalMemory();
 
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
   public:
     int deviceBlockSize();
     void getAddressRanges(AddrRangeList &resp, bool &snoop);
diff --git a/src/python/SConscript b/src/python/SConscript
index 66b852d25..f1b6a393f 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -29,10 +29,8 @@
 # Authors: Steve Reinhardt
 #          Nathan Binkert
 
-import os
 Import('*')
 
-Source('swig/init.cc')
 Source('swig/pyevent.cc')
 Source('swig/pyobject.cc')
 
@@ -45,13 +43,12 @@ PySource('m5', 'm5/main.py')
 PySource('m5', 'm5/multidict.py')
 PySource('m5', 'm5/params.py')
 PySource('m5', 'm5/proxy.py')
+PySource('m5', 'm5/simulate.py')
 PySource('m5', 'm5/smartdict.py')
 PySource('m5', 'm5/stats.py')
 PySource('m5', 'm5/ticks.py')
 PySource('m5', 'm5/util.py')
 
-PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py'))
-
 SwigSource('m5.internal', 'swig/core.i')
 SwigSource('m5.internal', 'swig/debug.i')
 SwigSource('m5.internal', 'swig/event.i')
diff --git a/src/python/generate.py b/src/python/generate.py
new file mode 100644
index 000000000..6a09b8106
--- /dev/null
+++ b/src/python/generate.py
@@ -0,0 +1,324 @@
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import imp
+import py_compile
+import sys
+import zipfile
+
+from os.path import basename
+from os.path import exists
+
+class DictImporter(object):
+    '''This importer takes a dictionary of arbitrary module names that
+    map to arbitrary filenames.'''
+    def __init__(self, modules, build_env):
+        self.modules = modules
+        self.installed = set()
+        self.build_env = build_env
+
+    def __del__(self):
+        self.unload()
+
+    def unload(self):
+        for module in self.installed:
+            del sys.modules[module]
+
+    def find_module(self, fullname, path):
+        if fullname == '__scons':
+            return self
+
+        if fullname == 'm5.objects':
+            return self
+
+        if fullname.startswith('m5.internal'):
+            return None
+
+        if fullname in self.modules and exists(self.modules[fullname]):
+            return self
+
+        return None
+
+    def load_module(self, fullname):
+        mod = imp.new_module(fullname)
+        sys.modules[fullname] = mod
+        self.installed.add(fullname)
+
+        mod.__loader__ = self
+        if fullname == 'm5.objects':
+            mod.__path__ = fullname.split('.')
+            return mod
+
+        if fullname == '__scons':
+            mod.__dict__['m5_build_env'] = self.build_env
+            return mod
+
+        srcfile = self.modules[fullname]
+        if basename(srcfile) == '__init__.py':
+            mod.__path__ = fullname.split('.')
+        mod.__file__ = srcfile
+
+        exec file(srcfile, 'r') in mod.__dict__
+
+        return mod
+
+class ordered_dict(dict):
+    def keys(self):
+        keys = super(ordered_dict, self).keys()
+        keys.sort()
+        return keys
+
+    def values(self):
+        return [ self[key] for key in self.keys() ]
+
+    def items(self):
+        return [ (key,self[key]) for key in self.keys() ]
+
+    def iterkeys(self):
+        for key in self.keys():
+            yield key
+
+    def itervalues(self):
+        for value in self.values():
+            yield value
+
+    def iteritems(self):
+        for key,value in self.items():
+            yield key, value
+
+class Generate(object):
+    def __init__(self, py_sources, sim_objects, build_env):
+        self.py_sources = py_sources
+        self.py_modules = {}
+        for source in py_sources:
+            self.py_modules[source.modpath]  = source.srcpath
+
+        importer = DictImporter(self.py_modules, build_env)
+
+        # install the python importer so we can grab stuff from the source
+        # tree itself.
+        sys.meta_path[0:0] = [ importer ]
+
+        import m5
+        self.m5 = m5
+
+        # import all sim objects so we can populate the all_objects list
+        # make sure that we're working with a list, then let's sort it
+        sim_objects = list(sim_objects)
+        sim_objects.sort()
+        for simobj in sim_objects:
+            exec('from m5.objects import %s' % simobj)
+
+        # we need to unload all of the currently imported modules so that they
+        # will be re-imported the next time the sconscript is run
+        importer.unload()
+        sys.meta_path.remove(importer)
+
+        self.sim_objects = m5.SimObject.allClasses
+        self.enums = m5.params.allEnums
+
+        self.params = {}
+        for name,obj in self.sim_objects.iteritems():
+            for param in obj._params.local.values():
+                if not hasattr(param, 'swig_decl'):
+                    continue
+                pname = param.ptype_str
+                if pname not in self.params:
+                    self.params[pname] = param
+
+    def createSimObjectParam(self, target, source, env):
+        assert len(target) == 1 and len(source) == 1
+
+        hh_file = file(target[0].abspath, 'w')
+        name = str(source[0].get_contents())
+        obj = self.sim_objects[name]
+
+        print >>hh_file, obj.cxx_decl()
+
+    # Generate Python file containing a dict specifying the current
+    # build_env flags.
+    def makeDefinesPyFile(self, target, source, env):
+        f = file(str(target[0]), 'w')
+        print >>f, "m5_build_env = ", source[0]
+        f.close()
+
+    # Generate python file containing info about the M5 source code
+    def makeInfoPyFile(self, target, source, env):
+        f = file(str(target[0]), 'w')
+        for src in source:
+            data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
+            print >>f, "%s = %s" % (src, repr(data))
+        f.close()
+
+    # Generate the __init__.py file for m5.objects
+    def makeObjectsInitFile(self, target, source, env):
+        f = file(str(target[0]), 'w')
+        print >>f, 'from params import *'
+        print >>f, 'from m5.SimObject import *'
+        for module in source:
+            print >>f, 'from %s import *' % module.get_contents()
+        f.close()
+
+    def createSwigParam(self, target, source, env):
+        assert len(target) == 1 and len(source) == 1
+
+        i_file = file(target[0].abspath, 'w')
+        name = str(source[0].get_contents())
+        param = self.params[name]
+
+        for line in param.swig_decl():
+            print >>i_file, line
+
+    def createEnumStrings(self, target, source, env):
+        assert len(target) == 1 and len(source) == 1
+
+        cc_file = file(target[0].abspath, 'w')
+        name = str(source[0].get_contents())
+        obj = self.enums[name]
+
+        print >>cc_file, obj.cxx_def()
+        cc_file.close()
+
+    def createEnumParam(self, target, source, env):
+        assert len(target) == 1 and len(source) == 1
+
+        hh_file = file(target[0].abspath, 'w')
+        name = str(source[0].get_contents())
+        obj = self.enums[name]
+
+        print >>hh_file, obj.cxx_decl()
+
+    def buildParams(self, target, source, env):
+        names = [ s.get_contents() for s in source ]
+        objs = [ self.sim_objects[name] for name in names ]
+        out = file(target[0].abspath, 'w')
+
+        ordered_objs = []
+        obj_seen = set()
+        def order_obj(obj):
+            name = str(obj)
+            if name in obj_seen:
+                return
+
+            obj_seen.add(name)
+            if str(obj) != 'SimObject':
+                order_obj(obj.__bases__[0])
+
+            ordered_objs.append(obj)
+
+        for obj in objs:
+            order_obj(obj)
+
+        enums = set()
+        predecls = []
+        pd_seen = set()
+
+        def add_pds(*pds):
+            for pd in pds:
+                if pd not in pd_seen:
+                    predecls.append(pd)
+                    pd_seen.add(pd)
+
+        for obj in ordered_objs:
+            params = obj._params.local.values()
+            for param in params:
+                ptype = param.ptype
+                if issubclass(ptype, self.m5.params.Enum):
+                    if ptype not in enums:
+                        enums.add(ptype)
+                pds = param.swig_predecls()
+                if isinstance(pds, (list, tuple)):
+                    add_pds(*pds)
+                else:
+                    add_pds(pds)
+
+        print >>out, '%module params'
+
+        print >>out, '%{'
+        for obj in ordered_objs:
+            print >>out, '#include "params/%s.hh"' % obj
+        print >>out, '%}'
+
+        for pd in predecls:
+            print >>out, pd
+
+        enums = list(enums)
+        enums.sort()
+        for enum in enums:
+            print >>out, '%%import "enums/%s.hh"' % enum.__name__
+        print >>out
+
+        for obj in ordered_objs:
+            code = 'class %s ' % obj.cxx_class
+            if str(obj) != 'SimObject':
+                code += ': public %s ' % obj.__bases__[0]
+            code += '{};'
+
+            klass = obj.cxx_class;
+            if hasattr(obj, 'cxx_namespace'):
+                code = 'namespace %s { %s }' % (obj.cxx_namespace, code)
+                klass = '%s::%s' % (obj.cxx_namespace, klass)
+
+            print >>out, '%%ignore %s;' % klass
+            print >>out, code
+
+        for obj in ordered_objs:
+            print >>out, '%%include "params/%s.hh"' % obj
+
+    def makeSwigInit(self, target, source, env):
+        f = file(str(target[0]), 'w')
+        print >>f, 'extern "C" {'
+        for module in source:
+            print >>f, '    void init_%s();' % module.get_contents()
+        print >>f, '}'
+        print >>f, 'void init_swig() {'
+        for module in source:
+            print >>f, '    init_%s();' % module.get_contents()
+        print >>f, '}'
+        f.close()
+
+    def compilePyFile(self, target, source, env):
+        '''Action function to compile a .py into a .pyc'''
+        py_compile.compile(str(source[0]), str(target[0]))
+
+    def buildPyZip(self, target, source, env):
+        '''Action function to build the zip archive.  Uses the
+        PyZipFile module included in the standard Python library.'''
+
+        py_compiled = {}
+        for s in self.py_sources:
+            compname = str(s.compiled)
+            assert compname not in py_compiled
+            py_compiled[compname] = s
+
+        zf = zipfile.ZipFile(str(target[0]), 'w')
+        for s in source:
+            zipname = str(s)
+            arcname = py_compiled[zipname].arcname
+            zf.write(zipname, arcname)
+        zf.close()
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index f87e13732..1e7d289e2 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -29,6 +29,8 @@
 
 import sys, types
 
+import proxy
+import m5
 from util import *
 from multidict import multidict
 
@@ -61,7 +63,7 @@ def isSimObjectOrSequence(value):
 from params import *
 # There are a few things we need that aren't in params.__all__ since
 # normal users don't need them
-from params import ParamDesc, isNullPointer, SimObjVector
+from params import ParamDesc, VectorParamDesc, isNullPointer, SimObjVector
 
 noDot = False
 try:
@@ -109,6 +111,9 @@ except:
 #
 #####################################################################
 
+# list of all SimObject classes
+allClasses = {}
+
 # dict to look up SimObjects based on path
 instanceDict = {}
 
@@ -119,12 +124,14 @@ instanceDict = {}
 class MetaSimObject(type):
     # Attributes that can be set only at initialization time
     init_keywords = { 'abstract' : types.BooleanType,
+                      'cxx_namespace' : types.StringType,
+                      'cxx_class' : types.StringType,
+                      'cxx_type' : types.StringType,
+                      'cxx_predecls' : types.ListType,
+                      'swig_predecls' : types.ListType,
                       'type' : types.StringType }
     # Attributes that can be set any time
-    keywords = { 'check' : types.FunctionType,
-                 'cxx_type' : types.StringType,
-                 'cxx_predecls' : types.ListType,
-                 'swig_predecls' : types.ListType }
+    keywords = { 'check' : types.FunctionType }
 
     # __new__ is called before __init__, and is where the statements
     # in the body of the class definition get loaded into the class's
@@ -132,6 +139,8 @@ class MetaSimObject(type):
     # and only allow "private" attributes to be passed to the base
     # __new__ (starting with underscore).
     def __new__(mcls, name, bases, dict):
+        assert name not in allClasses
+
         # Copy "private" attributes, functions, and classes to the
         # official dict.  Everything else goes in _init_dict to be
         # filtered in __init__.
@@ -144,8 +153,13 @@ class MetaSimObject(type):
             else:
                 # must be a param/port setting
                 value_dict[key] = val
+        if 'abstract' not in value_dict:
+            value_dict['abstract'] = False
         cls_dict['_value_dict'] = value_dict
-        return super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
+        cls = super(MetaSimObject, mcls).__new__(mcls, name, bases, cls_dict)
+        if 'type' in value_dict:
+            allClasses[name] = cls
+        return cls
 
     # subclass initialization
     def __init__(cls, name, bases, dict):
@@ -183,6 +197,34 @@ class MetaSimObject(type):
             # mark base as having been subclassed
             base._instantiated = True
 
+        # default keyword values
+        if 'type' in cls._value_dict:
+            _type = cls._value_dict['type']
+            if 'cxx_class' not in cls._value_dict:
+                cls._value_dict['cxx_class'] = _type
+
+            namespace = cls._value_dict.get('cxx_namespace', None)
+
+            _cxx_class = cls._value_dict['cxx_class']
+            if 'cxx_type' not in cls._value_dict:
+                t = _cxx_class + '*'
+                if namespace:
+                    t = '%s::%s' % (namespace, t)
+                cls._value_dict['cxx_type'] = t
+            if 'cxx_predecls' not in cls._value_dict:
+                # A forward class declaration is sufficient since we are
+                # just declaring a pointer.
+                decl = 'class %s;' % _cxx_class
+                if namespace:
+                    decl = 'namespace %s { %s }' % (namespace, decl)
+                cls._value_dict['cxx_predecls'] = [decl]
+
+            if 'swig_predecls' not in cls._value_dict:
+                # A forward class declaration is sufficient since we are
+                # just declaring a pointer.
+                cls._value_dict['swig_predecls'] = \
+                    cls._value_dict['cxx_predecls']
+
         # Now process the _value_dict items.  They could be defining
         # new (or overriding existing) parameters or ports, setting
         # class keywords (e.g., 'abstract'), or setting parameter
@@ -207,12 +249,6 @@ class MetaSimObject(type):
             else:
                 setattr(cls, key, val)
 
-        cls.cxx_type = cls.type + '*'
-        # A forward class declaration is sufficient since we are just
-        # declaring a pointer.
-        cls.cxx_predecls = ['class %s;' % cls.type]
-        cls.swig_predecls = cls.cxx_predecls
-
     def _set_keyword(cls, keyword, val, kwtype):
         if not isinstance(val, kwtype):
             raise TypeError, 'keyword %s has bad type %s (expecting %s)' % \
@@ -310,18 +346,19 @@ class MetaSimObject(type):
         return cls.__name__
 
     def cxx_decl(cls):
-        code = "#ifndef __PARAMS__%s\n#define __PARAMS__%s\n\n" % (cls, cls)
-
         if str(cls) != 'SimObject':
             base = cls.__bases__[0].type
         else:
             base = None
 
+        code = "#ifndef __PARAMS__%s\n" % cls
+        code += "#define __PARAMS__%s\n\n" % cls
+
         # The 'dict' attribute restricts us to the params declared in
         # the object itself, not including inherited params (which
         # will also be inherited from the base class's param struct
         # here).
-        params = cls._params.dict.values()
+        params = cls._params.local.values()
         try:
             ptypes = [p.ptype for p in params]
         except:
@@ -330,9 +367,10 @@ class MetaSimObject(type):
             raise
 
         # get a list of lists of predeclaration lines
-        predecls = [p.cxx_predecls() for p in params]
-        # flatten
-        predecls = reduce(lambda x,y:x+y, predecls, [])
+        predecls = []
+        predecls.extend(cls.cxx_predecls)
+        for p in params:
+            predecls.extend(p.cxx_predecls())
         # remove redundant lines
         predecls2 = []
         for pd in predecls:
@@ -345,17 +383,21 @@ class MetaSimObject(type):
         if base:
             code += '#include "params/%s.hh"\n\n' % base
 
-        # Generate declarations for locally defined enumerations.
-        enum_ptypes = [t for t in ptypes if issubclass(t, Enum)]
-        if enum_ptypes:
-            code += "\n".join([t.cxx_decl() for t in enum_ptypes])
-            code += "\n\n"
+        for ptype in ptypes:
+            if issubclass(ptype, Enum):
+                code += '#include "enums/%s.hh"\n' % ptype.__name__
+                code += "\n\n"
 
         # now generate the actual param struct
         code += "struct %sParams" % cls
         if base:
             code += " : public %sParams" % base
-        code += " {\n"
+        code += "\n{\n"
+        if cls == SimObject:
+            code += "    virtual ~%sParams() {}\n" % cls
+        if not hasattr(cls, 'abstract') or not cls.abstract:
+            if 'type' in cls.__dict__:
+                code += "    %s create();\n" % cls.cxx_type
         decls = [p.cxx_decl() for p in params]
         decls.sort()
         code += "".join(["    %s\n" % d for d in decls])
@@ -365,12 +407,34 @@ class MetaSimObject(type):
         code += "\n#endif\n"
         return code
 
+    def cxx_type_decl(cls):
+        if str(cls) != 'SimObject':
+            base = cls.__bases__[0]
+        else:
+            base = None
+
+        code = ''
+
+        if base:
+            code += '#include "%s_type.h"\n' % base
+
+        # now generate dummy code for inheritance
+        code += "struct %s" % cls.cxx_class
+        if base:
+            code += " : public %s" % base.cxx_class
+        code += "\n{};\n"
+
+        return code
+
     def swig_decl(cls):
+        code = '%%module %s\n' % cls
 
-        code = '%%module %sParams\n' % cls
+        code += '%{\n'
+        code += '#include "params/%s.hh"\n' % cls
+        code += '%}\n\n'
 
         if str(cls) != 'SimObject':
-            base = cls.__bases__[0].type
+            base = cls.__bases__[0]
         else:
             base = None
 
@@ -378,11 +442,12 @@ class MetaSimObject(type):
         # the object itself, not including inherited params (which
         # will also be inherited from the base class's param struct
         # here).
-        params = cls._params.dict.values()
+        params = cls._params.local.values()
         ptypes = [p.ptype for p in params]
 
         # get a list of lists of predeclaration lines
-        predecls = [p.swig_predecls() for p in params]
+        predecls = []
+        predecls.extend([ p.swig_predecls() for p in params ])
         # flatten
         predecls = reduce(lambda x,y:x+y, predecls, [])
         # remove redundant lines
@@ -395,11 +460,14 @@ class MetaSimObject(type):
         code += "\n\n";
 
         if base:
-            code += '%%import "python/m5/swig/%sParams.i"\n\n' % base
+            code += '%%import "params/%s.i"\n\n' % base
 
-        code += '%{\n'
-        code += '#include "params/%s.hh"\n' % cls
-        code += '%}\n\n'
+        for ptype in ptypes:
+            if issubclass(ptype, Enum):
+                code += '%%import "enums/%s.hh"\n' % ptype.__name__
+                code += "\n\n"
+
+        code += '%%import "params/%s_type.hh"\n\n' % cls
         code += '%%include "params/%s.hh"\n\n' % cls
 
         return code
@@ -412,6 +480,7 @@ class SimObject(object):
     # get this metaclass.
     __metaclass__ = MetaSimObject
     type = 'SimObject'
+    abstract = True
 
     name = Param.String("Object name")
 
@@ -440,6 +509,7 @@ class SimObject(object):
         self._parent = None
         self._children = {}
         self._ccObject = None  # pointer to C++ object
+        self._ccParams = None
         self._instantiated = False # really "cloned"
 
         # Inherit parameter values from class using multidict so
@@ -577,8 +647,11 @@ class SimObject(object):
             value._maybe_set_parent(self, attr)
         elif isSimObjectSequence(value):
             value = SimObjVector(value)
-            [v._maybe_set_parent(self, "%s%d" % (attr, i))
-             for i,v in enumerate(value)]
+            if len(value) == 1:
+                value[0]._maybe_set_parent(self, attr)
+            else:
+                for i,v in enumerate(value):
+                    v._maybe_set_parent(self, "%s%d" % (attr, i))
 
         self._values[attr] = value
 
@@ -680,25 +753,66 @@ class SimObject(object):
         for child in child_names:
             self._children[child].print_ini()
 
-    # Call C++ to create C++ object corresponding to this object and
-    # (recursively) all its children
-    def createCCObject(self):
-        self.getCCObject() # force creation
-        for child in self._children.itervalues():
-            child.createCCObject()
+    def getCCParams(self):
+        if self._ccParams:
+            return self._ccParams
+
+        cc_params_struct = eval('m5.objects.params.%sParams' % self.type)
+        cc_params = cc_params_struct()
+        cc_params.object = self
+        cc_params.name = str(self)
+
+        param_names = self._params.keys()
+        param_names.sort()
+        for param in param_names:
+            value = self._values.get(param)
+            if value is None:
+                continue
+
+            value = value.getValue()
+            if isinstance(self._params[param], VectorParamDesc):
+                assert isinstance(value, list)
+                vec = getattr(cc_params, param)
+                assert not len(vec)
+                for v in value:
+                    vec.append(v)
+            else:
+                setattr(cc_params, param, value)
+
+        port_names = self._ports.keys()
+        port_names.sort()
+        for port_name in port_names:
+            port = self._port_refs.get(port_name, None)
+            if port != None:
+                setattr(cc_params, port_name, port)
+        self._ccParams = cc_params
+        return self._ccParams
 
     # Get C++ object corresponding to this object, calling C++ if
     # necessary to construct it.  Does *not* recursively create
     # children.
     def getCCObject(self):
+        import internal
+        params = self.getCCParams()
         if not self._ccObject:
             self._ccObject = -1 # flag to catch cycles in recursion
-            self._ccObject = internal.sim_object.createSimObject(self.path())
+            self._ccObject = params.create()
         elif self._ccObject == -1:
             raise RuntimeError, "%s: recursive call to getCCObject()" \
                   % self.path()
         return self._ccObject
 
+    # Call C++ to create C++ object corresponding to this object and
+    # (recursively) all its children
+    def createCCObject(self):
+        self.getCCParams()
+        self.getCCObject() # force creation
+        for child in self._children.itervalues():
+            child.createCCObject()
+
+    def getValue(self):
+        return self.getCCObject()
+
     # Create C++ port connections corresponding to the connections in
     # _port_refs (& recursively for all children)
     def connectPorts(self):
@@ -730,6 +844,7 @@ class SimObject(object):
         return system_ptr.getMemoryMode()
 
     def changeTiming(self, mode):
+        import internal
         if isinstance(self, m5.objects.System):
             # i don't know if there's a better way to do this - calling
             # setMemoryMode directly from self._ccObject results in calling
@@ -740,6 +855,7 @@ class SimObject(object):
             child.changeTiming(mode)
 
     def takeOverFrom(self, old_cpu):
+        import internal
         cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject)
         self._ccObject.takeOverFrom(cpu_ptr)
 
@@ -794,9 +910,4 @@ def resolveSimObject(name):
 # __all__ defines the list of symbols that get exported when
 # 'from config import *' is invoked.  Try to keep this reasonably
 # short to avoid polluting other namespaces.
-__all__ = ['SimObject']
-
-# see comment on imports at end of __init__.py.
-import proxy
-import internal
-import m5
+__all__ = [ 'SimObject' ]
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index a9206a474..36f2eba61 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -27,19 +27,10 @@
 # Authors: Nathan Binkert
 #          Steve Reinhardt
 
-import atexit
 import os
 import sys
 
-# import the SWIG-wrapped main C++ functions
-import internal
-# import a few SWIG-wrapped items (those that are likely to be used
-# directly by user scripts) completely into this module for
-# convenience
-import event
-
-# import the m5 compile options
-import defines
+import smartdict
 
 # define a MaxTick parameter
 MaxTick = 2**63 - 1
@@ -69,178 +60,12 @@ def AddToPath(path):
     sys.path.insert(1, path)
 
 # make a SmartDict out of the build options for our local use
-import smartdict
 build_env = smartdict.SmartDict()
-build_env.update(defines.m5_build_env)
 
 # make a SmartDict out of the OS environment too
 env = smartdict.SmartDict()
 env.update(os.environ)
 
-# The final hook to generate .ini files.  Called from the user script
-# once the config is built.
-def instantiate(root):
-    # we need to fix the global frequency
-    ticks.fixGlobalFrequency()
-
-    root.unproxy_all()
-    # ugly temporary hack to get output to config.ini
-    sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
-    root.print_ini()
-    sys.stdout.close() # close config.ini
-    sys.stdout = sys.__stdout__ # restore to original
-
-    # load config.ini into C++
-    internal.core.loadIniFile(resolveSimObject)
-
-    # Initialize the global statistics
-    internal.stats.initSimStats()
-
-    # Create the C++ sim objects and connect ports
-    root.createCCObject()
-    root.connectPorts()
-
-    # Do a second pass to finish initializing the sim objects
-    internal.sim_object.initAll()
-
-    # Do a third pass to initialize statistics
-    internal.sim_object.regAllStats()
-
-    # Check to make sure that the stats package is properly initialized
-    internal.stats.check()
-
-    # Reset to put the stats in a consistent state.
-    internal.stats.reset()
-
-def doDot(root):
-    dot = pydot.Dot()
-    instance.outputDot(dot)
-    dot.orientation = "portrait"
-    dot.size = "8.5,11"
-    dot.ranksep="equally"
-    dot.rank="samerank"
-    dot.write("config.dot")
-    dot.write_ps("config.ps")
-
-need_resume = []
-need_startup = True
-def simulate(*args, **kwargs):
-    global need_resume, need_startup
-
-    if need_startup:
-        internal.core.SimStartup()
-        need_startup = False
-
-    for root in need_resume:
-        resume(root)
-    need_resume = []
-
-    return internal.event.simulate(*args, **kwargs)
-
-# Export curTick to user script.
-def curTick():
-    return internal.core.cvar.curTick
-
-# Python exit handlers happen in reverse order.  We want to dump stats last.
-atexit.register(internal.stats.dump)
-
-# register our C++ exit callback function with Python
-atexit.register(internal.core.doExitCleanup)
-
-# This loops until all objects have been fully drained.
-def doDrain(root):
-    all_drained = drain(root)
-    while (not all_drained):
-        all_drained = drain(root)
-
-# Tries to drain all objects.  Draining might not be completed unless
-# all objects return that they are drained on the first call.  This is
-# because as objects drain they may cause other objects to no longer
-# be drained.
-def drain(root):
-    all_drained = False
-    drain_event = internal.event.createCountedDrain()
-    unready_objects = root.startDrain(drain_event, True)
-    # If we've got some objects that can't drain immediately, then simulate
-    if unready_objects > 0:
-        drain_event.setCount(unready_objects)
-        simulate()
-    else:
-        all_drained = True
-    internal.event.cleanupCountedDrain(drain_event)
-    return all_drained
-
-def resume(root):
-    root.resume()
-
-def checkpoint(root, dir):
-    if not isinstance(root, objects.Root):
-        raise TypeError, "Checkpoint must be called on a root object."
-    doDrain(root)
-    print "Writing checkpoint"
-    internal.sim_object.serializeAll(dir)
-    resume(root)
-
-def restoreCheckpoint(root, dir):
-    print "Restoring from checkpoint"
-    internal.sim_object.unserializeAll(dir)
-    need_resume.append(root)
-
-def changeToAtomic(system):
-    if not isinstance(system, (objects.Root, objects.System)):
-        raise TypeError, "Parameter of type '%s'.  Must be type %s or %s." % \
-              (type(system), objects.Root, objects.System)
-    if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
-        doDrain(system)
-        print "Changing memory mode to atomic"
-        system.changeTiming(internal.sim_object.SimObject.Atomic)
-
-def changeToTiming(system):
-    if not isinstance(system, (objects.Root, objects.System)):
-        raise TypeError, "Parameter of type '%s'.  Must be type %s or %s." % \
-              (type(system), objects.Root, objects.System)
-
-    if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
-        doDrain(system)
-        print "Changing memory mode to timing"
-        system.changeTiming(internal.sim_object.SimObject.Timing)
-
-def switchCpus(cpuList):
-    print "switching cpus"
-    if not isinstance(cpuList, list):
-        raise RuntimeError, "Must pass a list to this function"
-    for i in cpuList:
-        if not isinstance(i, tuple):
-            raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
-
-    [old_cpus, new_cpus] = zip(*cpuList)
-
-    for cpu in old_cpus:
-        if not isinstance(cpu, objects.BaseCPU):
-            raise TypeError, "%s is not of type BaseCPU" % cpu
-    for cpu in new_cpus:
-        if not isinstance(cpu, objects.BaseCPU):
-            raise TypeError, "%s is not of type BaseCPU" % cpu
-
-    # Drain all of the individual CPUs
-    drain_event = internal.event.createCountedDrain()
-    unready_cpus = 0
-    for old_cpu in old_cpus:
-        unready_cpus += old_cpu.startDrain(drain_event, False)
-    # If we've got some objects that can't drain immediately, then simulate
-    if unready_cpus > 0:
-        drain_event.setCount(unready_cpus)
-        simulate()
-    internal.event.cleanupCountedDrain(drain_event)
-    # Now all of the CPUs are ready to be switched out
-    for old_cpu in old_cpus:
-        old_cpu._ccObject.switchOut()
-    index = 0
-    for new_cpu in new_cpus:
-        new_cpu.takeOverFrom(old_cpus[index])
-        new_cpu._ccObject.resume()
-        index += 1
-
 # Since we have so many mutual imports in this package, we should:
 # 1. Put all intra-package imports at the *bottom* of the file, unless
 #    they're absolutely needed before that (for top-level statements
@@ -250,7 +75,24 @@ def switchCpus(cpuList):
 #    you can get the wrong result if foo is only partially imported
 #    at the point you do that (i.e., because foo is in the middle of
 #    importing *you*).
-from main import options
-import objects
+try:
+    import internal
+    running_m5 = True
+except ImportError:
+    running_m5 = False
+
+if running_m5:
+    from event import *
+    from simulate import *
+    from main import options
+
+if running_m5:
+    import defines
+    build_env.update(defines.m5_build_env)
+else:
+    import __scons
+    build_env.update(__scons.m5_build_env)
+
+import SimObject
 import params
-from SimObject import resolveSimObject
+import objects
diff --git a/src/python/m5/environment.py b/src/python/m5/environment.py
new file mode 100644
index 000000000..bea0bc1d0
--- /dev/null
+++ b/src/python/m5/environment.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+#          Steve Reinhardt
+
+import os
+
+# import the m5 compile options
+import defines
+
+# make a SmartDict out of the build options for our local use
+import smartdict
+build_env = smartdict.SmartDict()
+build_env.update(defines.m5_build_env)
+
+# make a SmartDict out of the OS environment too
+env = smartdict.SmartDict()
+env.update(os.environ)
+
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index 88b162874..3fca4e97a 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -47,6 +47,7 @@
 import copy
 import datetime
 import inspect
+import re
 import sys
 import time
 
@@ -55,6 +56,17 @@ import proxy
 import ticks
 from util import *
 
+import SimObject
+
+def isSimObject(*args, **kwargs):
+    return SimObject.isSimObject(*args, **kwargs)
+
+def isSimObjectSequence(*args, **kwargs):
+    return SimObject.isSimObjectSequence(*args, **kwargs)
+
+def isSimObjectClass(*args, **kwargs):
+    return SimObject.isSimObjectClass(*args, **kwargs)
+
 # Dummy base class to identify types that are legitimate for SimObject
 # parameters.
 class ParamValue(object):
@@ -108,14 +120,15 @@ class ParamDesc(object):
     def __getattr__(self, attr):
         if attr == 'ptype':
             try:
-                ptype = eval(self.ptype_str, objects.__dict__)
+                ptype = SimObject.allClasses[self.ptype_str]
                 if not isinstance(ptype, type):
                     raise NameError
                 self.ptype = ptype
                 return ptype
             except NameError:
-                raise TypeError, \
-                      "Param qualifier '%s' is not a type" % self.ptype_str
+                raise
+                #raise TypeError, \
+                #      "Param qualifier '%s' is not a type" % self.ptype_str
         raise AttributeError, "'%s' object has no attribute '%s'" % \
               (type(self).__name__, attr)
 
@@ -150,6 +163,9 @@ class VectorParamValue(list):
     def ini_str(self):
         return ' '.join([v.ini_str() for v in self])
 
+    def getValue(self):
+        return [ v.getValue() for v in self ]
+
     def unproxy(self, base):
         return [v.unproxy(base) for v in self]
 
@@ -165,20 +181,26 @@ class VectorParamDesc(ParamDesc):
         if isinstance(value, (list, tuple)):
             # list: coerce each element into new list
             tmp_list = [ ParamDesc.convert(self, v) for v in value ]
-            if isSimObjectSequence(tmp_list):
-                return SimObjVector(tmp_list)
-            else:
-                return VectorParamValue(tmp_list)
         else:
-            # singleton: leave it be (could coerce to a single-element
-            # list here, but for some historical reason we don't...
-            return ParamDesc.convert(self, value)
+            # singleton: coerce to a single-element list
+            tmp_list = [ ParamDesc.convert(self, value) ]
 
-    def cxx_predecls(self):
-        return ['#include <vector>'] + self.ptype.cxx_predecls
+        if isSimObjectSequence(tmp_list):
+            return SimObjVector(tmp_list)
+        else:
+            return VectorParamValue(tmp_list)
 
     def swig_predecls(self):
-        return ['%include "std_vector.i"'] + self.ptype.swig_predecls
+        return ['%%include "%s_vptype.i"' % self.ptype_str]
+
+    def swig_decl(self):
+        cxx_type = re.sub('std::', '', self.ptype.cxx_type)
+        vdecl = 'namespace std { %%template(vector_%s) vector< %s >; }' % \
+                (self.ptype_str, cxx_type)
+        return ['%include "std_vector.i"'] + self.ptype.swig_predecls + [vdecl]
+
+    def cxx_predecls(self):
+        return ['#include <vector>'] + self.ptype.cxx_predecls
 
     def cxx_decl(self):
         return 'std::vector< %s > %s;' % (self.ptype.cxx_type, self.name)
@@ -232,7 +254,10 @@ class String(ParamValue,str):
     cxx_predecls = ['#include <string>']
     swig_predecls = ['%include "std_string.i"\n' +
                      '%apply const std::string& {std::string *};']
-    pass
+    swig_predecls = ['%include "std_string.i"' ]
+
+    def getValue(self):
+        return self
 
 # superclass for "numeric" parameter values, to emulate math
 # operations in a type-safe way.  e.g., a Latency times an int returns
@@ -291,7 +316,7 @@ class CheckedIntType(type):
 
         if not cls.swig_predecls:
             # most derived types require this, so we just do it here once
-            cls.swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+            cls.swig_predecls = ['%import "stdint.i"\n' +
                                  '%import "sim/host.hh"']
 
         if not (hasattr(cls, 'min') and hasattr(cls, 'max')):
@@ -328,6 +353,9 @@ class CheckedInt(NumericParamValue):
                   % type(value).__name__
         self._check()
 
+    def getValue(self):
+        return long(self.value)
+
 class Int(CheckedInt):      cxx_type = 'int';      size = 32; unsigned = False
 class Unsigned(CheckedInt): cxx_type = 'unsigned'; size = 32; unsigned = True
 
@@ -350,6 +378,9 @@ class Percent(CheckedInt):  cxx_type = 'int'; min = 0; max = 100
 class Float(ParamValue, float):
     cxx_type = 'double'
 
+    def getValue(self):
+        return float(self.value)
+
 class MemorySize(CheckedInt):
     cxx_type = 'uint64_t'
     size = 64
@@ -374,7 +405,7 @@ class MemorySize32(CheckedInt):
 
 class Addr(CheckedInt):
     cxx_type = 'Addr'
-    cxx_predecls = ['#include "targetarch/isa_traits.hh"']
+    cxx_predecls = ['#include "arch/isa_traits.hh"']
     size = 64
     unsigned = True
     def __init__(self, value):
@@ -443,9 +474,27 @@ class Range(ParamValue):
 
 class AddrRange(Range):
     type = Addr
+    swig_predecls = ['%include "python/swig/range.i"']
+
+    def getValue(self):
+        from m5.objects.params import AddrRange
+
+        value = AddrRange()
+        value.start = long(self.first)
+        value.end = long(self.second)
+        return value
 
 class TickRange(Range):
     type = Tick
+    swig_predecls = ['%include "python/swig/range.i"']
+
+    def getValue(self):
+        from m5.objects.params import TickRange
+
+        value = TickRange()
+        value.start = long(self.first)
+        value.end = long(self.second)
+        return value
 
 # Boolean parameter type.  Python doesn't let you subclass bool, since
 # it doesn't want to let you create multiple instances of True and
@@ -458,6 +507,9 @@ class Bool(ParamValue):
         except TypeError:
             self.value = bool(value)
 
+    def getValue(self):
+        return bool(self.value)
+
     def __str__(self):
         return str(self.value)
 
@@ -489,7 +541,7 @@ def NextEthernetAddr():
 class EthernetAddr(ParamValue):
     cxx_type = 'Net::EthAddr'
     cxx_predecls = ['#include "base/inet.hh"']
-    swig_predecls = ['class Net::EthAddr;']
+    swig_predecls = ['%include "python/swig/inet.i"']
     def __init__(self, value):
         if value == NextEthernetAddr:
             self.value = value
@@ -513,6 +565,10 @@ class EthernetAddr(ParamValue):
             return EthernetAddr(self.value())
         return self
 
+    def getValue(self):
+        from m5.objects.params import EthAddr
+        return EthAddr(self.value)
+
     def ini_str(self):
         return self.value
 
@@ -555,13 +611,40 @@ def parse_time(value):
     raise ValueError, "Could not parse '%s' as a time" % value
 
 class Time(ParamValue):
-    cxx_type = 'time_t'
+    cxx_type = 'tm'
+    cxx_predecls = [ '#include <time.h>' ]
+    swig_predecls = [ '%include "python/swig/time.i"' ]
     def __init__(self, value):
         self.value = parse_time(value)
 
+    def getValue(self):
+        from m5.objects.params import tm
+
+        c_time = tm()
+        py_time = self.value
+
+        # UNIX is years since 1900
+        c_time.tm_year = py_time.tm_year - 1900;
+
+        # Python starts at 1, UNIX starts at 0
+        c_time.tm_mon =  py_time.tm_mon - 1;
+        c_time.tm_mday = py_time.tm_mday;
+        c_time.tm_hour = py_time.tm_hour;
+        c_time.tm_min = py_time.tm_min;
+        c_time.tm_sec = py_time.tm_sec;
+
+        # Python has 0 as Monday, UNIX is 0 as sunday
+        c_time.tm_wday = py_time.tm_wday + 1
+        if c_time.tm_wday > 6:
+            c_time.tm_wday -= 7;
+
+        # Python starts at 1, Unix starts at 0
+        c_time.tm_yday = py_time.tm_yday - 1;
+
+        return c_time
+
     def __str__(self):
-        tm = self.value
-        return ' '.join([ str(tm[i]) for i in xrange(8)])
+        return time.asctime(self.value)
 
     def ini_str(self):
         return str(self)
@@ -580,9 +663,16 @@ class Time(ParamValue):
 # classes (_ListEnum and _DictEnum) to serve as base classes, then
 # derive the new type from the appropriate base class on the fly.
 
-
+allEnums = {}
 # Metaclass for Enum types
 class MetaEnum(type):
+    def __new__(mcls, name, bases, dict):
+        assert name not in allEnums
+
+        cls = super(MetaEnum, mcls).__new__(mcls, name, bases, dict)
+        allEnums[name] = cls
+        return cls
+
     def __init__(cls, name, bases, init_dict):
         if init_dict.has_key('map'):
             if not isinstance(cls.map, dict):
@@ -603,18 +693,42 @@ class MetaEnum(type):
             raise TypeError, "Enum-derived class must define "\
                   "attribute 'map' or 'vals'"
 
-        cls.cxx_type = name + '::Enum'
+        cls.cxx_type = 'Enums::%s' % name
 
         super(MetaEnum, cls).__init__(name, bases, init_dict)
 
+    def __str__(cls):
+        return cls.__name__
+
     # Generate C++ class declaration for this enum type.
     # Note that we wrap the enum in a class/struct to act as a namespace,
     # so that the enum strings can be brief w/o worrying about collisions.
     def cxx_decl(cls):
-        s = 'struct %s {\n  enum Enum {\n    ' % cls.__name__
-        s += ',\n    '.join(['%s = %d' % (v,cls.map[v]) for v in cls.vals])
-        s += '\n  };\n};\n'
-        return s
+        code = "#ifndef __ENUM__%s\n" % cls
+        code += '#define __ENUM__%s\n' % cls
+        code += '\n'
+        code += 'namespace Enums {\n'
+        code += '    enum %s {\n' % cls
+        for val in cls.vals:
+            code += '        %s = %d,\n' % (val, cls.map[val])
+        code += '        Num_%s = %d,\n' % (cls, len(cls.vals))
+        code += '    };\n'
+        code += '    extern const char *%sStrings[Num_%s];\n' % (cls, cls)
+        code += '}\n'
+        code += '\n'
+        code += '#endif\n'
+        return code
+
+    def cxx_def(cls):
+        code = '#include "enums/%s.hh"\n' % cls
+        code += 'namespace Enums {\n'
+        code += '    const char *%sStrings[Num_%s] =\n' % (cls, cls)
+        code += '    {\n'
+        for val in cls.vals:
+            code += '        "%s",\n' % val
+        code += '    };\n'
+        code += '}\n'
+        return code
 
 # Base class for enum types.
 class Enum(ParamValue):
@@ -627,6 +741,9 @@ class Enum(ParamValue):
                   % (value, self.vals)
         self.value = value
 
+    def getValue(self):
+        return int(self.map[self.value])
+
     def __str__(self):
         return self.value
 
@@ -636,9 +753,12 @@ frequency_tolerance = 0.001  # 0.1%
 class TickParamValue(NumericParamValue):
     cxx_type = 'Tick'
     cxx_predecls = ['#include "sim/host.hh"']
-    swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+    swig_predecls = ['%import "stdint.i"\n' +
                      '%import "sim/host.hh"']
 
+    def getValue(self):
+        return long(self.value)
+
 class Latency(TickParamValue):
     def __init__(self, value):
         if isinstance(value, (Latency, Clock)):
@@ -661,12 +781,16 @@ class Latency(TickParamValue):
             return Frequency(self)
         raise AttributeError, "Latency object has no attribute '%s'" % attr
 
-    # convert latency to ticks
-    def ini_str(self):
+    def getValue(self):
         if self.ticks or self.value == 0:
-            return '%d' % self.value
+            value = self.value
         else:
-            return '%d' % (ticks.fromSeconds(self.value))
+            value = ticks.fromSeconds(self.value)
+        return long(value)
+
+    # convert latency to ticks
+    def ini_str(self):
+        return '%d' % self.getValue()
 
 class Frequency(TickParamValue):
     def __init__(self, value):
@@ -691,11 +815,15 @@ class Frequency(TickParamValue):
         raise AttributeError, "Frequency object has no attribute '%s'" % attr
 
     # convert latency to ticks
-    def ini_str(self):
+    def getValue(self):
         if self.ticks or self.value == 0:
-            return '%d' % self.value
+            value = self.value
         else:
-            return '%d' % (ticks.fromSeconds(1.0 / self.value))
+            value = ticks.fromSeconds(1.0 / self.value)
+        return long(value)
+
+    def ini_str(self):
+        return '%d' % self.getValue()
 
 # A generic frequency and/or Latency value.  Value is stored as a latency,
 # but to avoid ambiguity this object does not support numeric ops (* or /).
@@ -703,7 +831,7 @@ class Frequency(TickParamValue):
 class Clock(ParamValue):
     cxx_type = 'Tick'
     cxx_predecls = ['#include "sim/host.hh"']
-    swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
+    swig_predecls = ['%import "stdint.i"\n' +
                      '%import "sim/host.hh"']
     def __init__(self, value):
         if isinstance(value, (Latency, Clock)):
@@ -726,6 +854,9 @@ class Clock(ParamValue):
             return Latency(self)
         raise AttributeError, "Frequency object has no attribute '%s'" % attr
 
+    def getValue(self):
+        return self.period.getValue()
+
     def ini_str(self):
         return self.period.ini_str()
 
@@ -739,11 +870,15 @@ class NetworkBandwidth(float,ParamValue):
     def __str__(self):
         return str(self.val)
 
-    def ini_str(self):
+    def getValue(self):
         # convert to seconds per byte
         value = 8.0 / float(self)
         # convert to ticks per byte
-        return '%f' % (ticks.fromSeconds(value))
+        value = ticks.fromSeconds(value)
+        return float(value)
+
+    def ini_str(self):
+        return '%f' % self.getValue()
 
 class MemoryBandwidth(float,ParamValue):
     cxx_type = 'float'
@@ -755,11 +890,15 @@ class MemoryBandwidth(float,ParamValue):
     def __str__(self):
         return str(self.val)
 
-    def ini_str(self):
+    def getValue(self):
         # convert to seconds per byte
         value = 1.0 / float(self)
         # convert to ticks per byte
-        return '%f' % (ticks.fromSeconds(value))
+        value = ticks.fromSeconds(value)
+        return float(value)
+
+    def ini_str(self):
+        return '%f' % self.getValue()
 
 #
 # "Constants"... handy aliases for various values.
@@ -786,9 +925,13 @@ class NullSimObject(object):
 
     def set_path(self, parent, name):
         pass
+
     def __str__(self):
         return 'Null'
 
+    def getValue(self):
+        return None
+
 # The only instance you'll ever need...
 NULL = NullSimObject()
 
@@ -882,6 +1025,8 @@ class PortRef(object):
 
     # Call C++ to create corresponding port connection between C++ objects
     def ccConnect(self):
+        import internal
+
         if self.ccConnected: # already done this
             return
         peer = self.peer
@@ -1006,7 +1151,6 @@ class PortParamDesc(object):
     ptype_str = 'Port'
     ptype = Port
 
-
 __all__ = ['Param', 'VectorParam',
            'Enum', 'Bool', 'String', 'Float',
            'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
@@ -1021,8 +1165,3 @@ __all__ = ['Param', 'VectorParam',
            'Time',
            'NextEthernetAddr', 'NULL',
            'Port', 'VectorPort']
-
-# see comment on imports at end of __init__.py.
-from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
-import objects
-import internal
diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py
new file mode 100644
index 000000000..1ef78d6cb
--- /dev/null
+++ b/src/python/m5/simulate.py
@@ -0,0 +1,199 @@
+# Copyright (c) 2005 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+#          Steve Reinhardt
+
+import atexit
+import os
+import sys
+
+# import the SWIG-wrapped main C++ functions
+import internal
+from main import options
+import SimObject
+import ticks
+
+# The final hook to generate .ini files.  Called from the user script
+# once the config is built.
+def instantiate(root):
+    # we need to fix the global frequency
+    ticks.fixGlobalFrequency()
+
+    root.unproxy_all()
+    # ugly temporary hack to get output to config.ini
+    sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
+    root.print_ini()
+    sys.stdout.close() # close config.ini
+    sys.stdout = sys.__stdout__ # restore to original
+
+    # Initialize the global statistics
+    internal.stats.initSimStats()
+
+    # Create the C++ sim objects and connect ports
+    root.createCCObject()
+    root.connectPorts()
+
+    # Do a second pass to finish initializing the sim objects
+    internal.sim_object.initAll()
+
+    # Do a third pass to initialize statistics
+    internal.sim_object.regAllStats()
+
+    # Check to make sure that the stats package is properly initialized
+    internal.stats.check()
+
+    # Reset to put the stats in a consistent state.
+    internal.stats.reset()
+
+def doDot(root):
+    dot = pydot.Dot()
+    instance.outputDot(dot)
+    dot.orientation = "portrait"
+    dot.size = "8.5,11"
+    dot.ranksep="equally"
+    dot.rank="samerank"
+    dot.write("config.dot")
+    dot.write_ps("config.ps")
+
+need_resume = []
+need_startup = True
+def simulate(*args, **kwargs):
+    global need_resume, need_startup
+
+    if need_startup:
+        internal.core.SimStartup()
+        need_startup = False
+
+    for root in need_resume:
+        resume(root)
+    need_resume = []
+
+    return internal.event.simulate(*args, **kwargs)
+
+# Export curTick to user script.
+def curTick():
+    return internal.core.cvar.curTick
+
+# Python exit handlers happen in reverse order.  We want to dump stats last.
+atexit.register(internal.stats.dump)
+
+# register our C++ exit callback function with Python
+atexit.register(internal.core.doExitCleanup)
+
+# This loops until all objects have been fully drained.
+def doDrain(root):
+    all_drained = drain(root)
+    while (not all_drained):
+        all_drained = drain(root)
+
+# Tries to drain all objects.  Draining might not be completed unless
+# all objects return that they are drained on the first call.  This is
+# because as objects drain they may cause other objects to no longer
+# be drained.
+def drain(root):
+    all_drained = False
+    drain_event = internal.event.createCountedDrain()
+    unready_objects = root.startDrain(drain_event, True)
+    # If we've got some objects that can't drain immediately, then simulate
+    if unready_objects > 0:
+        drain_event.setCount(unready_objects)
+        simulate()
+    else:
+        all_drained = True
+    internal.event.cleanupCountedDrain(drain_event)
+    return all_drained
+
+def resume(root):
+    root.resume()
+
+def checkpoint(root, dir):
+    if not isinstance(root, objects.Root):
+        raise TypeError, "Checkpoint must be called on a root object."
+    doDrain(root)
+    print "Writing checkpoint"
+    internal.sim_object.serializeAll(dir)
+    resume(root)
+
+def restoreCheckpoint(root, dir):
+    print "Restoring from checkpoint"
+    internal.sim_object.unserializeAll(dir)
+    need_resume.append(root)
+
+def changeToAtomic(system):
+    if not isinstance(system, (objects.Root, objects.System)):
+        raise TypeError, "Parameter of type '%s'.  Must be type %s or %s." % \
+              (type(system), objects.Root, objects.System)
+    if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
+        doDrain(system)
+        print "Changing memory mode to atomic"
+        system.changeTiming(internal.sim_object.SimObject.Atomic)
+
+def changeToTiming(system):
+    if not isinstance(system, (objects.Root, objects.System)):
+        raise TypeError, "Parameter of type '%s'.  Must be type %s or %s." % \
+              (type(system), objects.Root, objects.System)
+
+    if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
+        doDrain(system)
+        print "Changing memory mode to timing"
+        system.changeTiming(internal.sim_object.SimObject.Timing)
+
+def switchCpus(cpuList):
+    print "switching cpus"
+    if not isinstance(cpuList, list):
+        raise RuntimeError, "Must pass a list to this function"
+    for i in cpuList:
+        if not isinstance(i, tuple):
+            raise RuntimeError, "List must have tuples of (oldCPU,newCPU)"
+
+    [old_cpus, new_cpus] = zip(*cpuList)
+
+    for cpu in old_cpus:
+        if not isinstance(cpu, objects.BaseCPU):
+            raise TypeError, "%s is not of type BaseCPU" % cpu
+    for cpu in new_cpus:
+        if not isinstance(cpu, objects.BaseCPU):
+            raise TypeError, "%s is not of type BaseCPU" % cpu
+
+    # Drain all of the individual CPUs
+    drain_event = internal.event.createCountedDrain()
+    unready_cpus = 0
+    for old_cpu in old_cpus:
+        unready_cpus += old_cpu.startDrain(drain_event, False)
+    # If we've got some objects that can't drain immediately, then simulate
+    if unready_cpus > 0:
+        drain_event.setCount(unready_cpus)
+        simulate()
+    internal.event.cleanupCountedDrain(drain_event)
+    # Now all of the CPUs are ready to be switched out
+    for old_cpu in old_cpus:
+        old_cpu._ccObject.switchOut()
+    index = 0
+    for new_cpu in new_cpus:
+        new_cpu.takeOverFrom(old_cpus[index])
+        new_cpu._ccObject.resume()
+        index += 1
diff --git a/src/python/m5/ticks.py b/src/python/m5/ticks.py
index e91b470ff..91834c9c8 100644
--- a/src/python/m5/ticks.py
+++ b/src/python/m5/ticks.py
@@ -28,14 +28,12 @@
 
 import sys
 
-import convert
-import internal
-
 tps = 1.0e12         # default to 1 THz (1 Tick == 1 ps)
 tps_fixed = False    # once set to true, can't be changed
 
 # fix the global frequency and tell C++ about it
 def fixGlobalFrequency():
+    import internal
     global tps, tps_fixed
     if not tps_fixed:
         tps_fixed = True
@@ -43,6 +41,8 @@ def fixGlobalFrequency():
         print "Global frequency set at %d ticks per second" % int(tps)
 
 def setGlobalFrequency(ticksPerSecond):
+    import convert
+
     global tps, tps_fixed
 
     if tps_fixed:
diff --git a/src/cpu/trace/reader/mem_trace_reader.cc b/src/python/swig/inet.i
index 5623f168a..96b4b85d0 100644
--- a/src/cpu/trace/reader/mem_trace_reader.cc
+++ b/src/python/swig/inet.i
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,15 +25,19 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Erik Hallnor
+ * Authors: Nathan Binkert
  */
 
-/**
- * @file
- * SimObject Declaration of pure virtual MemTraceReader class.
- */
+%{
+#include "base/inet.hh"
+%}
 
-#include "cpu/trace/reader/mem_trace_reader.hh"
-#include "sim/param.hh"
+namespace Net {
+struct EthAddr
+{
+    EthAddr();
+    EthAddr(const uint8_t ea[6]);
+    EthAddr(const std::string &addr);
+};
+}
 
-DEFINE_SIM_OBJECT_CLASS_NAME("MemTraceReader", MemTraceReader);
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
index 2a5f2b9fb..455888c04 100644
--- a/src/python/swig/pyobject.cc
+++ b/src/python/swig/pyobject.cc
@@ -36,7 +36,6 @@
 #include "base/output.hh"
 #include "mem/mem_object.hh"
 #include "mem/port.hh"
-#include "sim/builder.hh"
 #include "sim/sim_object.hh"
 
 using namespace std;
@@ -89,12 +88,6 @@ inifile()
     return inifile;
 }
 
-SimObject *
-createSimObject(const string &name)
-{
-    return SimObjectClass::createObject(inifile(), name);
-}
-
 /**
  * Pointer to the Python function that maps names to SimObjects.
  */
@@ -130,7 +123,6 @@ void
 loadIniFile(PyObject *_resolveFunc)
 {
     resolveFunc = _resolveFunc;
-    configStream = simout.find("config.out");
 
     // The configuration database is now complete; start processing it.
     inifile().load(simout.resolve("config.ini"));
diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh
index d8efc9149..da609e07e 100644
--- a/src/python/swig/pyobject.hh
+++ b/src/python/swig/pyobject.hh
@@ -36,7 +36,6 @@
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
 
-SimObject *createSimObject(const std::string &name);
 extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
 SimObject *resolveSimObject(const std::string &name);
 void loadIniFile(PyObject *_resolveFunc);
diff --git a/src/mem/cache/tags/repl/repl.cc b/src/python/swig/range.i
index ce781eb9f..40809dae4 100644
--- a/src/mem/cache/tags/repl/repl.cc
+++ b/src/python/swig/range.i
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,19 +25,11 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Erik Hallnor
- *          Nathan Binkert
+ * Authors: Nathan Binkert
  */
 
-/**
- * Definitions of the base replacement class.
- */
-
-#include "sim/param.hh"
-#include "mem/cache/tags/repl/repl.hh"
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-DEFINE_SIM_OBJECT_CLASS_NAME("Repl", Repl)
+%include "base/range.hh"
+%include "sim/host.hh"
 
-#endif //DOXYGEN_SHOULD_SKIP_THIS
+%template(AddrRange) Range<Addr>;
+%template(TickRange) Range<Tick>;
diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i
index a1737c438..ebd019ca3 100644
--- a/src/python/swig/sim_object.i
+++ b/src/python/swig/sim_object.i
@@ -31,6 +31,7 @@
 %module sim_object
 
 %{
+#include "enums/MemoryMode.hh"
 #include "python/swig/pyobject.hh"
 %}
 
@@ -49,12 +50,6 @@ class SimObject {
       Drained
     };
 
-    enum MemoryMode {
-      Invalid,
-      Atomic,
-      Timing
-    };
-
     unsigned int drain(Event *drain_event);
     void resume();
     void switchOut();
@@ -66,12 +61,10 @@ class System {
     private:
       System();
     public:
-      SimObject::MemoryMode getMemoryMode();
-      void setMemoryMode(SimObject::MemoryMode mode);
+      Enums::MemoryMode getMemoryMode();
+      void setMemoryMode(Enums::MemoryMode mode);
 };
 
-SimObject *createSimObject(const std::string &name);
-
 int connectPorts(SimObject *o1, const std::string &name1, int i1,
                  SimObject *o2, const std::string &name2, int i2);
 
diff --git a/src/cpu/op_class.cc b/src/python/swig/time.i
index 02cb4a08a..9bbad081a 100644
--- a/src/cpu/op_class.cc
+++ b/src/python/swig/time.i
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,28 +25,20 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Steve Reinhardt
+ * Authors: Nathan Binkert
  */
 
-#include "cpu/op_class.hh"
+%{
+#include <sys/time.h>
+%}
 
-/** OpClass enum -> description string */
-const char *
-opClassStrings[Num_OpClasses] =
-{
-    "No_OpClass",
-    "IntAlu",
-    "IntMult",
-    "IntDiv",
-    "FloatAdd",
-    "FloatCmp",
-    "FloatCvt",
-    "FloatMult",
-    "FloatDiv",
-    "FloatSqrt",
-    "MemRead",
-    "MemWrite",
-    "IprAccess",
-    "InstPrefetch"
+struct tm {
+    int tm_sec;         /* seconds after the minute [0-60] */
+    int tm_min;         /* minutes after the hour [0-59] */
+    int tm_hour;        /* hours since midnight [0-23] */
+    int tm_mday;        /* day of the month [1-31] */
+    int tm_mon;         /* months since January [0-11] */
+    int tm_year;        /* years since 1900 */
+    int tm_wday;        /* days since Sunday [0-6] */
+    int tm_yday;        /* days since January 1 [0-365] */
 };
-
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 50f966bcf..455e5678a 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -34,13 +34,11 @@ SimObject('Root.py')
 SimObject('System.py')
 
 Source('async.cc')
-Source('builder.cc')
 Source('core.cc')
 Source('debug.cc')
 Source('eventq.cc')
 Source('faults.cc')
 Source('main.cc')
-Source('param.cc')
 Source('root.cc')
 Source('serialize.cc')
 Source('sim_events.cc')
diff --git a/src/sim/builder.cc b/src/sim/builder.cc
deleted file mode 100644
index 532df36b1..000000000
--- a/src/sim/builder.cc
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#include <assert.h>
-
-#include "base/inifile.hh"
-#include "base/misc.hh"
-#include "sim/builder.hh"
-#include "sim/host.hh"
-#include "sim/sim_object.hh"
-#include "sim/core.hh"
-
-using namespace std;
-
-SimObjectBuilder::SimObjectBuilder(const std::string &_iniSection)
-    : ParamContext(_iniSection)
-{
-}
-
-SimObjectBuilder::~SimObjectBuilder()
-{
-}
-
-///////////////////////////////////////////
-//
-// SimObjectBuilder member definitions
-//
-///////////////////////////////////////////
-
-// override ParamContext::parseParams() to check params based on
-// instance name first.  If not found, then check based on iniSection
-// (as in default ParamContext implementation).
-void
-SimObjectBuilder::parseParams(IniFile &iniFile)
-{
-    iniFilePtr = &iniFile;	// set object member
-
-    ParamList::iterator i;
-
-    for (i = paramList->begin(); i != paramList->end(); ++i) {
-        string string_value;
-        if (iniFile.find(iniSection, (*i)->name, string_value))
-            (*i)->parse(string_value);
-    }
-}
-
-
-void
-SimObjectBuilder::printErrorProlog(ostream &os)
-{
-    ccprintf(os, "Error creating object '%s':\n", iniSection);
-}
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// SimObjectClass member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-// Map of class names to SimObjectBuilder creation functions.  Need to
-// make this a pointer so we can force initialization on the first
-// reference; otherwise, some SimObjectClass constructors may be invoked
-// before the classMap constructor.
-map<string,SimObjectClass::CreateFunc> *SimObjectClass::classMap = NULL;
-
-// SimObjectClass constructor: add mapping to classMap
-SimObjectClass::SimObjectClass(const string &className, CreateFunc createFunc)
-{
-    if (classMap == NULL)
-        classMap = new map<string,SimObjectClass::CreateFunc>();
-
-    if ((*classMap)[className])
-        panic("Error: simulation object class '%s' redefined\n", className);
-
-    // add className --> createFunc to class map
-    (*classMap)[className] = createFunc;
-}
-
-
-//
-//
-SimObject *
-SimObjectClass::createObject(IniFile &configDB, const std::string &iniSection)
-{
-    string type;
-    if (!configDB.find(iniSection, "type", type)) {
-        // no C++ type associated with this object
-        return NULL;
-    }
-
-    // look up className to get appropriate createFunc
-    if (classMap->find(type) == classMap->end())
-        panic("Simulator object type '%s' not found.\n", type);
-
-
-    CreateFunc createFunc = (*classMap)[type];
-
-    // call createFunc with config hierarchy node to get object
-    // builder instance (context with parameters for object creation)
-    SimObjectBuilder *objectBuilder = (*createFunc)(iniSection);
-
-    assert(objectBuilder != NULL);
-
-    // parse all parameters in context to generate parameter values
-    objectBuilder->parseParams(configDB);
-
-    // now create the actual simulation object
-    SimObject *object = objectBuilder->create();
-
-    assert(object != NULL);
-
-    // echo object parameters to stats file (for documenting the
-    // config used to generate the associated stats)
-    ccprintf(*configStream, "[%s]\n", object->name());
-    ccprintf(*configStream, "type=%s\n", type);
-    objectBuilder->showParams(*configStream);
-    ccprintf(*configStream, "\n");
-
-    // done with the SimObjectBuilder now
-    delete objectBuilder;
-
-    return object;
-}
-
-
-//
-// static method:
-//
-void
-SimObjectClass::describeAllClasses(ostream &os)
-{
-    map<string,CreateFunc>::iterator iter;
-
-    for (iter = classMap->begin(); iter != classMap->end(); ++iter) {
-        const string &className = iter->first;
-        CreateFunc createFunc = iter->second;
-
-        os << "[" << className << "]\n";
-
-        // create dummy object builder just to instantiate parameters
-        SimObjectBuilder *objectBuilder = (*createFunc)("");
-
-        // now get the object builder to describe ite params
-        objectBuilder->describeParams(os);
-
-        os << endl;
-
-        // done with the object builder now
-        delete objectBuilder;
-    }
-}
diff --git a/src/sim/builder.hh b/src/sim/builder.hh
deleted file mode 100644
index aa0e3d17c..000000000
--- a/src/sim/builder.hh
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- */
-
-#ifndef __BUILDER_HH__
-#define __BUILDER_HH__
-
-#include <iosfwd>
-#include <list>
-#include <map>
-#include <vector>
-
-#include "sim/param.hh"
-
-class SimObject;
-
-//
-// A SimObjectBuilder serves as an evaluation context for a set of
-// parameters that describe a specific instance of a SimObject.  This
-// evaluation context corresponds to a section in the .ini file (as
-// with the base ParamContext) plus an optional node in the
-// configuration hierarchy (the configNode member) for resolving
-// SimObject references.  SimObjectBuilder is an abstract superclass;
-// derived classes specialize the class for particular subclasses of
-// SimObject (e.g., BaseCache).
-//
-// For typical usage, see the definition of
-// SimObjectClass::createObject().
-//
-class SimObjectBuilder : public ParamContext
-{
-  public:
-    SimObjectBuilder(const std::string &_iniSection);
-
-    virtual ~SimObjectBuilder();
-
-    // call parse() on all params in this context to convert string
-    // representations to parameter values
-    virtual void parseParams(IniFile &iniFile);
-
-    // parameter error prolog (override of ParamContext)
-    virtual void printErrorProlog(std::ostream &);
-
-    // generate the name for this SimObject instance (derived from the
-    // configuration hierarchy node label and position)
-    virtual const std::string &getInstanceName() { return iniSection; }
-
-    // Create the actual SimObject corresponding to the parameter
-    // values in this context.  This function is overridden in derived
-    // classes to call a specific constructor for a particular
-    // subclass of SimObject.
-    virtual SimObject *create() = 0;
-};
-
-
-//
-// Handy macros for initializing parameter members of classes derived
-// from SimObjectBuilder.  Assumes that the name of the parameter
-// member object is the same as the textual parameter name seen by the
-// user.  (Note that '#p' is expanded by the preprocessor to '"p"'.)
-//
-#define INIT_PARAM(p, desc)		p(this, #p, desc)
-#define INIT_PARAM_DFLT(p, desc, dflt)	p(this, #p, desc, dflt)
-
-//
-// Initialize an enumeration variable... assumes that 'map' is the
-// name of an array of mappings (char * for SimpleEnumParam, or
-// EnumParamMap for MappedEnumParam).
-//
-#define INIT_ENUM_PARAM(p, desc, map)	\
-        p(this, #p, desc, map, sizeof(map)/sizeof(map[0]))
-#define INIT_ENUM_PARAM_DFLT(p, desc, map, dflt)	\
-        p(this, #p, desc, map, sizeof(map)/sizeof(map[0]), dflt)
-
-//
-// An instance of SimObjectClass corresponds to a class derived from
-// SimObject.  The SimObjectClass instance serves to bind the string
-// name (found in the config file) to a function that creates an
-// instance of the appropriate derived class.
-//
-// This would be much cleaner in Smalltalk or Objective-C, where types
-// are first-class objects themselves.
-//
-class SimObjectClass
-{
-  public:
-    // Type CreateFunc is a pointer to a function that creates a new
-    // simulation object builder based on a .ini-file parameter
-    // section (specified by the first string argument), a unique name
-    // for the object (specified by the second string argument), and
-    // an optional config hierarchy node (specified by the third
-    // argument).  A pointer to the new SimObjectBuilder is returned.
-    typedef SimObjectBuilder *(*CreateFunc)(const std::string &iniSection);
-
-    static std::map<std::string,CreateFunc> *classMap;
-
-    // Constructor.  For example:
-    //
-    // SimObjectClass baseCacheClass("BaseCache", newBaseCacheBuilder);
-    //
-    SimObjectClass(const std::string &className, CreateFunc createFunc);
-
-    // create SimObject given name of class and pointer to
-    // configuration hierarchy node
-    static SimObject *createObject(IniFile &configDB,
-                                   const std::string &iniSection);
-
-    // print descriptions of all parameters registered with all
-    // SimObject classes
-    static void describeAllClasses(std::ostream &os);
-};
-
-//
-// Macros to encapsulate the magic of declaring & defining
-// SimObjectBuilder and SimObjectClass objects
-//
-
-#define BEGIN_DECLARE_SIM_OBJECT_PARAMS(OBJ_CLASS)		\
-class OBJ_CLASS##Builder : public SimObjectBuilder		\
-{								\
-  public:
-
-#define END_DECLARE_SIM_OBJECT_PARAMS(OBJ_CLASS)		\
-                                                                \
-    OBJ_CLASS##Builder(const std::string &iniSection);          \
-    virtual ~OBJ_CLASS##Builder() {}				\
-                                                                \
-    OBJ_CLASS *create();					\
-};
-
-#define BEGIN_INIT_SIM_OBJECT_PARAMS(OBJ_CLASS)			\
-    OBJ_CLASS##Builder::OBJ_CLASS##Builder(const std::string &iSec) \
-    : SimObjectBuilder(iSec),
-
-
-#define END_INIT_SIM_OBJECT_PARAMS(OBJ_CLASS)			\
-{								\
-}
-
-#define CREATE_SIM_OBJECT(OBJ_CLASS)				\
-OBJ_CLASS *OBJ_CLASS##Builder::create()
-
-#define REGISTER_SIM_OBJECT(CLASS_NAME, OBJ_CLASS)		\
-SimObjectBuilder *						\
-new##OBJ_CLASS##Builder(const std::string &iniSection)          \
-{								\
-    return new OBJ_CLASS##Builder(iniSection);			\
-}								\
-                                                                \
-SimObjectClass the##OBJ_CLASS##Class(CLASS_NAME,		\
-                                     new##OBJ_CLASS##Builder);	\
-                                                                \
-/* see param.hh */						\
-DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, OBJ_CLASS)
-
-/* Macros that use the namespace for sinic... yuk. */
-#define BEGIN_DECLARE_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS)		\
-class NAME_SPACE##OBJ_CLASS##Builder : public SimObjectBuilder		\
-{								\
-  public:
-
-#define END_DECLARE_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS)		\
-                                                                \
-    NAME_SPACE##OBJ_CLASS##Builder(const std::string &iniSection);          \
-    virtual ~NAME_SPACE##OBJ_CLASS##Builder() {}				\
-                                                                \
-    NAME_SPACE::OBJ_CLASS *create();					\
-};
-
-#define BEGIN_INIT_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS)			\
-    NAME_SPACE::OBJ_CLASS##Builder::OBJ_CLASS##Builder(const std::string &iSec) \
-    : SimObjectBuilder(iSec),
-
-
-#define END_INIT_SIM_OBJECT_PARAMS_WNS(NAME_SPACE, OBJ_CLASS)			\
-{								\
-}
-
-#define CREATE_SIM_OBJECT_WNS(NAME_SPACE, OBJ_CLASS)				\
-NAME_SPACE::OBJ_CLASS *NAME_SPACE##OBJ_CLASS##Builder::create()
-
-#define REGISTER_SIM_OBJECT_WNS(NAME_SPACE, CLASS_NAME, OBJ_CLASS)		\
-SimObjectBuilder *						\
-new##NAME_SPACEi##OBJ_CLASS##Builder(const std::string &iniSection)          \
-{								\
-    return new NAME_SPACE##OBJ_CLASS##Builder(iniSection);			\
-}								\
-                                                                \
-SimObjectClass the##NAME_SPACE##OBJ_CLASS##Class(CLASS_NAME,		\
-                                     new##NAME_SPACE##OBJ_CLASS##Builder);	\
-                                                                \
-/* see param.hh */						\
-DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, NAME_SPACE##OBJ_CLASS)
-
-
-
-#endif // __BUILDER_HH__
diff --git a/src/sim/core.cc b/src/sim/core.cc
index c961e9eb8..75f1f384c 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -98,7 +98,6 @@ setOutputDir(const string &dir)
 }
 
 ostream *outputStream;
-ostream *configStream;
 
 void
 setOutputFile(const string &file)
diff --git a/src/sim/core.hh b/src/sim/core.hh
index 7360032c2..fb7f921f4 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -75,9 +75,6 @@ extern std::ostream *outputStream;
 void setOutputFile(const std::string &file);
 void setOutputDir(const std::string &dir);
 
-/// Output stream for configuration dump.
-extern std::ostream *configStream;
-
 struct Callback;
 void registerExitCallback(Callback *callback);
 void doExitCleanup();
diff --git a/src/sim/debug.cc b/src/sim/debug.cc
index 84ab1074d..c189117bd 100644
--- a/src/sim/debug.cc
+++ b/src/sim/debug.cc
@@ -38,7 +38,6 @@
 
 #include "sim/debug.hh"
 #include "sim/eventq.hh"
-#include "sim/param.hh"
 #include "sim/sim_events.hh"
 
 using namespace std;
diff --git a/src/sim/param.cc b/src/sim/param.cc
deleted file mode 100644
index 51d389f5a..000000000
--- a/src/sim/param.cc
+++ /dev/null
@@ -1,700 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#include <algorithm>
-#include <cassert>
-#include <list>
-#include <string>
-#include <vector>
-
-#include "base/inifile.hh"
-#include "base/misc.hh"
-#include "base/range.hh"
-#include "base/str.hh"
-#include "base/trace.hh"
-#include "sim/param.hh"
-#include "sim/sim_object.hh"
-
-using namespace std;
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// BaseParam member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-void
-BaseParam::die(const string &err) const
-{
-    context->printErrorProlog(cerr);
-    cerr << "  parameter '" << name << "': "
-         << err << endl;
-    abort();
-}
-
-
-////////////////////////////////////////////////////////////////////////
-//
-// Param<T> and VectorParam<T> member definitions
-//
-// We implement parsing & displaying values for various parameter
-// types T using a set of overloaded functions:
-//
-//  - parseParam(string s, T &value) parses s into value
-//  - showParam(ostream &os, T &value) displays value on os
-//
-// By making these independent functions, we can reuse the same code
-// for type T in both Param<T> and VectorParam<T>.
-//
-// For enum types, the parseParam function requires additional
-// arguments, in which case we must specialize the Param<T>::parse and
-// VectorParam<T>::parse calls as well.
-//
-// Type-specific instances come first, followed by more generic
-// templated versions and their instantiations.
-//
-////////////////////////////////////////////////////////////////////////
-
-//
-// The base implementations use to_number for parsing and '<<' for
-// displaying, suitable for integer types.
-//
-template <class T>
-bool
-parseParam(const string &s, T &value)
-{
-    return to_number(s, value);
-}
-
-template <class T>
-void
-showParam(ostream &os, T const &value)
-{
-    os << value;
-}
-
-//
-// Template specializations:
-// - char (8-bit integer)
-// - floating-point types
-// - bool
-// - string
-//
-
-// Treat 8-bit ints (chars) as ints on output, not as chars
-template <>
-void
-showParam(ostream &os, const char &value)
-{
-    os << (int)value;
-}
-
-
-template <>
-void
-showParam(ostream &os, const unsigned char &value)
-{
-    os << (unsigned int)value;
-}
-
-
-// Use sscanf() for FP types as to_number() only handles integers
-template <>
-bool
-parseParam(const string &s, float &value)
-{
-    return (sscanf(s.c_str(), "%f", &value) == 1);
-}
-
-template <>
-bool
-parseParam(const string &s, double &value)
-{
-    return (sscanf(s.c_str(), "%lf", &value) == 1);
-}
-
-// Be flexible about what we take for bool
-template <>
-bool
-parseParam(const string &s, bool &value)
-{
-    const string &ls = to_lower(s);
-
-    if (ls == "true" || ls == "t" || ls == "yes" || ls == "y" || ls == "1") {
-        value = true;
-        return true;
-    }
-
-    if (ls == "false" || ls == "f" || ls == "no" || ls == "n" || ls == "0") {
-        value = false;
-        return true;
-    }
-
-    return false;
-}
-
-// Display bools as strings
-template <>
-void
-showParam(ostream &os, const bool &value)
-{
-    os << (value ? "true" : "false");
-}
-
-
-// String requires no processing to speak of
-template <>
-bool
-parseParam(const string &s, string &value)
-{
-    value = s;
-    return true;
-}
-
-template <>
-bool
-parseParam(const string &s, Range<uint32_t> &value)
-{
-    value = s;
-    return value.valid();
-}
-
-template <>
-bool
-parseParam(const string &s, Range<uint64_t> &value)
-{
-    value = s;
-    return value.valid();
-}
-
-//
-// End of parseParam/showParam definitions.  Now we move on to
-// incorporate them into the Param/VectorParam parse() and showValue()
-// methods.
-//
-
-// These definitions for Param<T>::parse and VectorParam<T>::parse
-// work for any type for which parseParam() takes only two arguments
-// (i.e., all the fundamental types like int, bool, etc.), thanks to
-// overloading.
-template <class T>
-void
-Param<T>::parse(const string &s)
-{
-    if (parseParam(s, value)) {
-        wasSet = true;
-    }
-    else {
-        string err("could not parse \"");
-
-        err += s;
-        err += "\"";
-
-        die(err);
-    }
-}
-
-template <class T>
-void
-VectorParam<T>::parse(const string &s)
-{
-    if (s.empty()) {
-        wasSet = true;
-        return;
-    }
-
-    vector<string> tokens;
-
-    tokenize(tokens, s, ' ');
-
-    value.resize(tokens.size());
-
-    for (int i = 0; i < tokens.size(); i++) {
-        // need to parse into local variable to handle vector<bool>,
-        // for which operator[] returns a special reference class
-        // that's not the same as 'bool&', (since it's a packed
-        // vector)
-        T scalar_value;
-        if (!parseParam(tokens[i], scalar_value)) {
-            string err("could not parse \"");
-
-            err += s;
-            err += "\"";
-
-            die(err);
-        }
-
-        // assign parsed value to vector
-        value[i] = scalar_value;
-    }
-
-    wasSet = true;
-}
-
-// These definitions for Param<T>::showValue() and
-// VectorParam<T>::showValue() work for any type where showParam()
-// takes only two arguments (i.e., everything but the SimpleEnum and
-// MappedEnum classes).
-template <class T>
-void
-Param<T>::showValue(ostream &os) const
-{
-    showParam(os, value);
-}
-
-template <class T>
-void
-VectorParam<T>::showValue(ostream &os) const
-{
-    for (int i = 0; i < value.size(); i++) {
-        if (i != 0) {
-            os << " ";
-        }
-        showParam(os, value[i]);
-    }
-}
-
-
-#ifdef INSURE_BUILD
-#define INSTANTIATE_PARAM_TEMPLATES(type, typestr)			\
-void Param<type>::showType(ostream &os) const { os << typestr; }	\
-void VectorParam<type>::showType(ostream &os) const { 			\
-    os << "vector of " << typestr; 					\
-}									\
-template Param<type>;							\
-template VectorParam<type>;
-
-#else
-// instantiate all four methods (parse/show, scalar/vector) for basic
-// types that can use the above templates
-#define INSTANTIATE_PARAM_TEMPLATES(type, typestr)			\
-template bool parseParam<type>(const string &s, type &value);		\
-template void showParam<type>(ostream &os, type const &value);		\
-template void Param<type>::parse(const string &);			\
-template void VectorParam<type>::parse(const string &);			\
-template void Param<type>::showValue(ostream &) const;			\
-template void VectorParam<type>::showValue(ostream &) const;		\
-template <> void Param<type>::showType(ostream &os) const { os << typestr; }	\
-template <> void VectorParam<type>::showType(ostream &os) const {			\
-    os << "vector of " << typestr;					\
-}
-#endif
-
-INSTANTIATE_PARAM_TEMPLATES(unsigned long long, "ull")
-INSTANTIATE_PARAM_TEMPLATES(signed long long, "sll")
-INSTANTIATE_PARAM_TEMPLATES(unsigned long, "uns long")
-INSTANTIATE_PARAM_TEMPLATES(signed long, "long")
-INSTANTIATE_PARAM_TEMPLATES(unsigned int, "uns")
-INSTANTIATE_PARAM_TEMPLATES(signed int, "int")
-INSTANTIATE_PARAM_TEMPLATES(unsigned short, "uns short")
-INSTANTIATE_PARAM_TEMPLATES(signed short, "short")
-INSTANTIATE_PARAM_TEMPLATES(unsigned char, "uns char")
-INSTANTIATE_PARAM_TEMPLATES(signed char, "char")
-
-INSTANTIATE_PARAM_TEMPLATES(float, "float")
-INSTANTIATE_PARAM_TEMPLATES(double, "double")
-
-INSTANTIATE_PARAM_TEMPLATES(bool, "bool")
-INSTANTIATE_PARAM_TEMPLATES(string, "string")
-
-INSTANTIATE_PARAM_TEMPLATES(Range<uint64_t>, "uint64 range")
-INSTANTIATE_PARAM_TEMPLATES(Range<uint32_t>, "uint32 range")
-
-#undef INSTANTIATE_PARAM_TEMPLATES
-
-//
-// SimpleEnumParam & MappedEnumParam must specialize their parse(),
-// showValue(), and showType() methods.
-//
-
-//
-// SimpleEnumParam & SimpleEnumVectorParam
-//
-bool
-parseEnumParam(const char *const *map, const int num_values,
-               const string &s, int &value)
-{
-    for (int i = 0; i < num_values; ++i) {
-        if (s == map[i]) {
-            value = i;
-            return true;
-        }
-    }
-
-    return false;
-}
-
-void
-showEnumParam(ostream &os,
-              const char *const *map,  const int num_values,
-              int value)
-{
-    assert(0 <= value && value < num_values);
-    os << map[value];
-}
-
-void
-showEnumType(ostream &os,
-             const char *const *map,  const int num_values)
-{
-    os << "{" << map[0];
-    for (int i = 1; i < num_values; ++i)
-        os << "," << map[i];
-
-    os << "}";
-}
-
-
-//
-// MappedEnumParam & MappedEnumVectorParam
-//
-bool
-parseEnumParam(const EnumParamMap *map, const int num_values,
-               const string &s, int &value)
-{
-    for (int i = 0; i < num_values; ++i) {
-        if (s == map[i].name) {
-            value = map[i].value;
-            return true;
-        }
-    }
-
-    return false;
-}
-
-void
-showEnumParam(ostream &os,
-              const EnumParamMap *map, const int num_values,
-              int value)
-{
-    for (int i = 0; i < num_values; ++i) {
-        if (value == map[i].value) {
-            os << map[i].name;
-            return;
-        }
-    }
-
-    // if we can't find a reverse mapping just print the int value
-    os << value;
-}
-
-void
-showEnumType(ostream &os,
-             const EnumParamMap *map,  const int num_values)
-{
-    os << "{" << map[0].name;
-    for (int i = 1; i < num_values; ++i)
-        os << "," << map[i].name;
-
-    os << "}";
-}
-
-
-template <class Map>
-void
-EnumParam<Map>::parse(const string &s)
-{
-    if (parseEnumParam(map, num_values, s, value)) {
-        wasSet = true;
-    } else {
-        string err("no match for enum string \"");
-
-        err += s;
-        err += "\"";
-
-        die(err);
-    }
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::parse(const string &s)
-{
-    vector<string> tokens;
-
-    if (s.empty()) {
-        wasSet = true;
-        return;
-    }
-
-    tokenize(tokens, s, ' ');
-
-    value.resize(tokens.size());
-
-    for (int i = 0; i < tokens.size(); i++) {
-        if (!parseEnumParam(map, num_values, tokens[i], value[i])) {
-            string err("no match for enum string \"");
-
-            err += s;
-            err += "\"";
-
-            die(err);
-        }
-    }
-
-    wasSet = true;
-}
-
-template <class Map>
-void
-EnumParam<Map>::showValue(ostream &os) const
-{
-    showEnumParam(os, map, num_values, value);
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::showValue(ostream &os) const
-{
-    for (int i = 0; i < value.size(); i++) {
-        if (i != 0) {
-            os << " ";
-        }
-        showEnumParam(os, map, num_values, value[i]);
-    }
-}
-
-template <class Map>
-void
-EnumParam<Map>::showType(ostream &os) const
-{
-    showEnumType(os, map, num_values);
-}
-
-template <class Map>
-void
-EnumVectorParam<Map>::showType(ostream &os) const
-{
-    os << "vector of";
-    showEnumType(os, map, num_values);
-}
-
-template class EnumParam<const char *>;
-template class EnumVectorParam<const char *>;
-
-template class EnumParam<EnumParamMap>;
-template class EnumVectorParam<EnumParamMap>;
-
-////////////////////////////////////////////////////////////////////////
-//
-// SimObjectBaseParam methods
-//
-////////////////////////////////////////////////////////////////////////
-
-bool
-parseSimObjectParam(ParamContext *context, const string &s, SimObject *&value)
-{
-    SimObject *obj;
-
-    if (to_lower(s) == "null") {
-        // explicitly set to null by user; assume that's OK
-        obj = NULL;
-    }
-    else {
-        // defined in main.cc
-        extern SimObject *resolveSimObject(const string &);
-        obj = resolveSimObject(s);
-
-        if (obj == NULL)
-            return false;
-    }
-
-    value = obj;
-    return true;
-}
-
-
-void
-SimObjectBaseParam::showValue(ostream &os, SimObject *value) const
-{
-    os << (value ? value->name() : "null");
-}
-
-void
-SimObjectBaseParam::parse(const string &s, SimObject *&value)
-{
-    if (parseSimObjectParam(context, s, value)) {
-        wasSet = true;
-    }
-    else {
-        string err("could not resolve object name \"");
-
-        err += s;
-        err += "\"";
-
-        die(err);
-    }
-}
-
-void
-SimObjectBaseParam::parse(const string &s, vector<SimObject *>&value)
-{
-    vector<string> tokens;
-
-    tokenize(tokens, s, ' ');
-
-    value.resize(tokens.size());
-
-    for (int i = 0; i < tokens.size(); i++) {
-        if (!parseSimObjectParam(context, tokens[i], value[i])) {
-            string err("could not resolve object name \"");
-
-            err += s;
-            err += "\"";
-
-            die(err);
-        }
-    }
-
-    wasSet = true;
-}
-
-////////////////////////////////////////////////////////////////////////
-//
-// ParamContext member definitions
-//
-////////////////////////////////////////////////////////////////////////
-
-ParamContext::ParamContext(const string &_iniSection)
-    : iniFilePtr(NULL),	// initialized on call to parseParams()
-      iniSection(_iniSection), paramList(NULL)
-{
-}
-
-
-void
-ParamContext::addParam(BaseParam *param)
-{
-    getParamList()->push_back(param);
-}
-
-
-void
-ParamContext::parseParams(IniFile &iniFile)
-{
-    iniFilePtr = &iniFile;	// set object member
-
-    ParamList::iterator i;
-
-    for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
-        string string_value;
-
-        if (iniFile.find(iniSection, (*i)->name, string_value))
-            (*i)->parse(string_value);
-    }
-}
-
-
-// Check parameter values for validity & consistency. Default
-// implementation is no-op; derive subclass & override to add
-// actual functionality here.
-void
-ParamContext::checkParams()
-{
-    // nada
-}
-
-
-// Clean up context-related objects at end of execution. Default
-// implementation is no-op; derive subclass & override to add actual
-// functionality here.
-void
-ParamContext::cleanup()
-{
-    // nada
-}
-
-
-void
-ParamContext::describeParams(ostream &os)
-{
-    ParamList::iterator i;
-
-    for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
-        BaseParam *p = *i;
-
-        os << p->name << " (";
-        p->showType(os);
-        os << "): " << p->description << "\n";
-    }
-}
-
-
-
-void
-ParamContext::showParams(ostream &os)
-{
-    ParamList::iterator i;
-
-    for (i = getParamList()->begin(); i != getParamList()->end(); ++i) {
-        BaseParam *p = *i;
-
-        if (p->isValid()) {
-            os << p->name << "=";
-            p->showValue(os);
-            os << endl;
-        }
-        else {
-            os << "// "<< p->name << " not specified" << endl;
-        }
-    }
-}
-
-
-void
-ParamContext::printErrorProlog(ostream &os)
-{
-    os << "Parameter error in section [" << iniSection << "]: " << endl;
-}
-
-void
-parseTime(const std::vector<int> &time, struct tm *tm)
-{
-    memset(tm, 0, sizeof(struct tm));
-
-    // UNIX is years since 1900
-    tm->tm_year = time[0] - 1900;
-
-    // Python starts at 1, UNIX starts at 0
-    tm->tm_mon = time[1] - 1;
-    tm->tm_mday = time[2];
-    tm->tm_hour = time[3];
-    tm->tm_min = time[4];
-    tm->tm_sec = time[5];
-
-    // Python has 0 as Monday, UNIX is 0 as sunday
-    tm->tm_wday = time[6] + 1;
-    if (tm->tm_wday > 6)
-        tm->tm_wday -= 7;
-
-    // Python starts at 1, Unix starts at 0
-    tm->tm_yday = time[7] - 1;
-}
diff --git a/src/sim/param.hh b/src/sim/param.hh
deleted file mode 100644
index dff0fa72d..000000000
--- a/src/sim/param.hh
+++ /dev/null
@@ -1,740 +0,0 @@
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Reinhardt
- */
-
-#ifndef __SIM_PARAM_HH__
-#define __SIM_PARAM_HH__
-
-#include <iostream>
-#include <list>
-#include <string>
-#include <vector>
-
-#include "sim/startup.hh"
-
-// forward decls
-class IniFile;
-class BaseParam;
-class SimObject;
-
-//
-// The context of a parameter definition... usually a subclass of
-// SimObjectBuilder (which derives from ParamContext), but abstracted
-// here to support more global simulator control parameters as well.
-//
-class ParamContext : protected StartupCallback
-{
-  protected:
-
-    // .ini file (database) for parameter lookup... initialized on call
-    // to parseParams()
-    IniFile *iniFilePtr;
-
-    // .ini file section for parameter lookup
-    const std::string iniSection;
-
-    typedef std::vector<BaseParam *> ParamList;
-
-    // list of parameters defined in this context
-    ParamList *paramList;
-
-    ParamList *getParamList() {
-        if (!paramList)
-            paramList = new ParamList;
-        return paramList;
-    }
-
-  public:
-
-    /// Constructor.
-    /// @param _iniSection Name of .ini section corresponding to this context.
-    /// @param _initPhase Initialization phase  (see InitPhase).
-    ParamContext(const std::string &_iniSection);
-    virtual ~ParamContext() {}
-
-    // add a parameter to the context... called from the parameter
-    // object's constructor (see BaseParam::BaseParam())
-    void addParam(BaseParam *);
-
-    // call parse() on all params in this context to convert string
-    // representations to parameter values
-    virtual void parseParams(IniFile &iniFile);
-
-    // Check parameter values for validity & consistency. Default
-    // implementation is no-op; derive subclass & override to add
-    // actual functionality here
-    virtual void checkParams();
-
-    // Clean up at end of execution: close file descriptors, etc.
-    // Default implementation is no-op; derive subclass & override to
-    // add actual functionality here
-    virtual void cleanup();
-
-    // dump parameter descriptions
-    void describeParams(std::ostream &);
-
-    // Display the parameters & values used
-    void showParams(std::ostream &);
-
-    // print context information for parameter error
-    virtual void printErrorProlog(std::ostream &);
-
-    // generate the name for this instance of this context (used as a
-    // prefix to create unique names in resolveSimObject()
-    virtual const std::string &getInstanceName() { return iniSection; }
-};
-
-
-//
-// Base class for all parameter objects
-//
-class BaseParam
-{
-  public:
-
-    ParamContext *context;
-    std::string name;
-    std::string description;	// text description for help message
-    bool wasSet;	// true if parameter was set by user
-    bool hasDefault;	// true if parameter has default value
-
-    BaseParam(ParamContext *_context, const std::string &_name,
-              const std::string &_description, bool _hasDefault)
-        : context(_context), name(_name), description(_description),
-          wasSet(false), hasDefault(_hasDefault)
-    {
-        context->addParam(this);
-    }
-
-    virtual ~BaseParam() {}
-
-    // a parameter is valid only if its value was set by the user or
-    // it has a default value
-    bool isValid() const
-    {
-        return (wasSet || hasDefault);
-    }
-
-    // set value by parsing string
-    virtual void parse(const std::string &s) = 0;
-
-    // display value to stream
-    virtual void showValue(std::ostream &) const = 0;
-
-    // display type to stream
-    virtual void showType(std::ostream &) const = 0;
-
-    // signal parse or usage error
-    virtual void die(const std::string &err) const;
-};
-
-//
-// Template classes to specialize parameters to specific types.
-//
-// Param<T> is for single-valued (scalar) parameters of type T.
-// VectorParam<T> is for multi-valued (vector) parameters of type T.
-// These are specified in the .ini file as a space-delimited list of
-// arguments.
-//
-template <class T>
-class Param : public BaseParam
-{
-  protected:
-
-    T value;
-
-  public:
-
-    // Param with default value: set value to default
-    Param(ParamContext *context,
-          const std::string &name, const std::string &description, T dfltValue)
-        : BaseParam(context, name, description, true),
-          value(dfltValue)
-    {
-    }
-
-    // Param with no default value: leave value uninitialized
-    Param(ParamContext *context,
-          const std::string &name, const std::string &description)
-        : BaseParam(context, name, description, false)
-    {
-    }
-
-    virtual ~Param() {}
-
-    operator T&()
-    {
-        // if we attempt to reference an invalid parameter (i.e., one
-        // with no default value that was not set by the user), die.
-        if (!isValid())
-            die("not found");
-        return value;
-    }
-
-    T returnValue() const { return value; }
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const;
-
-    // display type to stream
-    virtual void showType(std::ostream &) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s);
-};
-
-
-//
-// Template class for vector-valued parameters (lists)
-//
-template <class T>
-class VectorParam : public BaseParam
-{
-  protected:
-
-    std::vector<T> value;
-
-  public:
-
-    typedef typename std::vector<T>::size_type size_type;
-
-    // Param with default value: set value to default
-    VectorParam(ParamContext *context, const std::string &name,
-                const std::string &description,
-                const std::vector<T> &dfltValue)
-        : BaseParam(context, name, description, true),
-          value(dfltValue)
-    {
-    }
-
-    // Param with no default value: leave value uninitialized
-    VectorParam(ParamContext *context,
-                const std::string &name, const std::string &description)
-        : BaseParam(context, name, description, false)
-    {
-    }
-
-    virtual ~VectorParam() {}
-
-    // basic vector access methods
-    size_type size() const
-    {
-        if (!isValid())
-            die("not found");
-        return value.size();
-    }
-
-    const T &operator[](size_type n) const
-    {
-        if (!isValid())
-            die("not found");
-        return value[n];
-    }
-
-    // return reference to value vector
-    operator std::vector<T>&()
-    {
-        if (!isValid())
-            die("not found");
-        return value;
-    }
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const;
-
-    // display type to stream
-    virtual void showType(std::ostream &) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s);
-};
-
-//
-// Specialization of Param<int> and VectorParam<int> to handle
-// enumerated types is done in two ways, using SimpleEnumParam and
-// MappedEnumParam (and their vector counterparts,
-// SimpleEnumVectorParam and MappedEnumVectorParam).  SimpleEnumParam
-// takes an array of strings and maps them to integers based on array
-// index.  MappedEnumParam takes an array of string-to-int mappings,
-// allowing for mapping strings to non-contiguous integer values, or
-// mapping multiple strings to the same integer value.
-//
-// Both SimpleEnumParam and MappedEnumParam are implemented using a
-// single template class, EnumParam<Map>, which takes the type of the map
-// as a parameter (const char * or EnumParamMap).  Similarly,
-// SimpleEnumVectorParam and MappedEnumVectorParam are both
-// implemented using EnumVectorParam<Map>.
-//
-template <class Map>
-class EnumParam : public Param<int>
-{
-    const int num_values;
-    const Map *map;
-
-  public:
-
-    // Param with default value: set value to default
-    EnumParam(ParamContext *context,
-              const std::string &name, const std::string &description,
-              const Map *_map, int _num_values,
-              int dfltValue)
-        : Param<int>(context, name, description, dfltValue),
-          num_values(_num_values), map(_map)
-    {
-    }
-
-    // Param with no default value: leave value uninitialized
-    EnumParam(ParamContext *context,
-              const std::string &name, const std::string &description,
-              const Map *_map, int _num_values)
-        : Param<int>(context, name, description),
-          num_values(_num_values), map(_map)
-    {
-    }
-
-    virtual ~EnumParam() {}
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const;
-
-    // display type to stream
-    virtual void showType(std::ostream &) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s);
-};
-
-//
-// Vector counterpart to SimpleEnumParam
-//
-template <class Map>
-class EnumVectorParam : public VectorParam<int>
-{
-    const int num_values;
-    const Map *map;
-
-  public:
-
-    // Param with default value: set value to default
-    EnumVectorParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const Map *_map, int _num_values,
-                    std::vector<int> &dfltValue)
-        : VectorParam<int>(context, name, description, dfltValue),
-          num_values(_num_values), map(_map)
-    {
-    }
-
-    // Param with no default value: leave value uninitialized
-    EnumVectorParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const Map *_map, int _num_values)
-        : VectorParam<int>(context, name, description),
-          num_values(_num_values), map(_map)
-    {
-    }
-
-    virtual ~EnumVectorParam() {}
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const;
-
-    // display type to stream
-    virtual void showType(std::ostream &) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s);
-};
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class SimpleEnumParam : public EnumParam<const char *>
-{
-  public:
-
-    SimpleEnumParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const char **_map, int _num_values,
-                    ENUM dfltValue)
-        : EnumParam<const char *>(context, name, description,
-                                  _map, _num_values, (int)dfltValue)
-    {
-    }
-
-    SimpleEnumParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const char **_map, int _num_values)
-        : EnumParam<const char *>(context, name, description,
-                                  _map, _num_values)
-    {
-    }
-
-    operator ENUM() const
-    {
-        if (!isValid())
-            die("not found");
-        return (ENUM)value;
-    }
-};
-
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class SimpleEnumVectorParam : public EnumVectorParam<const char *>
-{
-  public:
-
-    // skip default value constructor: too much pain to convert
-    // vector<ENUM> initializer to vector<int>
-
-
-    SimpleEnumVectorParam(ParamContext *context,
-                          const std::string &name,
-                          const std::string &description,
-                          const char **_map, int _num_values)
-        : EnumVectorParam<const char *>(context, name, description,
-                                        _map, _num_values)
-    {
-    }
-
-    ENUM operator[](size_type n)
-    {
-        if (!isValid())
-            die("not found");
-        return (ENUM)value[n];
-    }
-};
-
-
-//
-// Handle enums via string-to-int map (see comment above).
-//
-
-// An array of string-to-int mappings must be supplied using the
-// following type.
-typedef struct {
-    const char *name;
-    int value;
-} EnumParamMap;
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class MappedEnumParam : public EnumParam<EnumParamMap>
-{
-  public:
-
-    MappedEnumParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const EnumParamMap *_map, int _num_values,
-                    ENUM dfltValue)
-        : EnumParam<EnumParamMap>(context, name, description,
-                                  _map, _num_values, (int)dfltValue)
-    {
-    }
-
-    MappedEnumParam(ParamContext *context,
-                    const std::string &name, const std::string &description,
-                    const EnumParamMap *_map, int _num_values)
-        : EnumParam<EnumParamMap>(context, name, description,
-                                  _map, _num_values)
-    {
-    }
-
-    operator ENUM()
-    {
-        if (!isValid())
-            die("not found");
-        return (ENUM)value[this->n];
-    }
-};
-
-
-// Specialize EnumParam for a particular enumeration type ENUM
-// (automates casting to get value of enum type)
-
-template <class ENUM>
-class MappedEnumVectorParam : public EnumVectorParam<EnumParamMap>
-{
-  public:
-
-    // skip default value constructor: too much pain to convert
-    // vector<ENUM> initializer to vector<int>
-
-
-    MappedEnumVectorParam(ParamContext *context,
-                          const std::string &name,
-                          const std::string &description,
-                          const EnumParamMap *_map, int _num_values)
-        : EnumVectorParam<EnumParamMap>(context, name, description,
-                                        _map, _num_values)
-    {
-    }
-
-    ENUM operator[](size_type n)
-    {
-        if (!isValid())
-            die("not found");
-        return (ENUM)value[n];
-    }
-};
-
-
-//
-// Parameters that point to other simulation objects (e.g. caches,
-// busses, etc.) are handled by specializing SimObjectBaseParam to the
-// specific subtype.  The main purpose of SimObjectBaseParam is to
-// provide a place to stick several helper functions common to all
-// SimObject-derived parameters.
-//
-class SimObjectBaseParam : public BaseParam
-{
-  public:
-
-    SimObjectBaseParam(ParamContext *context, const std::string &name,
-                       const std::string &description, bool hasDefault)
-        : BaseParam(context, name, description, hasDefault)
-    {
-    }
-
-    virtual ~SimObjectBaseParam() {}
-
-    // helper function for SimObjectParam<T>::showValue()
-    void showValue(std::ostream &os, SimObject *obj) const;
-
-    // helper function for SimObjectParam<T>::parse()
-    void parse(const std::string &s, SimObject *&value);
-
-    // helper function for SimObjectParam<T>::parse()
-    void parse(const std::string &s, std::vector<SimObject *>&value_vec);
-};
-
-
-//
-// Parameter to a specific type of SimObject.  Note that T must be a
-// pointer to a class derived from SimObject (e.g., <CPU *>).
-//
-
-template <class T> class SimObjectParam;
-
-template <class T>
-class SimObjectParam<T *> : public SimObjectBaseParam
-{
-  protected:
-
-    T *value;
-
-  public:
-
-    // initialization w/o default
-    SimObjectParam(ParamContext *context,
-                   const std::string &name, const std::string &description)
-        : SimObjectBaseParam(context, name, description, false)
-    {
-    }
-
-    // initialization wit=h default
-    SimObjectParam(ParamContext *context,
-                   const std::string &name, const std::string &description,
-                   T *dfltValue)
-        : SimObjectBaseParam(context, name, description, true),
-          value(dfltValue)
-    {
-    }
-
-    virtual ~SimObjectParam() {}
-
-    // convert to pointer
-    operator T*()
-    {
-        if (!isValid())
-            die("not found");
-        return value;
-    }
-
-    T *operator->() const
-    {
-        if (!isValid())
-            die("not found");
-        return value;
-    }
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const
-    {
-        SimObjectBaseParam::showValue(os, value);
-    }
-
-    // display type to stream: see REGISTER_SIM_OBJECT macro in
-    // sim_object.hh for declaration
-    virtual void showType(std::ostream &os) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s)
-    {
-        SimObject *so_ptr;
-        // first parse to generic SimObject *
-        SimObjectBaseParam::parse(s, so_ptr);
-        // now dynamic_cast to specific derived type
-        value = dynamic_cast<T *>(so_ptr);
-        // check for failure of dynamic_cast
-        if (value == NULL && so_ptr != NULL)
-            die("not of appropriate type");
-    }
-};
-
-
-//
-// Vector counterpart to SimObjectParam<T>
-//
-
-template <class T> class SimObjectVectorParam;
-
-template <class T>
-class SimObjectVectorParam<T *> : public SimObjectBaseParam
-{
-  protected:
-
-    std::vector<T *> value;
-
-  public:
-
-    typedef typename std::vector<T *>::size_type size_type;
-
-    SimObjectVectorParam(ParamContext *context,
-                         const std::string &name,
-                         const std::string &description)
-        : SimObjectBaseParam(context, name, description, false)
-    {
-    }
-
-    SimObjectVectorParam(ParamContext *context,
-                         const std::string &name,
-                         const std::string &description,
-                         std::vector<T *> dfltValue)
-        : SimObjectBaseParam(context, name, description, true),
-          value(dfltValue)
-    {
-    }
-
-    virtual ~SimObjectVectorParam() {}
-
-    // basic vector access methods
-    size_type size() const
-    {
-        if (!isValid())
-            die("not found");
-        return value.size();
-    }
-
-    T *&operator[](size_type n)
-    {
-        if (!isValid())
-            die("not found");
-        return value[n];
-    }
-
-    // return reference to value vector
-    operator std::vector<T *>&()
-    {
-        if (!isValid())
-            die("not found");
-        return value;
-    }
-
-    // display value to stream
-    virtual void showValue(std::ostream &os) const
-    {
-        for (int i = 0; i < value.size(); i++) {
-            if (i != 0)
-                os << " ";
-            SimObjectBaseParam::showValue(os, value[i]);
-        }
-    }
-
-    // display type to stream: see
-    virtual void showType(std::ostream &os) const;
-
-    // set value by parsing string
-    virtual void parse(const std::string &s)
-    {
-        std::vector<SimObject *> so_ptr_vec;
-        // first parse to generic SimObject * vector (from SimObjectBaseParam)
-        SimObjectBaseParam::parse(s, so_ptr_vec);
-
-        value.resize(so_ptr_vec.size());
-
-        for (int i = 0; i < so_ptr_vec.size(); ++i) {
-            // now dynamic_cast to specific derived type
-            value[i] = dynamic_cast<T *>(so_ptr_vec[i]);
-            // check for failure of dynamic_cast
-            if (value[i] == NULL && so_ptr_vec[i] != NULL)
-                die("not of appropriate type");
-        }
-    }
-};
-
-//
-// Macro to define showType() methods for SimObjectParam &
-// SimObjectVectorParam.  Can't do this automatically as it requires a
-// string name for the type, which you can't get from a template
-// argument.  For concrete derived SimObject types, this macro is
-// automatically invoked by REGISTER_SIM_OBJECT() (see sim_object.hh).
-//
-#define DEFINE_SIM_OBJECT_CLASS_NAME(CLASS_NAME, OBJ_CLASS)		\
-template<>								\
-void									\
-SimObjectParam<OBJ_CLASS *>::showType(std::ostream &os)	const		\
-{									\
-    os << CLASS_NAME;							\
-}									\
-                                                                        \
-template<>								\
-void									\
-SimObjectVectorParam<OBJ_CLASS *>::showType(std::ostream &os) const	\
-{									\
-    os << "vector of " << CLASS_NAME;					\
-}
-
-
-//
-// Declarations for low-level parsing & displaying functions.  These
-// are used internally, but should not be used directly by clients of
-// the parameter mechanism, but are declared here so they can be
-// shared with the serialization code (see sim/serialize.cc).
-template <class T> bool parseParam(const std::string &str, T &data);
-template <class T> void showParam(std::ostream &os, const T &data);
-
-void parseTime(const std::vector<int> &time, struct tm *tm);
-#endif // _SIM_PARAM_HH_
diff --git a/src/sim/process.cc b/src/sim/process.cc
index 8b273d591..7343039df 100644
--- a/src/sim/process.cc
+++ b/src/sim/process.cc
@@ -45,7 +45,7 @@
 #include "mem/page_table.hh"
 #include "mem/physical.hh"
 #include "mem/translating_port.hh"
-#include "sim/builder.hh"
+#include "params/LiveProcess.hh"
 #include "sim/process.hh"
 #include "sim/process_impl.hh"
 #include "sim/stats.hh"
@@ -312,14 +312,6 @@ Process::unserialize(Checkpoint *cp, const std::string &section)
 }
 
 
-//
-// need to declare these here since there is no concrete Process type
-// that can be constructed (i.e., no REGISTER_SIM_OBJECT() macro call,
-// which is where these get declared for concrete types).
-//
-DEFINE_SIM_OBJECT_CLASS_NAME("Process", Process)
-
-
 ////////////////////////////////////////////////////////////////////////
 //
 // LiveProcess member definitions
@@ -413,8 +405,9 @@ LiveProcess::argsInit(int intSize, int pageSize)
     copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
     copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
 
-    threadContexts[0]->setIntReg(ArgumentReg0, argc);
-    threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
+    assert(NumArgumentRegs >= 2);
+    threadContexts[0]->setIntReg(ArgumentReg[0], argc);
+    threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
     threadContexts[0]->setIntReg(StackPointerReg, stack_min);
 
     Addr prog_entry = objFile->entryPoint();
@@ -551,46 +544,8 @@ LiveProcess::create(const std::string &nm, System *system, int stdin_fd,
     return process;
 }
 
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(LiveProcess)
-
-    VectorParam<string> cmd;
-    Param<string> executable;
-    Param<string> input;
-    Param<string> output;
-    VectorParam<string> env;
-    Param<string> cwd;
-    SimObjectParam<System *> system;
-    Param<uint64_t> uid;
-    Param<uint64_t> euid;
-    Param<uint64_t> gid;
-    Param<uint64_t> egid;
-    Param<uint64_t> pid;
-    Param<uint64_t> ppid;
-
-END_DECLARE_SIM_OBJECT_PARAMS(LiveProcess)
-
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(LiveProcess)
-
-    INIT_PARAM(cmd, "command line (executable plus arguments)"),
-    INIT_PARAM(executable, "executable (overrides cmd[0] if set)"),
-    INIT_PARAM(input, "filename for stdin (dflt: use sim stdin)"),
-    INIT_PARAM(output, "filename for stdout/stderr (dflt: use sim stdout)"),
-    INIT_PARAM(env, "environment settings"),
-    INIT_PARAM(cwd, "current working directory"),
-    INIT_PARAM(system, "system"),
-    INIT_PARAM(uid, "user id"),
-    INIT_PARAM(euid, "effective user id"),
-    INIT_PARAM(gid, "group id"),
-    INIT_PARAM(egid, "effective group id"),
-    INIT_PARAM(pid, "process id"),
-    INIT_PARAM(ppid, "parent process id")
-
-END_INIT_SIM_OBJECT_PARAMS(LiveProcess)
-
-
-CREATE_SIM_OBJECT(LiveProcess)
+LiveProcess *
+LiveProcessParams::create()
 {
     string in = input;
     string out = output;
@@ -612,12 +567,9 @@ CREATE_SIM_OBJECT(LiveProcess)
 
     stderr_fd = (stdout_fd != STDOUT_FILENO) ? stdout_fd : STDERR_FILENO;
 
-    return LiveProcess::create(getInstanceName(), system,
+    return LiveProcess::create(name, system,
                                stdin_fd, stdout_fd, stderr_fd,
                                (string)executable == "" ? cmd[0] : executable,
                                cmd, env, cwd,
                                uid, euid, gid, egid, pid, ppid);
 }
-
-
-REGISTER_SIM_OBJECT("LiveProcess", LiveProcess)
diff --git a/src/sim/root.cc b/src/sim/root.cc
index f4743af0a..15f73b15b 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -36,28 +36,17 @@
 #include <vector>
 
 #include "base/misc.hh"
-#include "sim/builder.hh"
+#include "params/Root.hh"
 #include "sim/sim_object.hh"
 
 // Dummy Object
 struct Root : public SimObject
 {
-    Root(const std::string &name) : SimObject(name) {}
+    Root(RootParams *params) : SimObject(params) {}
 };
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(Root)
-
-    Param<int> dummy; // needed below
-
-END_DECLARE_SIM_OBJECT_PARAMS(Root)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(Root)
-
-    INIT_PARAM(dummy, "")  // All SimObjects must have params
-
-END_INIT_SIM_OBJECT_PARAMS(Root)
-
-CREATE_SIM_OBJECT(Root)
+Root *
+RootParams::create()
 {
     static bool created = false;
     if (created)
@@ -65,7 +54,5 @@ CREATE_SIM_OBJECT(Root)
 
     created = true;
 
-    return  new Root(getInstanceName());
+    return new Root(this);
 }
-
-REGISTER_SIM_OBJECT("Root", Root)
diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc
index d32bb1142..a01e053b9 100644
--- a/src/sim/serialize.cc
+++ b/src/sim/serialize.cc
@@ -46,7 +46,6 @@
 #include "base/str.hh"
 #include "base/trace.hh"
 #include "sim/eventq.hh"
-#include "sim/param.hh"
 #include "sim/serialize.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
@@ -59,6 +58,101 @@ using namespace std;
 
 extern SimObject *resolveSimObject(const string &);
 
+//
+// The base implementations use to_number for parsing and '<<' for
+// displaying, suitable for integer types.
+//
+template <class T>
+bool
+parseParam(const string &s, T &value)
+{
+    return to_number(s, value);
+}
+
+template <class T>
+void
+showParam(ostream &os, const T &value)
+{
+    os << value;
+}
+
+//
+// Template specializations:
+// - char (8-bit integer)
+// - floating-point types
+// - bool
+// - string
+//
+
+// Treat 8-bit ints (chars) as ints on output, not as chars
+template <>
+void
+showParam(ostream &os, const char &value)
+{
+    os << (int)value;
+}
+
+
+template <>
+void
+showParam(ostream &os, const unsigned char &value)
+{
+    os << (unsigned int)value;
+}
+
+
+// Use sscanf() for FP types as to_number() only handles integers
+template <>
+bool
+parseParam(const string &s, float &value)
+{
+    return (sscanf(s.c_str(), "%f", &value) == 1);
+}
+
+template <>
+bool
+parseParam(const string &s, double &value)
+{
+    return (sscanf(s.c_str(), "%lf", &value) == 1);
+}
+
+template <>
+bool
+parseParam(const string &s, bool &value)
+{
+    const string &ls = to_lower(s);
+
+    if (ls == "true") {
+        value = true;
+        return true;
+    }
+
+    if (ls == "false") {
+        value = false;
+        return true;
+    }
+
+    return false;
+}
+
+// Display bools as strings
+template <>
+void
+showParam(ostream &os, const bool &value)
+{
+    os << (value ? "true" : "false");
+}
+
+
+// String requires no processing to speak of
+template <>
+bool
+parseParam(const string &s, string &value)
+{
+    value = s;
+    return true;
+}
+
 int Serializable::ckptMaxCount = 0;
 int Serializable::ckptCount = 0;
 int Serializable::ckptPrevCount = -1;
diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc
index a4457a11c..1949e88dd 100644
--- a/src/sim/sim_events.cc
+++ b/src/sim/sim_events.cc
@@ -33,7 +33,6 @@
 #include "base/callback.hh"
 #include "base/hostinfo.hh"
 #include "sim/eventq.hh"
-#include "sim/param.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/startup.hh"
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 434fcffe6..67604e24c 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -40,7 +40,6 @@
 #include "sim/host.hh"
 #include "sim/sim_object.hh"
 #include "sim/stats.hh"
-#include "sim/param.hh"
 
 using namespace std;
 
@@ -59,7 +58,7 @@ SimObject::SimObjectList SimObject::simObjectList;
 //
 // SimObject constructor: used to maintain static simObjectList
 //
-SimObject::SimObject(Params *p)
+SimObject::SimObject(const Params *p)
     : _params(p)
 {
 #ifdef DEBUG
@@ -70,13 +69,18 @@ SimObject::SimObject(Params *p)
     state = Running;
 }
 
-//
-// SimObject constructor: used to maintain static simObjectList
-//
+SimObjectParams *
+makeParams(const string &name)
+{
+    SimObjectParams *params = new SimObjectParams;
+    params->name = name;
+
+    return params;
+}
+
 SimObject::SimObject(const string &_name)
-    : _params(new Params)
+    : _params(makeParams(_name))
 {
-    _params->name = _name;
 #ifdef DEBUG
     doDebugBreak = false;
 #endif
@@ -272,5 +276,3 @@ SimObject::takeOverFrom(BaseCPU *cpu)
 {
     panic("Unimplemented!");
 }
-
-DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject)
diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh
index 536e761e5..2e99a85bf 100644
--- a/src/sim/sim_object.hh
+++ b/src/sim/sim_object.hh
@@ -41,6 +41,7 @@
 #include <vector>
 #include <iostream>
 
+#include "params/SimObject.hh"
 #include "sim/serialize.hh"
 #include "sim/startup.hh"
 
@@ -55,33 +56,19 @@ class Event;
 class SimObject : public Serializable, protected StartupCallback
 {
   public:
-    struct Params {
-        std::string name;
-    };
-
     enum State {
         Running,
         Draining,
         Drained
     };
 
-    enum MemoryMode {
-        Invalid=0,
-        Atomic,
-        Timing
-    };
-
   private:
     State state;
 
   protected:
-    Params *_params;
-
     void changeState(State new_state) { state = new_state; }
 
   public:
-    const Params *params() const { return _params; }
-
     State getState() { return state; }
 
   private:
@@ -90,10 +77,14 @@ class SimObject : public Serializable, protected StartupCallback
     // list of all instantiated simulation objects
     static SimObjectList simObjectList;
 
+  protected:
+    const SimObjectParams *_params;
+
   public:
-    SimObject(Params *_params);
+    typedef SimObjectParams Params;
+    const Params *params() const { return _params; }
+    SimObject(const Params *_params);
     SimObject(const std::string &_name);
-
     virtual ~SimObject() {}
 
     virtual const std::string name() const { return params()->name; }
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 2d0eaaf5b..3c4746e93 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -40,12 +40,13 @@
 #include "cpu/thread_context.hh"
 #include "mem/mem_object.hh"
 #include "mem/physical.hh"
-#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "sim/system.hh"
 #if FULL_SYSTEM
 #include "arch/vtophys.hh"
 #include "kern/kernel_stats.hh"
+#else
+#include "params/System.hh"
 #endif
 
 using namespace std;
@@ -90,14 +91,14 @@ System::System(Params *p)
     /**
      * Load the kernel code into memory
      */
-    if (params()->kernel_path == "") {
+    if (params()->kernel == "") {
         warn("No kernel set for full system simulation. Assuming you know what"
                 " you're doing...\n");
     } else {
         // Load kernel code
-        kernel = createObjectFile(params()->kernel_path);
+        kernel = createObjectFile(params()->kernel);
         if (kernel == NULL)
-            fatal("Could not load kernel file %s", params()->kernel_path);
+            fatal("Could not load kernel file %s", params()->kernel);
 
         // Load program sections into memory
         kernel->loadSections(&functionalPort, LoadAddrMask);
@@ -146,7 +147,7 @@ int rgdb_wait = -1;
 int rgdb_enable = true;
 
 void
-System::setMemoryMode(MemoryMode mode)
+System::setMemoryMode(Enums::MemoryMode mode)
 {
     assert(getState() == Drained);
     memoryMode = mode;
@@ -269,39 +270,16 @@ printSystems()
 const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
     "timing"};
 
-#if FULL_SYSTEM
-
-// In full system mode, only derived classes (e.g. AlphaLinuxSystem)
-// can be created directly.
-
-DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
-
-#else
-
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
-
-    SimObjectParam<PhysicalMemory *> physmem;
-    SimpleEnumParam<System::MemoryMode> mem_mode;
-
-END_DECLARE_SIM_OBJECT_PARAMS(System)
-
-BEGIN_INIT_SIM_OBJECT_PARAMS(System)
-
-    INIT_PARAM(physmem, "physical memory"),
-    INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
-            System::MemoryModeStrings)
-
-END_INIT_SIM_OBJECT_PARAMS(System)
+#if !FULL_SYSTEM
 
-CREATE_SIM_OBJECT(System)
+System *
+SystemParams::create()
 {
     System::Params *p = new System::Params;
-    p->name = getInstanceName();
+    p->name = name;
     p->physmem = physmem;
     p->mem_mode = mem_mode;
     return new System(p);
 }
 
-REGISTER_SIM_OBJECT("System", System)
-
 #endif
diff --git a/src/sim/system.hh b/src/sim/system.hh
index 758da709e..197d9027b 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -41,7 +41,9 @@
 #include "base/statistics.hh"
 #include "config/full_system.hh"
 #include "cpu/pc_event.hh"
+#include "enums/MemoryMode.hh"
 #include "mem/port.hh"
+#include "params/System.hh"
 #include "sim/sim_object.hh"
 #if FULL_SYSTEM
 #include "kern/system_events.hh"
@@ -68,13 +70,18 @@ class System : public SimObject
 
     static const char *MemoryModeStrings[3];
 
-    SimObject::MemoryMode getMemoryMode() { assert(memoryMode); return memoryMode; }
+    Enums::MemoryMode
+    getMemoryMode()
+    {
+        assert(memoryMode);
+        return memoryMode;
+    }
 
     /** Change the memory mode of the system. This should only be called by the
      * python!!
      * @param mode Mode to change to (atomic/timing)
      */
-    void setMemoryMode(SimObject::MemoryMode mode);
+    void setMemoryMode(Enums::MemoryMode mode);
 
     PhysicalMemory *physmem;
     PCEventQueue pcEventQueue;
@@ -122,8 +129,7 @@ class System : public SimObject
 #endif // FULL_SYSTEM
 
   protected:
-
-    SimObject::MemoryMode memoryMode;
+    Enums::MemoryMode memoryMode;
 
 #if FULL_SYSTEM
     /**
@@ -164,22 +170,7 @@ class System : public SimObject
     bool breakpoint();
 
   public:
-    struct Params
-    {
-        std::string name;
-        PhysicalMemory *physmem;
-        SimObject::MemoryMode mem_mode;
-
-#if FULL_SYSTEM
-        Tick boot_cpu_frequency;
-        std::string boot_osflags;
-        uint64_t init_param;
-
-        std::string kernel_path;
-        std::string readfile;
-        std::string symbolfile;
-#endif
-    };
+    typedef SystemParams Params;
 
   protected:
     Params *_params;