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author | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:34 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2011-06-19 21:43:34 -0400 |
commit | 17f5749dbbb007ee56b60c27f15f43e2e5250408 (patch) | |
tree | 75a4c123d3aeb728a8340785fd1caeee5653dc0c /src | |
parent | 2a59fcfbe9f4d68bfe3dcb263acf68b998e0705c (diff) | |
download | gem5-17f5749dbbb007ee56b60c27f15f43e2e5250408.tar.xz |
inorder: ISA-zero reg handling
ignore writes to the ISA zero register
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/inorder/cpu.cc | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 01eab9af7..f1c531c53 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -1135,10 +1135,16 @@ InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid) void InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid) { - DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n", - tid, reg_idx, val); + if (reg_idx == TheISA::ZeroReg) { + DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg " + "(Int. Reg %i) to %x\n", tid, reg_idx, val); + return; + } else { + DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n", + tid, reg_idx, val); - intRegs[tid][reg_idx] = val; + intRegs[tid][reg_idx] = val; + } } |