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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-09-03 07:43:06 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-09-03 07:43:06 -0400 |
| commit | 346fe7337009980566e023a60a09391ed893a5c0 (patch) | |
| tree | 3fe6cae924a1fd6dae410fb83f7c837f6392eb34 /src | |
| parent | 1c0ae90027f0aea96389d0b82f2c732df72fc06c (diff) | |
| download | gem5-346fe7337009980566e023a60a09391ed893a5c0.tar.xz | |
dev: seperate legacy io offsets from PCI offset
The PC platform has a single IO range that is used both legacy IO and PCI IO
while other platforms may use seperate regions. Provide another mechanism to
configure the legacy IO base address range and set it to the PCI IO address
range for x86.
Diffstat (limited to 'src')
| -rw-r--r-- | src/dev/Pci.py | 1 | ||||
| -rw-r--r-- | src/dev/pcidev.cc | 2 | ||||
| -rw-r--r-- | src/dev/x86/SouthBridge.py | 1 |
3 files changed, 3 insertions, 1 deletions
diff --git a/src/dev/Pci.py b/src/dev/Pci.py index 79ea1f68a..ef7137186 100644 --- a/src/dev/Pci.py +++ b/src/dev/Pci.py @@ -98,6 +98,7 @@ class PciDevice(DmaDevice): BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO") BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO") BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO") + LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO") CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") SubsystemID = Param.UInt16(0x00, "Subsystem ID") diff --git a/src/dev/pcidev.cc b/src/dev/pcidev.cc index a24fa8da8..adc12bb55 100644 --- a/src/dev/pcidev.cc +++ b/src/dev/pcidev.cc @@ -213,7 +213,7 @@ PciDevice::PciDevice(const Params *p) for (int i = 0; i < 6; ++i) { if (legacyIO[i]) { - BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i])); + BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]); config.baseAddr[i] = 0; } else { BARAddrs[i] = 0; diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py index 45c49ce3a..911853dd5 100644 --- a/src/dev/x86/SouthBridge.py +++ b/src/dev/x86/SouthBridge.py @@ -84,6 +84,7 @@ class SouthBridge(SimObject): ide.ProgIF = 0x80 ide.InterruptLine = 14 ide.InterruptPin = 1 + ide.LegacyIOBase = x86IOAddress(0) def attachIO(self, bus, dma_ports): # Route interupt signals |