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authorGabe Black <gblack@eecs.umich.edu>2010-11-23 06:11:50 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-11-23 06:11:50 -0500
commit40d434d5516affffe9ded9365e0d2da060aa7c78 (patch)
tree095a480b2f025a4e113d09b693a6cb3c7ccf2040 /src
parent3cd349f44305d6ca9496f7f626f0f4f939bd84ad (diff)
downloadgem5-40d434d5516affffe9ded9365e0d2da060aa7c78.tar.xz
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/BaseCPU.py4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 402831f5a..868f47015 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -167,7 +167,7 @@ class BaseCPU(MemObject):
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) < 6)
+ assert(len(self._mem_ports) < 8)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
@@ -176,6 +176,8 @@ class BaseCPU(MemObject):
if buildEnv['FULL_SYSTEM']:
if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
+ if buildEnv['TARGET_ISA'] == 'x86':
+ self._mem_ports += ["interrupts.pio", "interrupts.int_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)