diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-13 12:13:44 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-13 12:13:44 -0400 |
commit | 8127c4e7bf5fa95b3d06dd0e10ca5b7d32261064 (patch) | |
tree | cd4ec3f82a01a2ae2ed07b8ddb11150463fbe88e /src | |
parent | 4b802a09c52ca2a2274a232ba5a29936de8ec3a9 (diff) | |
download | gem5-8127c4e7bf5fa95b3d06dd0e10ca5b7d32261064.tar.xz |
misc: Fix issues flagged by gcc 6
A few warnings (and thus errors) pop up after being added to -Wall:
1. -Wmisleading-indentation
In the auto-generated code there were instances of if/else blocks that
were not indented to gcc's liking. This is addressed by adding braces.
2. -Wshift-negative-value
gcc is clever enougn to consider ~0 a negative constant, and
rightfully complains. This is addressed by using mask() which
explicitly casts to unsigned before shifting.
That is all. Porting done.
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/arm/isa/insts/neon.isa | 15 | ||||
-rw-r--r-- | src/mem/ruby/system/DMASequencer.cc | 2 |
2 files changed, 10 insertions, 7 deletions
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index 1b20c660d..163b71c13 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -2939,29 +2939,32 @@ let {{ twoRegShiftInst("vrsra", "NVrsraQ", "SimdShiftAccOp", allTypes, 4, vrsraCode, True) vsriCode = ''' - if (imm >= sizeof(Element) * 8) + if (imm >= sizeof(Element) * 8) { destElem = destElem; - else + } else { destElem = (srcElem1 >> imm) | (destElem & ~mask(sizeof(Element) * 8 - imm)); + } ''' twoRegShiftInst("vsri", "NVsriD", "SimdShiftOp", unsignedTypes, 2, vsriCode, True) twoRegShiftInst("vsri", "NVsriQ", "SimdShiftOp", unsignedTypes, 4, vsriCode, True) vshlCode = ''' - if (imm >= sizeof(Element) * 8) + if (imm >= sizeof(Element) * 8) { destElem = (srcElem1 << (sizeof(Element) * 8 - 1)) << 1; - else + } else { destElem = srcElem1 << imm; + } ''' twoRegShiftInst("vshl", "NVshlD", "SimdShiftOp", unsignedTypes, 2, vshlCode) twoRegShiftInst("vshl", "NVshlQ", "SimdShiftOp", unsignedTypes, 4, vshlCode) vsliCode = ''' - if (imm >= sizeof(Element) * 8) + if (imm >= sizeof(Element) * 8) { destElem = destElem; - else + } else { destElem = (srcElem1 << imm) | (destElem & mask(imm)); + } ''' twoRegShiftInst("vsli", "NVsliD", "SimdShiftOp", unsignedTypes, 2, vsliCode, True) twoRegShiftInst("vsli", "NVsliQ", "SimdShiftOp", unsignedTypes, 4, vsliCode, True) diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc index 6e708a927..3b0304158 100644 --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -45,7 +45,7 @@ DMASequencer::init() { RubyPort::init(); m_is_busy = false; - m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); + m_data_block_mask = mask(RubySystem::getBlockSizeBits()); for (const auto &s_port : slave_ports) s_port->sendRangeChange(); |