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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:11 -0500
commitaade63a8fec1bf3e302ccce630c718a79d7b3907 (patch)
treebd28a7a2b637d0308e8ba9d4875a11fba1af9b12 /src
parenta8b56b452c62d761a698d91cc16c1d93bfe14204 (diff)
downloadgem5-aade63a8fec1bf3e302ccce630c718a79d7b3907.tar.xz
ARM: Implement the VMRS instruction.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/isa/insts/fp.isa7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index 7d0fbed85..0beb167dd 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -49,4 +49,11 @@ let {{
header_output += RegRegOpDeclare.subst(vmsrIop);
decoder_output += RegRegOpConstructor.subst(vmsrIop);
exec_output += PredOpExecute.subst(vmsrIop);
+
+ vmrsIop = InstObjParams("vmrs", "Vmrs", "RegRegOp",
+ { "code": "Dest = MiscOp1;",
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegOpDeclare.subst(vmrsIop);
+ decoder_output += RegRegOpConstructor.subst(vmrsIop);
+ exec_output += PredOpExecute.subst(vmrsIop);
}};