summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorNikos Nikoleris <nikos.nikoleris@arm.com>2016-10-26 11:07:27 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-03-03 14:09:37 +0000
commitce2a0076c962a902f34442010f4373f7347a0156 (patch)
tree31d14ab01813fecc9b3d8f12deba1de5cdf0e6cf /src
parentceb3bd9733d094b7c7d659ec5990fda26c2da27c (diff)
downloadgem5-ce2a0076c962a902f34442010f4373f7347a0156.tar.xz
mem: Use pkt::getBlockAddr instead of BaseCace::blockAlign
Change-Id: I0ed4e528cb750a323facdc811dde7f0ed1ff228e Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/base.hh8
-rw-r--r--src/mem/cache/cache.cc12
2 files changed, 8 insertions, 12 deletions
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 4b89be967..2787eea8c 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -484,15 +484,11 @@ class BaseCache : public MemObject
return blkSize;
}
-
- Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
-
-
const AddrRangeList &getAddrRanges() const { return addrRanges; }
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
{
- MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
+ MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
pkt, time, order++,
allocOnFill(pkt->cmd));
@@ -513,7 +509,7 @@ class BaseCache : public MemObject
// should only see writes or clean evicts here
assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
- Addr blk_addr = blockAlign(pkt->getAddr());
+ Addr blk_addr = pkt->getBlockAddr(blkSize);
WriteQueueEntry *wq_entry =
writeBuffer.findMatch(blk_addr, pkt->isSecure());
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 5f7802030..09148100e 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -737,7 +737,7 @@ Cache::recvTimingReq(PacketPtr pkt)
} else {
// miss
- Addr blk_addr = blockAlign(pkt->getAddr());
+ Addr blk_addr = pkt->getBlockAddr(blkSize);
// ignore any existing MSHR if we are dealing with an
// uncacheable request
@@ -961,7 +961,7 @@ Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
}
// the packet should be block aligned
- assert(pkt->getAddr() == blockAlign(pkt->getAddr()));
+ assert(pkt->getAddr() == pkt->getBlockAddr(blkSize));
pkt->allocate();
DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(),
@@ -1149,7 +1149,7 @@ Cache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
return;
}
- Addr blk_addr = blockAlign(pkt->getAddr());
+ Addr blk_addr = pkt->getBlockAddr(blkSize);
bool is_secure = pkt->isSecure();
CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
@@ -1731,7 +1731,7 @@ Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
#endif
// When handling a fill, we should have no writes to this line.
- assert(addr == blockAlign(addr));
+ assert(addr == pkt->getBlockAddr(blkSize));
assert(!writeBuffer.findMatch(addr, is_secure));
if (blk == nullptr) {
@@ -2092,7 +2092,7 @@ Cache::recvTimingSnoopReq(PacketPtr pkt)
bool is_secure = pkt->isSecure();
CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
- Addr blk_addr = blockAlign(pkt->getAddr());
+ Addr blk_addr = pkt->getBlockAddr(blkSize);
MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
// Update the latency cost of the snoop so that the crossbar can
@@ -2281,7 +2281,7 @@ Cache::getNextQueueEntry()
// If we have a miss queue slot, we can try a prefetch
PacketPtr pkt = prefetcher->getPacket();
if (pkt) {
- Addr pf_addr = blockAlign(pkt->getAddr());
+ Addr pf_addr = pkt->getBlockAddr(blkSize);
if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
!mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
!writeBuffer.findMatch(pf_addr, pkt->isSecure())) {