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authorKevin Lim <ktlim@umich.edu>2006-06-08 17:04:41 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-08 17:04:41 -0400
commitf5b6aef154c39b7d0a6c8badac5bb40daa0a0827 (patch)
tree7e94184cce80535154fccf39c6ee267a7b9c00c3 /src
parent1ef5585feeed641b20d0fbf4fe89ec6b1daaced5 (diff)
downloadgem5-f5b6aef154c39b7d0a6c8badac5bb40daa0a0827.tar.xz
Tell checker that an instruction is completed prior once it does the access to memory. As long as the checker does not access memory to verify the store's data (currently impossible in the O3 model), this will work fine.
src/cpu/o3/lsq_unit_impl.hh: Tell checker that an instruction is completed prior once it does the access to memory. --HG-- extra : convert_revision : 1d4bbac4b35fbd355f300eab76f29b38b5bc88cb
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 083217d26..62bb96610 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -633,6 +633,14 @@ LSQUnit<Impl>::writebackStores()
assert(!storeQueue[storeWBIdx].inst->isStoreConditional());
// Non-store conditionals do not need a writeback.
state->noWB = true;
+
+ // The store is basically completed at this time. This
+ // only works so long as the checker doesn't try to
+ // verify the value in memory for stores.
+ storeQueue[storeWBIdx].inst->setCompleted();
+ if (cpu->checker) {
+ cpu->checker->tick(storeQueue[storeWBIdx].inst);
+ }
}
if (data_pkt->result != Packet::Success) {