Merge zizzer.eecs.umich.edu:/bk/newmem

into  ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

--HG--
extra : convert_revision : f2fac2b1a09e709021cd8382a9fbe805df2177ef

10 files changed, 39 insertions, 34 deletions

diff --git a/src/SConscript b/src/SConscript
index 34c5453b7..7a3b25c92 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -277,9 +277,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
     if strip:
         stripped_bin = bin + '.stripped'
         if sys.platform == 'sunos5':
-            newEnv.Command(stripped_bin, bin, 'cp $SOURCE $TARGET; strip $TARGET')
+            cmd = 'cp $SOURCE $TARGET; strip $TARGET'
         else:
-            newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
+            cmd = 'strip $SOURCE -o $TARGET'
+        newEnv.Command(stripped_bin, bin, cmd)
         bin = stripped_bin
     targets = newEnv.Concat(exe, [bin, 'm5py.zip'])
     newEnv.M5Binary = targets[0]
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 078ae1283..f86313da0 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -269,12 +269,10 @@ Tick
 BaseCPU::nextCycle(Tick begin_tick)
 {
     Tick next_tick = begin_tick;
-    next_tick -= (next_tick % clock);
+    if (next_tick % clock != 0)
+        next_tick = next_tick - (next_tick % clock) + clock;
     next_tick += phase;
 
-    while (next_tick < curTick)
-        next_tick += clock;
-
     assert(next_tick >= curTick);
     return next_tick;
 }
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e031faefa..e691cfe5d 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -55,7 +55,7 @@ class DerivO3CPU(BaseCPU):
             checker.itb = Parent.itb
             checker.dtb = Parent.dtb
 
-    cachePorts = Param.Unsigned("Cache Ports")
+    cachePorts = Param.Unsigned(200, "Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
     _mem_ports = ['icache_port', 'dcache_port']
@@ -137,15 +137,15 @@ class DerivO3CPU(BaseCPU):
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
 
-    smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
-    smtFetchPolicy = Param.String("SMT Fetch policy")
-    smtLSQPolicy    = Param.String("SMT LSQ Sharing Policy")
-    smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
-    smtIQPolicy    = Param.String("SMT IQ Sharing Policy")
-    smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
-    smtROBPolicy   = Param.String("SMT ROB Sharing Policy")
-    smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
-    smtCommitPolicy = Param.String("SMT Commit Policy")
+    smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
+    smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
+    smtLSQPolicy    = Param.String('Partitioned', "SMT LSQ Sharing Policy")
+    smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
+    smtIQPolicy    = Param.String('Partitioned', "SMT IQ Sharing Policy")
+    smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
+    smtROBPolicy   = Param.String('Partitioned', "SMT ROB Sharing Policy")
+    smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
+    smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
     def addPrivateSplitL1Caches(self, ic, dc):
         BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index a775b66d5..9e1b5d132 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -204,19 +204,17 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
         _status = Idle;
     }
 
-    checker = NULL;
-
-    if (params->checker) {
 #if USE_CHECKER
+    if (params->checker) {
         BaseCPU *temp_checker = params->checker;
         checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
 #if FULL_SYSTEM
         checker->setSystem(params->system);
 #endif
-#else
-        panic("Checker enabled but not compiled in!");
-#endif // USE_CHECKER
+    } else {
+        checker = NULL;
     }
+#endif // USE_CHECKER
 
 #if !FULL_SYSTEM
     thread.resize(number_of_threads);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index e71d05c8e..b7533e311 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -42,6 +42,7 @@
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
 #include "config/full_system.hh"
+#include "config/use_checker.hh"
 #include "cpu/activity.hh"
 #include "cpu/base.hh"
 #include "cpu/simple_thread.hh"
@@ -617,11 +618,13 @@ class FullO3CPU : public BaseO3CPU
     /** The global sequence number counter. */
     InstSeqNum globalSeqNum;//[Impl::MaxThreads];
 
+#if USE_CHECKER
     /** Pointer to the checker, which can dynamically verify
      * instruction results at run time.  This can be set to NULL if it
      * is not being used.
      */
     Checker<DynInstPtr> *checker;
+#endif
 
 #if FULL_SYSTEM
     /** Pointer to the system. */
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index e81862a96..587087640 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -64,7 +64,8 @@ class EtherDump(SimObject):
 
 class IGbE(PciDevice):
     type = 'IGbE'
-    hardware_address = Param.String("Ethernet Hardware Address")
+    hardware_address = Param.EthernetAddr(NextEthernetAddr,
+        "Ethernet Hardware Address")
     use_flow_control = Param.Bool(False,
         "Should we use xon/xoff flow contorl (UNIMPLEMENTD)")
     rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
@@ -100,9 +101,9 @@ class IGbEInt(EtherInt):
     type = 'IGbEInt'
     device = Param.IGbE("Ethernet device of this interface")
 
-
-
 class EtherDevBase(PciDevice):
+    type = 'EtherDevBase'
+    abstract = True
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 13e545064..d818a25ea 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -115,11 +115,14 @@ void Bus::occupyBus(PacketPtr pkt)
     //Bring tickNextIdle up to the present tick
     //There is some potential ambiguity where a cycle starts, which might make
     //a difference when devices are acting right around a cycle boundary. Using
-    //a < allows things which happen exactly on a cycle boundary to take up only
-    //the following cycle. Anthing that happens later will have to "wait" for
-    //the end of that cycle, and then start using the bus after that.
-    while (tickNextIdle < curTick)
-        tickNextIdle += clock;
+    //a < allows things which happen exactly on a cycle boundary to take up
+    //only the following cycle. Anything that happens later will have to "wait"
+    //for the end of that cycle, and then start using the bus after that.
+    if (tickNextIdle < curTick) {
+        tickNextIdle = curTick;
+        if (tickNextIdle % clock != 0)
+            tickNextIdle = curTick - (curTick % clock) + clock;
+    }
 
     // The packet will be sent. Figure out how long it occupies the bus, and
     // how much of that time is for the first "word", aka bus width.
@@ -132,10 +135,9 @@ void Bus::occupyBus(PacketPtr pkt)
         // We're using the "adding instead of dividing" trick again here
         if (pkt->hasData()) {
             int dataSize = pkt->getSize();
-            for (int transmitted = 0; transmitted < dataSize;
-                    transmitted += width) {
+            numCycles += dataSize/width;
+            if (dataSize % width)
                 numCycles++;
-            }
         } else {
             // If the packet didn't have data, it must have been a response.
             // Those use the bus for one cycle to send their data.
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 32f3f0174..55b68f81f 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -90,3 +90,4 @@ class BaseCache(MemObject):
          "Only prefetch on data not on instruction accesses")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
+    addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
diff --git a/src/sim/Process.py b/src/sim/Process.py
index 16be65fd4..34ff6c394 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -40,7 +40,7 @@ class LiveProcess(Process):
     type = 'LiveProcess'
     executable = Param.String('', "executable (overrides cmd[0] if set)")
     cmd = VectorParam.String("command line (executable plus arguments)")
-    env = VectorParam.String('', "environment settings")
+    env = VectorParam.String([], "environment settings")
     cwd = Param.String('', "current working directory")
     input = Param.String('cin', "filename for stdin")
     uid = Param.Int(100, 'user id')
diff --git a/src/sim/System.py b/src/sim/System.py
index b37e385c1..3f4c57f0c 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -39,6 +39,7 @@ class System(SimObject):
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
     mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
     if build_env['FULL_SYSTEM']:
+        abstract = True
         boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                              "boot processor frequency")
         init_param = Param.UInt64(0, "numerical value to pass into simulator")