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authorAndreas Hansson <andreas.hansson@arm.com>2014-10-01 08:05:51 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-10-01 08:05:51 -0400
commit10f82934be924f265af4f10b15ca66106171f770 (patch)
treee8e92c73422751d4ee26c3b87ceae204fa520751 /src
parentff2d58f935c434e89a499474d3bda76f476e6d25 (diff)
downloadgem5-10f82934be924f265af4f10b15ca66106171f770.tar.xz
arm: More UBSan cleanups after additional full-system runs
Some incorrect casting to IntRegIndex, and a few uninitialized members in the i8254xGBe device.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/insts/misc.hh8
-rw-r--r--src/arch/arm/isa/formats/misc.isa4
-rw-r--r--src/arch/arm/isa/templates/misc.isa8
-rw-r--r--src/dev/i8254xGBe.cc8
4 files changed, 15 insertions, 13 deletions
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 4217dc6f1..0c864559e 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -97,13 +97,13 @@ class MsrRegOp : public MsrBase
class MrrcOp : public PredOp
{
protected:
- IntRegIndex op1;
+ MiscRegIndex op1;
IntRegIndex dest;
IntRegIndex dest2;
uint32_t imm;
MrrcOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
+ MiscRegIndex _op1, IntRegIndex _dest, IntRegIndex _dest2,
uint32_t _imm) :
PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
dest2(_dest2), imm(_imm)
@@ -117,11 +117,11 @@ class McrrOp : public PredOp
protected:
IntRegIndex op1;
IntRegIndex op2;
- IntRegIndex dest;
+ MiscRegIndex dest;
uint32_t imm;
McrrOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _dest,
+ IntRegIndex _op1, IntRegIndex _op2, MiscRegIndex _dest,
uint32_t _imm) :
PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
dest(_dest), imm(_imm)
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 7d3865104..925ed55cd 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -274,8 +274,8 @@ let {{
uint32_t iss = mcrrMrrcIssBuild(isRead, crm, rt, rt2, opc1);
if (isRead)
- return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2, rt, iss);
- return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg, iss);
+ return new Mrrc15(machInst, miscReg, rt2, rt, iss);
+ return new Mcrr15(machInst, rt2, rt, miscReg, iss);
} else {
return new FailUnimplemented(isRead ? "mrrc" : "mcrr", machInst,
csprintf("%s %s",
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 5cd4637a6..d661b4f18 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -183,7 +183,7 @@ class %(class_name)s : public %(base_class)s
protected:
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
%(BasicExecDeclare)s
};
@@ -191,7 +191,7 @@ class %(class_name)s : public %(base_class)s
def template MrrcOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex op1,
+ MiscRegIndex op1,
IntRegIndex dest,
IntRegIndex dest2,
uint32_t imm)
@@ -214,7 +214,7 @@ class %(class_name)s : public %(base_class)s
public:
// Constructor
%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _dest, uint32_t imm);
+ MiscRegIndex _dest, uint32_t imm);
%(BasicExecDeclare)s
};
}};
@@ -223,7 +223,7 @@ def template McrrOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
IntRegIndex op1,
IntRegIndex op2,
- IntRegIndex dest,
+ MiscRegIndex dest,
uint32_t imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
dest, imm)
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index e65baba89..d86d7b486 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -821,8 +821,9 @@ IGbE::chkInterrupt()
template<class T>
IGbE::DescCache<T>::DescCache(IGbE *i, const std::string n, int s)
: igbe(i), _name(n), cachePnt(0), size(s), curFetching(0),
- wbOut(0), pktPtr(NULL), wbDelayEvent(this),
- fetchDelayEvent(this), fetchEvent(this), wbEvent(this)
+ wbOut(0), moreToWb(false), wbAlignment(0), pktPtr(NULL),
+ wbDelayEvent(this), fetchDelayEvent(this), fetchEvent(this),
+ wbEvent(this)
{
fetchBuf = new T[size];
wbBuf = new T[size];
@@ -1540,7 +1541,8 @@ IGbE::RxDescCache::unserialize(Checkpoint *cp, const std::string &section)
IGbE::TxDescCache::TxDescCache(IGbE *i, const std::string n, int s)
: DescCache<TxDesc>(i,n, s), pktDone(false), isTcp(false),
- pktWaiting(false), completionAddress(0), completionEnabled(false),
+ pktWaiting(false), pktMultiDesc(false),
+ completionAddress(0), completionEnabled(false),
useTso(false), tsoHeaderLen(0), tsoMss(0), tsoTotalLen(0), tsoUsedLen(0),
tsoPrevSeq(0), tsoPktPayloadBytes(0), tsoLoadedHeader(false),
tsoPktHasHeader(false), tsoDescBytesUsed(0), tsoCopyBytes(0), tsoPkts(0),