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authorSteve Reinhardt <stever@eecs.umich.edu>2006-10-19 13:33:08 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-10-19 13:33:08 -0400
commit11f0badbaa8573560a76f19f11e26d267e481627 (patch)
treed533988109a75199e6d62d1da7cb4845d3c3a927 /src
parentbba3dfb0d3f3ee15ddb5261d0b57c789b42a6925 (diff)
parenta78e92381b14dae8eb3113a48f9b0112e8d02a98 (diff)
downloadgem5-11f0badbaa8573560a76f19f11e26d267e481627.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head --HG-- extra : convert_revision : 8a70922250092c013fa4db6d83254b438ee6c4be
Diffstat (limited to 'src')
-rw-r--r--src/base/traceflags.py3
-rw-r--r--src/sim/eventq.hh22
2 files changed, 16 insertions, 9 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index 757c9e7b7..298d22c2b 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -182,7 +182,8 @@ compoundFlagMap = {
'EthernetNoData' : [ 'Ethernet', 'EthernetPIO', 'EthernetDesc', 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ],
'IdeAll' : [ 'IdeCtrl', 'IdeDisk' ],
'O3CPUAll' : [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 'IQ', 'ROB', 'FreeList', 'RenameMap', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'FullCPU', 'O3CPU', 'Activity','Scoreboard','Writeback'],
- 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU']
+ 'OzoneCPUAll' : [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU'],
+ 'All' : baseFlags
}
#############################################################
diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh
index 537bfb918..fa65b08af 100644
--- a/src/sim/eventq.hh
+++ b/src/sim/eventq.hh
@@ -120,10 +120,22 @@ class Event : public Serializable, public FastAlloc
/// priority; these values are used to control events that need to
/// be ordered within a cycle.
enum Priority {
- /// Breakpoints should happen before anything else, so we
- /// don't miss any action when debugging.
+ /// If we enable tracing on a particular cycle, do that as the
+ /// very first thing so we don't miss any of the events on
+ /// that cycle (even if we enter the debugger).
+ Trace_Enable_Pri = -101,
+
+ /// Breakpoints should happen before anything else (except
+ /// enabling trace output), so we don't miss any action when
+ /// debugging.
Debug_Break_Pri = -100,
+ /// CPU switches schedule the new CPU's tick event for the
+ /// same cycle (after unscheduling the old CPU's tick event).
+ /// The switch needs to come before any tick events to make
+ /// sure we don't tick both CPUs in the same cycle.
+ CPU_Switch_Pri = -31,
+
/// For some reason "delayed" inter-cluster writebacks are
/// scheduled before regular writebacks (which have default
/// priority). Steve?
@@ -132,12 +144,6 @@ class Event : public Serializable, public FastAlloc
/// Default is zero for historical reasons.
Default_Pri = 0,
- /// CPU switches schedule the new CPU's tick event for the
- /// same cycle (after unscheduling the old CPU's tick event).
- /// The switch needs to come before any tick events to make
- /// sure we don't tick both CPUs in the same cycle.
- CPU_Switch_Pri = -31,
-
/// Serailization needs to occur before tick events also, so
/// that a serialize/unserialize is identical to an on-line
/// CPU switch.