diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-12 04:07:59 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-10-12 04:07:59 -0400 |
| commit | 22c04190c607b9360d9a23548f8a54e83cf0e74a (patch) | |
| tree | 576135962e3c9c725157b461c8009b05933bba2b /src | |
| parent | 735c4a87665119a33443cf8d191d329c66191c6e (diff) | |
| download | gem5-22c04190c607b9360d9a23548f8a54e83cf0e74a.tar.xz | |
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
Diffstat (limited to 'src')
168 files changed, 512 insertions, 628 deletions
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh index 6a88ee40b..6c06fc397 100644 --- a/src/arch/alpha/isa.hh +++ b/src/arch/alpha/isa.hh @@ -92,8 +92,8 @@ namespace AlphaISA memset(ipr, 0, sizeof(ipr)); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; int flattenIntIndex(int reg) const diff --git a/src/arch/alpha/kernel_stats.hh b/src/arch/alpha/kernel_stats.hh index 188d3ec4b..06d20e6fa 100644 --- a/src/arch/alpha/kernel_stats.hh +++ b/src/arch/alpha/kernel_stats.hh @@ -86,8 +86,8 @@ class Statistics : public ::Kernel::Statistics void setIdleProcess(Addr idle, ThreadContext *tc); public: - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace Kernel diff --git a/src/arch/alpha/pagetable.hh b/src/arch/alpha/pagetable.hh index 0b6524043..dc13d3790 100644 --- a/src/arch/alpha/pagetable.hh +++ b/src/arch/alpha/pagetable.hh @@ -142,8 +142,8 @@ struct TlbEntry : public Serializable return ppn << PageShift; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace AlphaISA diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh index 6701017e0..cd45871b1 100644 --- a/src/arch/alpha/process.hh +++ b/src/arch/alpha/process.hh @@ -42,7 +42,7 @@ class AlphaLiveProcess : public LiveProcess protected: AlphaLiveProcess(LiveProcessParams *params, ObjectFile *objFile); - void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void loadState(CheckpointIn &cp) override; void initState(); void argsInit(int intSize, int pageSize); diff --git a/src/arch/alpha/system.hh b/src/arch/alpha/system.hh index 3f4a2367e..f8ca54506 100644 --- a/src/arch/alpha/system.hh +++ b/src/arch/alpha/system.hh @@ -60,8 +60,8 @@ class AlphaSystem : public System /** * Serialization stuff */ - void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serializeSymtab(CheckpointOut &cp) const override; + void unserializeSymtab(CheckpointIn &cp) override; /** Override startup() to provide a path to call setupFuncEvents() */ diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh index 73ffda1f6..a8bdf30e1 100644 --- a/src/arch/alpha/tlb.hh +++ b/src/arch/alpha/tlb.hh @@ -117,8 +117,8 @@ class TLB : public BaseTLB static Fault checkCacheability(RequestPtr &req, bool itb = false); // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; // Most recently used page table entries TlbEntry *EntryCache[3]; diff --git a/src/arch/arm/isa_device.hh b/src/arch/arm/isa_device.hh index 8b12fa502..185e632a5 100644 --- a/src/arch/arm/isa_device.hh +++ b/src/arch/arm/isa_device.hh @@ -97,8 +97,8 @@ class DummyISADevice : public BaseISADevice : BaseISADevice() {} ~DummyISADevice() {} - void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE; - MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE; + void setMiscReg(int misc_reg, MiscReg val) override; + MiscReg readMiscReg(int misc_reg) override; }; } diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh index 97127b471..aee27a8a4 100644 --- a/src/arch/arm/kvm/armv8_cpu.hh +++ b/src/arch/arm/kvm/armv8_cpu.hh @@ -83,11 +83,11 @@ class ArmV8KvmCPU : public BaseArmKvmCPU ArmV8KvmCPU(ArmV8KvmCPUParams *params); virtual ~ArmV8KvmCPU(); - void dump() M5_ATTR_OVERRIDE; + void dump() override; protected: - void updateKvmState() M5_ATTR_OVERRIDE; - void updateThreadContext() M5_ATTR_OVERRIDE; + void updateKvmState() override; + void updateThreadContext() override; protected: /** Mapping between integer registers in gem5 and KVM */ diff --git a/src/arch/arm/kvm/base_cpu.hh b/src/arch/arm/kvm/base_cpu.hh index 736153b78..2f6f978f7 100644 --- a/src/arch/arm/kvm/base_cpu.hh +++ b/src/arch/arm/kvm/base_cpu.hh @@ -52,10 +52,10 @@ class BaseArmKvmCPU : public BaseKvmCPU BaseArmKvmCPU(BaseArmKvmCPUParams *params); virtual ~BaseArmKvmCPU(); - void startup() M5_ATTR_OVERRIDE; + void startup() override; protected: - Tick kvmRun(Tick ticks) M5_ATTR_OVERRIDE; + Tick kvmRun(Tick ticks) override; /** Cached state of the IRQ line */ diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh index 4a115c87c..f156caa6b 100644 --- a/src/arch/arm/kvm/gic.hh +++ b/src/arch/arm/kvm/gic.hh @@ -76,23 +76,23 @@ class KvmGic : public BaseGic KvmGic(const KvmGicParams *p); ~KvmGic(); - void startup() M5_ATTR_OVERRIDE { verifyMemoryMode(); } - void drainResume() M5_ATTR_OVERRIDE { verifyMemoryMode(); } + void startup() override { verifyMemoryMode(); } + void drainResume() override { verifyMemoryMode(); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(Checkpoint *cp, const std::string &sec) override; public: // PioDevice AddrRangeList getAddrRanges() const { return addrRanges; } - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; public: // BaseGic - void sendInt(uint32_t num) M5_ATTR_OVERRIDE; - void clearInt(uint32_t num) M5_ATTR_OVERRIDE; + void sendInt(uint32_t num) override; + void clearInt(uint32_t num) override; - void sendPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE; - void clearPPInt(uint32_t num, uint32_t cpu) M5_ATTR_OVERRIDE; + void sendPPInt(uint32_t num, uint32_t cpu) override; + void clearPPInt(uint32_t num, uint32_t cpu) override; protected: /** diff --git a/src/arch/arm/pagetable.hh b/src/arch/arm/pagetable.hh index 3de993d27..6d306d6e0 100644 --- a/src/arch/arm/pagetable.hh +++ b/src/arch/arm/pagetable.hh @@ -284,7 +284,7 @@ struct TlbEntry : public Serializable } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { SERIALIZE_SCALAR(longDescFormat); SERIALIZE_SCALAR(pfn); @@ -314,7 +314,7 @@ struct TlbEntry : public Serializable paramOut(cp, "domain", domain_); } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { UNSERIALIZE_SCALAR(longDescFormat); UNSERIALIZE_SCALAR(pfn); diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh index 80be965a4..fc5bf74b3 100644 --- a/src/arch/arm/pmu.hh +++ b/src/arch/arm/pmu.hh @@ -96,10 +96,10 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { void addEventProbe(unsigned int id, SimObject *obj, const char *name); public: // SimObject and related interfaces - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; public: // ISA Device interface @@ -109,14 +109,14 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { * @param misc_reg Register number (see miscregs.hh) * @param val Value to store */ - void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE; + void setMiscReg(int misc_reg, MiscReg val) override; /** * Read a register within the PMU. * * @param misc_reg Register number (see miscregs.hh) * @return Register value. */ - MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE; + MiscReg readMiscReg(int misc_reg) override; protected: // PMU register types and constants BitUnion32(PMCR_t) @@ -269,7 +269,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { : ProbeListenerArgBase(pm, name), pmu(_pmu), id(_id) {} - void notify(const uint64_t &val) M5_ATTR_OVERRIDE + void notify(const uint64_t &val) override { pmu.handleEvent(id, val); } @@ -329,8 +329,8 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { listeners.reserve(4); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Add an event count to the counter and check for overflow. diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index e973e9a74..8af70075d 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -891,8 +891,8 @@ class TableWalker : public MemObject bool haveLargeAsid64() const { return _haveLargeAsid64; } /** Checks if all state is cleared and if so, completes drain */ void completeDrain(); - DrainState drain() M5_ATTR_OVERRIDE; - virtual void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + virtual void drainResume() override; virtual BaseMasterPort& getMasterPort(const std::string &if_name, PortID idx = InvalidPortID); diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 35049db48..f6776b0a9 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -284,15 +284,15 @@ class TLB : public BaseTLB bool callFromS2); Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void regStats(); - void regProbePoints() M5_ATTR_OVERRIDE; + void regProbePoints() override; /** * Get the table walker master port. This is used for migrating diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index c54bfb5f4..29828be75 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -45,7 +45,6 @@ #include "arch/generic/types.hh" #include "base/bitunion.hh" -#include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" #include "debug/Decoder.hh" @@ -483,7 +482,7 @@ namespace ArmISA } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { Base::serialize(cp); SERIALIZE_SCALAR(flags); @@ -494,7 +493,7 @@ namespace ArmISA } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { Base::unserialize(cp); UNSERIALIZE_SCALAR(flags); @@ -740,7 +739,7 @@ namespace ArmISA } // namespace ArmISA -__hash_namespace_begin +namespace std { template<> struct hash<ArmISA::ExtMachInst> : @@ -752,6 +751,6 @@ struct hash<ArmISA::ExtMachInst> : }; -__hash_namespace_end +} #endif diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh index 8e35b5b2f..2de8ca7b4 100644 --- a/src/arch/generic/types.hh +++ b/src/arch/generic/types.hh @@ -105,14 +105,14 @@ class PCStateBase : public Serializable } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { SERIALIZE_SCALAR(_pc); SERIALIZE_SCALAR(_npc); } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { UNSERIALIZE_SCALAR(_pc); UNSERIALIZE_SCALAR(_npc); @@ -248,7 +248,7 @@ class UPCState : public SimplePCState<MachInst> } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { Base::serialize(cp); SERIALIZE_SCALAR(_upc); @@ -256,7 +256,7 @@ class UPCState : public SimplePCState<MachInst> } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { Base::unserialize(cp); UNSERIALIZE_SCALAR(_upc); @@ -329,14 +329,14 @@ class DelaySlotPCState : public SimplePCState<MachInst> } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { Base::serialize(cp); SERIALIZE_SCALAR(_nnpc); } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { Base::unserialize(cp); UNSERIALIZE_SCALAR(_nnpc); @@ -426,7 +426,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst> } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { Base::serialize(cp); SERIALIZE_SCALAR(_upc); @@ -434,7 +434,7 @@ class DelaySlotUPCState : public DelaySlotPCState<MachInst> } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { Base::unserialize(cp); UNSERIALIZE_SCALAR(_upc); diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh index 3c9165bfa..b5323e4e1 100755 --- a/src/arch/mips/interrupts.hh +++ b/src/arch/mips/interrupts.hh @@ -116,13 +116,13 @@ class Interrupts : public SimObject void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { fatal("Serialization of Interrupts Unimplemented for MIPS"); } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { fatal("Unserialization of Interrupts Unimplemented for MIPS"); } diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh index 5a9069e4c..a2f356e1f 100644 --- a/src/arch/mips/tlb.hh +++ b/src/arch/mips/tlb.hh @@ -107,8 +107,8 @@ class TLB : public BaseTLB static Fault checkCacheability(RequestPtr &req); // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void regStats(); diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh index a07dad954..81ea22cc4 100644 --- a/src/arch/power/tlb.hh +++ b/src/arch/power/tlb.hh @@ -172,8 +172,8 @@ class TLB : public BaseTLB Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const; // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void regStats(); }; diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh index a5d204827..83917ec0c 100644 --- a/src/arch/power/types.hh +++ b/src/arch/power/types.hh @@ -33,7 +33,6 @@ #include "arch/generic/types.hh" #include "base/bitunion.hh" -#include "base/hashmap.hh" #include "base/types.hh" namespace PowerISA @@ -89,7 +88,7 @@ typedef GenericISA::SimplePCState<MachInst> PCState; } // PowerISA namespace -__hash_namespace_begin +namespace std { template<> struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> { @@ -98,6 +97,6 @@ struct hash<PowerISA::ExtMachInst> : public hash<uint32_t> { }; }; -__hash_namespace_end +} #endif // __ARCH_POWER_TYPES_HH__ diff --git a/src/arch/sparc/interrupts.hh b/src/arch/sparc/interrupts.hh index 432132f66..8929759f3 100644 --- a/src/arch/sparc/interrupts.hh +++ b/src/arch/sparc/interrupts.hh @@ -191,14 +191,14 @@ class Interrupts : public SimObject } void - serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + serialize(CheckpointOut &cp) const override { SERIALIZE_ARRAY(interrupts,NumInterruptTypes); SERIALIZE_SCALAR(intStatus); } void - unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + unserialize(CheckpointIn &cp) override { UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); UNSERIALIZE_SCALAR(intStatus); diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh index 1d2a457d2..18ac30857 100644 --- a/src/arch/sparc/isa.hh +++ b/src/arch/sparc/isa.hh @@ -167,8 +167,8 @@ class ISA : public SimObject void clear(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void startup(ThreadContext *tc) {} diff --git a/src/arch/sparc/system.hh b/src/arch/sparc/system.hh index 68688cc1f..68a192cb9 100644 --- a/src/arch/sparc/system.hh +++ b/src/arch/sparc/system.hh @@ -54,8 +54,8 @@ class SparcSystem : public System * Serialization stuff */ public: - void serializeSymtab(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserializeSymtab(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serializeSymtab(CheckpointOut &cp) const override; + void unserializeSymtab(CheckpointIn &cp) override; /** reset binary symbol table */ SymbolTable *resetSymtab; diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh index e64d3f1b4..cd4634ab8 100644 --- a/src/arch/sparc/tlb.hh +++ b/src/arch/sparc/tlb.hh @@ -176,8 +176,8 @@ class TLB : public BaseTLB void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs); // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** Give an entry id, read that tlb entries' tte */ uint64_t TteRead(int entry); diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh index d42751d21..2e5e83764 100644 --- a/src/arch/x86/decoder.hh +++ b/src/arch/x86/decoder.hh @@ -32,6 +32,7 @@ #define __ARCH_X86_DECODER_HH__ #include <cassert> +#include <unordered_map> #include <vector> #include "arch/x86/regs/misc.hh" @@ -223,11 +224,11 @@ class Decoder typedef DecodeCache::AddrMap<Decoder::InstBytes> DecodePages; DecodePages *decodePages; - typedef m5::hash_map<CacheKey, DecodePages *> AddrCacheMap; + typedef std::unordered_map<CacheKey, DecodePages *> AddrCacheMap; AddrCacheMap addrCacheMap; DecodeCache::InstMap *instMap; - typedef m5::hash_map<CacheKey, DecodeCache::InstMap *> InstCacheMap; + typedef std::unordered_map<CacheKey, DecodeCache::InstMap *> InstCacheMap; static InstCacheMap instCacheMap; public: diff --git a/src/arch/x86/interrupts.hh b/src/arch/x86/interrupts.hh index 272cfea44..b1bdbf10f 100644 --- a/src/arch/x86/interrupts.hh +++ b/src/arch/x86/interrupts.hh @@ -293,8 +293,8 @@ class Interrupts : public BasicPioDevice, IntDevice /* * Serialization. */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /* * Old functions needed for compatability but which will be phased out diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh index 88f4980ae..90ab619cc 100644 --- a/src/arch/x86/isa.hh +++ b/src/arch/x86/isa.hh @@ -97,8 +97,8 @@ namespace X86ISA return reg; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void startup(ThreadContext *tc); diff --git a/src/arch/x86/pagetable.hh b/src/arch/x86/pagetable.hh index 3345366d0..1361109d5 100644 --- a/src/arch/x86/pagetable.hh +++ b/src/arch/x86/pagetable.hh @@ -149,8 +149,8 @@ namespace X86ISA return (1 << logBytes); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** The size of each level of the page table expressed in base 2 diff --git a/src/arch/x86/regs/msr.hh b/src/arch/x86/regs/msr.hh index a2ae5c69a..f273a8227 100644 --- a/src/arch/x86/regs/msr.hh +++ b/src/arch/x86/regs/msr.hh @@ -31,14 +31,15 @@ #ifndef __ARCH_X86_REG_MSR_HH__ #define __ARCH_X86_REG_MSR_HH__ +#include <unordered_map> + #include "arch/x86/regs/misc.hh" -#include "base/hashmap.hh" #include "base/types.hh" namespace X86ISA { -typedef m5::hash_map<Addr, MiscRegIndex> MsrMap; +typedef std::unordered_map<Addr, MiscRegIndex> MsrMap; /** * Map between MSR addresses and their corresponding misc registers. diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh index 83ec7cc59..6e3eb2eee 100644 --- a/src/arch/x86/tlb.hh +++ b/src/arch/x86/tlb.hh @@ -148,8 +148,8 @@ namespace X86ISA TlbEntry * insert(Addr vpn, TlbEntry &entry); // Checkpointing - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Get the table walker master port. This is used for diff --git a/src/arch/x86/types.hh b/src/arch/x86/types.hh index 88b000b6e..99e2c826c 100644 --- a/src/arch/x86/types.hh +++ b/src/arch/x86/types.hh @@ -45,7 +45,6 @@ #include "arch/generic/types.hh" #include "base/bitunion.hh" #include "base/cprintf.hh" -#include "base/hashmap.hh" #include "base/types.hh" #include "sim/serialize.hh" @@ -346,7 +345,7 @@ namespace X86ISA } -__hash_namespace_begin +namespace std { template<> struct hash<X86ISA::ExtMachInst> { size_t operator()(const X86ISA::ExtMachInst &emi) const { @@ -362,7 +361,7 @@ __hash_namespace_begin emi.stackSize ^ emi.dispSize; }; }; -__hash_namespace_end +} // These two functions allow ExtMachInst to be used with SERIALIZE_SCALAR // and UNSERIALIZE_SCALAR. diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh index 9be66d8d2..87bed9762 100644 --- a/src/arch/x86/utility.hh +++ b/src/arch/x86/utility.hh @@ -42,7 +42,6 @@ #include "arch/x86/regs/misc.hh" #include "arch/x86/types.hh" -#include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" #include "cpu/static_inst.hh" diff --git a/src/base/compiler.hh b/src/base/compiler.hh index 1a104dd87..9cad07d7a 100644 --- a/src/base/compiler.hh +++ b/src/base/compiler.hh @@ -43,37 +43,8 @@ #ifndef __BASE_COMPILER_HH__ #define __BASE_COMPILER_HH__ -// gcc C++11 status: http://gcc.gnu.org/projects/cxx0x.html -// clang C++11 status: http://clang.llvm.org/cxx_status.html // http://gcc.gnu.org/onlinedocs/gcc/Function-Attributes.html -/* Support for override control (final/override) */ -#undef M5_COMP_HAS_OVERRIDE_CONTROL - -#if defined(__GNUC__) && !defined(__clang__) /* Check for gcc */ - -# define M5_GCC_VERSION(maj, min) \ - (__GNUC__ > (maj) || (__GNUC__ == (maj) && __GNUC_MINOR__ >= (min))) - -# define M5_COMP_HAS_OVERRIDE_CONTROL M5_GCC_VERSION(4, 7) - -#elif defined(__clang__) /* Check for clang */ - -# define M5_COMP_HAS_OVERRIDE_CONTROL __has_feature(cxx_override_control) - -#else -# error "Need to define compiler options in base/compiler.hh" -#endif - - -#if M5_COMP_HAS_OVERRIDE_CONTROL -# define M5_ATTR_FINAL final -# define M5_ATTR_OVERRIDE override -#else -# define M5_ATTR_FINAL -# define M5_ATTR_OVERRIDE -#endif - #if defined(__GNUC__) // clang or gcc # define M5_ATTR_NORETURN __attribute__((noreturn)) # define M5_DUMMY_RETURN diff --git a/src/base/cp_annotate.hh b/src/base/cp_annotate.hh index a57d9bc79..0a0cc34a3 100644 --- a/src/base/cp_annotate.hh +++ b/src/base/cp_annotate.hh @@ -47,10 +47,10 @@ #include <map> #include <memory> #include <string> +#include <unordered_map> #include <vector> #include "base/loader/symtab.hh" -#include "base/hashmap.hh" #include "base/trace.hh" #include "base/types.hh" #include "debug/AnnotateQ.hh" @@ -127,7 +127,7 @@ class CPA /** * Provide a hash function for the CPI Id type */ -__hash_namespace_begin +namespace std { template <> struct hash<std::pair<std::string, uint64_t> > { @@ -139,7 +139,7 @@ struct hash<std::pair<std::string, uint64_t> > } }; -__hash_namespace_end +} class CPA : SimObject { @@ -202,8 +202,8 @@ class CPA : SimObject uint8_t cpu; bool dump; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; typedef std::shared_ptr<AnnotateData> AnnDataPtr; @@ -236,12 +236,12 @@ class CPA : SimObject uint64_t conId; // Convert state strings into state ids - typedef m5::hash_map<std::string, int> SCache; + typedef std::unordered_map<std::string, int> SCache; typedef std::vector<SCache> StCache; // Convert sm and queue name,id into queue id typedef std::pair<std::string, uint64_t> Id; - typedef m5::hash_map<Id, int> IdHCache; + typedef std::unordered_map<Id, int> IdHCache; typedef std::vector<IdHCache> IdCache; // Hold mapping of sm and queues to output python @@ -266,7 +266,7 @@ class CPA : SimObject typedef std::map<int, int> LinkMap; // SC Links - typedef m5::hash_map<Id, AnnDataPtr> ScHCache; + typedef std::unordered_map<Id, AnnDataPtr> ScHCache; typedef std::vector<ScHCache> ScCache; @@ -540,8 +540,8 @@ class CPA : SimObject void dump(bool all); void dumpKey(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // !CP_ANNOTATE diff --git a/src/base/framebuffer.hh b/src/base/framebuffer.hh index eaac25111..fbeafb467 100644 --- a/src/base/framebuffer.hh +++ b/src/base/framebuffer.hh @@ -256,8 +256,8 @@ class FrameBuffer : public Serializable virtual ~FrameBuffer(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Resize the frame buffer. diff --git a/src/base/hashmap.hh b/src/base/hashmap.hh deleted file mode 100644 index b838f1e2c..000000000 --- a/src/base/hashmap.hh +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2012 ARM Limited - * All rights reserved - * - * The license below extends only to copyright in the software and shall - * not be construed as granting a license to any other intellectual - * property including but not limited to intellectual property relating - * to a hardware implementation of the functionality of the software - * licensed hereunder. You may use the software subject to the license - * terms below provided that you ensure that this notice is replicated - * unmodified and in its entirety in all distributions of the software, - * modified or unmodified, in source code or in binary form. - * - * Copyright (c) 2003-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - * Andreas Hansson - */ - -#ifndef __HASHMAP_HH__ -#define __HASHMAP_HH__ - -// we stick with defines here until gcc >= 4.7 and clang >= 3.2 is -// adopted as these are the minimum versions to support variadic -// templates and template aliasing -#define hash_map unordered_map -#define hash_multimap unordered_multimap -#define hash_set unordered_set -#define hash_multiset unordered_multiset - -// gcc >= 4.4 or clang with libc++ no longer rely on the transitional -// tr1 namespace -#include <unordered_map> -#include <unordered_set> -#define __hash_namespace std -#define __hash_namespace_begin namespace std { -#define __hash_namespace_end } - -namespace m5 { - using ::__hash_namespace::hash_multimap; - using ::__hash_namespace::hash_multiset; - using ::__hash_namespace::hash_map; - using ::__hash_namespace::hash_set; - using ::__hash_namespace::hash; -} - -#endif // __HASHMAP_HH__ diff --git a/src/base/inifile.hh b/src/base/inifile.hh index c2d263619..b4892d60a 100644 --- a/src/base/inifile.hh +++ b/src/base/inifile.hh @@ -35,10 +35,9 @@ #include <fstream> #include <list> #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" - /** * @file * Declaration of IniFile object. @@ -94,7 +93,7 @@ class IniFile class Section { /// EntryTable type. Map of strings to Entry object pointers. - typedef m5::hash_map<std::string, Entry *> EntryTable; + typedef std::unordered_map<std::string, Entry *> EntryTable; EntryTable table; ///< Table of entries. mutable bool referenced; ///< Has this section been used? @@ -139,7 +138,7 @@ class IniFile }; /// SectionTable type. Map of strings to Section object pointers. - typedef m5::hash_map<std::string, Section *> SectionTable; + typedef std::unordered_map<std::string, Section *> SectionTable; protected: /// Hash of section names to Section object pointers. diff --git a/src/base/pollevent.hh b/src/base/pollevent.hh index 632239e08..55f3b3717 100644 --- a/src/base/pollevent.hh +++ b/src/base/pollevent.hh @@ -60,8 +60,8 @@ class PollEvent : public Serializable bool queued() { return queue != 0; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; class PollQueue diff --git a/src/base/random.hh b/src/base/random.hh index dca956306..522ac8913 100644 --- a/src/base/random.hh +++ b/src/base/random.hh @@ -104,8 +104,8 @@ class Random : public Serializable return dist(gen); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; extern Random random_mt; diff --git a/src/base/trace.hh b/src/base/trace.hh index 2b1d03eff..ddf936ecd 100644 --- a/src/base/trace.hh +++ b/src/base/trace.hh @@ -101,9 +101,9 @@ class OstreamLogger : public Logger { } void logMessage(Tick when, const std::string &name, - const std::string &message) M5_ATTR_OVERRIDE; + const std::string &message) override; - std::ostream &getOstream() M5_ATTR_OVERRIDE { return stream; } + std::ostream &getOstream() override { return stream; } }; /** Get the current global debug logger. This takes ownership of the given diff --git a/src/base/vnc/vncserver.hh b/src/base/vnc/vncserver.hh index 0222a7726..a52850323 100644 --- a/src/base/vnc/vncserver.hh +++ b/src/base/vnc/vncserver.hh @@ -307,8 +307,8 @@ class VncServer : public VncInput static const PixelConverter pixelConverter; public: - void setDirty() M5_ATTR_OVERRIDE; - void frameBufferResized() M5_ATTR_OVERRIDE; + void setDirty() override; + void frameBufferResized() override; }; #endif diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 95ae4fc43..554c4d754 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -307,7 +307,7 @@ class BaseCPU : public MemObject virtual void startup(); virtual void regStats(); - void regProbePoints() M5_ATTR_OVERRIDE; + void regProbePoints() override; void registerThreadContexts(); @@ -399,7 +399,7 @@ class BaseCPU : public MemObject * * @param os The stream to serialize to. */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; /** * Reconstruct the state of this object from a checkpoint. @@ -412,7 +412,7 @@ class BaseCPU : public MemObject * @param cp The checkpoint use. * @param section The section name of this object. */ - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void unserialize(CheckpointIn &cp) override; /** * Serialize a single thread. diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 0351ec2e0..14c0ad0b2 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -189,8 +189,8 @@ class CheckerCPU : public BaseCPU, public ExecContext Counter numLoad; Counter startNumLoad; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; // These functions are only used in CPU models that split // effective address computation from the actual memory access. @@ -380,7 +380,7 @@ class CheckerCPU : public BaseCPU, public ExecContext Fault hwrei() { return thread->hwrei(); } bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } - void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { } + void wakeup(ThreadID tid) override { } // Assume that the normal CPU's call to syscall was successful. // The checker's state would have already been updated by the syscall. void syscall(int64_t callnum) { } diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh index 34387419f..c451cbb69 100644 --- a/src/cpu/decode_cache.hh +++ b/src/cpu/decode_cache.hh @@ -31,9 +31,10 @@ #ifndef __CPU_DECODE_CACHE_HH__ #define __CPU_DECODE_CACHE_HH__ +#include <unordered_map> + #include "arch/isa_traits.hh" #include "arch/types.hh" -#include "base/hashmap.hh" #include "config/the_isa.hh" #include "cpu/static_inst_fwd.hh" @@ -46,7 +47,7 @@ namespace DecodeCache { /// Hash for decoded instructions. -typedef m5::hash_map<TheISA::ExtMachInst, StaticInstPtr> InstMap; +typedef std::unordered_map<TheISA::ExtMachInst, StaticInstPtr> InstMap; /// A sparse map from an Addr to a Value, stored in page chunks. template<class Value> @@ -58,7 +59,7 @@ class AddrMap Value items[TheISA::PageBytes]; }; // A map of cache pages which allows a sparse mapping. - typedef typename m5::hash_map<Addr, CachePage *> PageMap; + typedef typename std::unordered_map<Addr, CachePage *> PageMap; typedef typename PageMap::iterator PageIt; // Mini cache of recent lookups. PageIt recent[2]; @@ -75,7 +76,7 @@ class AddrMap /// Attempt to find the CacheePage which goes with a particular /// address. First check the small cache of recent results, then - /// actually look in the hash_map. + /// actually look in the hash map. /// @param addr The address to look up. CachePage * getPage(Addr addr) diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh index bdafb6245..57b3c2c59 100644 --- a/src/cpu/inst_pb_trace.hh +++ b/src/cpu/inst_pb_trace.hh @@ -75,7 +75,7 @@ class InstPBTraceRecord : public InstRecord * This implementation of dump calls InstPBTrace to output the contents to a * protobuf file */ - void dump() M5_ATTR_OVERRIDE; + void dump() override; protected: InstPBTrace& tracer; @@ -90,7 +90,7 @@ class InstPBTrace : public InstTracer InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr si, TheISA::PCState pc, const - StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE; + StaticInstPtr mi = NULL) override; protected: /** One output stream for the entire simulation. diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh index 89c52cf6b..d57ac3421 100644 --- a/src/cpu/kvm/base.hh +++ b/src/cpu/kvm/base.hh @@ -84,13 +84,11 @@ class BaseKvmCPU : public BaseCPU void startup(); void regStats(); - void serializeThread(CheckpointOut &cp, - ThreadID tid) const M5_ATTR_OVERRIDE; - void unserializeThread(CheckpointIn &cp, - ThreadID tid) M5_ATTR_OVERRIDE; + void serializeThread(CheckpointOut &cp, ThreadID tid) const override; + void unserializeThread(CheckpointIn &cp, ThreadID tid) override; - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; void switchOut(); void takeOverFrom(BaseCPU *cpu); @@ -100,7 +98,7 @@ class BaseKvmCPU : public BaseCPU MasterPort &getDataPort() { return dataPort; } MasterPort &getInstPort() { return instPort; } - void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE; + void wakeup(ThreadID tid = 0) override; void activateContext(ThreadID thread_num); void suspendContext(ThreadID thread_num); void deallocateContext(ThreadID thread_num); diff --git a/src/cpu/kvm/x86_cpu.hh b/src/cpu/kvm/x86_cpu.hh index 2e93a5f26..14f16d544 100644 --- a/src/cpu/kvm/x86_cpu.hh +++ b/src/cpu/kvm/x86_cpu.hh @@ -47,7 +47,7 @@ class X86KvmCPU : public BaseKvmCPU void startup(); /** @{ */ - void dump() const M5_ATTR_OVERRIDE; + void dump() const override; void dumpFpuRegs() const; void dumpIntRegs() const; void dumpSpecRegs() const; diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 99b915693..5bfc3b29f 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -128,7 +128,7 @@ class MinorCPU : public BaseCPU /** Starting, waking and initialisation */ void init(); void startup(); - void wakeup(ThreadID tid) M5_ATTR_OVERRIDE; + void wakeup(ThreadID tid) override; Addr dbg_vtophys(Addr addr); @@ -142,17 +142,16 @@ class MinorCPU : public BaseCPU Counter totalInsts() const; Counter totalOps() const; - void serializeThread(CheckpointOut &cp, - ThreadID tid) const M5_ATTR_OVERRIDE; - void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE; + void serializeThread(CheckpointOut &cp, ThreadID tid) const override; + void unserializeThread(CheckpointIn &cp, ThreadID tid) override; /** Serialize pipeline data */ void serialize(CheckpointOut &cp) const; void unserialize(CheckpointIn &cp); /** Drain interface */ - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; /** Signal from Pipeline that MinorCPU should signal that a drain * is complete and set its drainState */ void signalDrainDone(); diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh index bf2071b02..213def58e 100644 --- a/src/cpu/minor/pipeline.hh +++ b/src/cpu/minor/pipeline.hh @@ -126,7 +126,7 @@ class Pipeline : public Ticked * stages and pipeline advance) */ void evaluate(); - void countCycles(Cycles delta) M5_ATTR_OVERRIDE + void countCycles(Cycles delta) override { cpu.ppCycles->notify(delta); } diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index bd9c44752..bed61234a 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -338,9 +338,8 @@ class FullO3CPU : public BaseO3CPU /** Is the CPU draining? */ bool isDraining() const { return drainState() == DrainState::Draining; } - void serializeThread(CheckpointOut &cp, - ThreadID tid) const M5_ATTR_OVERRIDE; - void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE; + void serializeThread(CheckpointOut &cp, ThreadID tid) const override; + void unserializeThread(CheckpointIn &cp, ThreadID tid) override; public: /** Executes a syscall. @@ -350,10 +349,10 @@ class FullO3CPU : public BaseO3CPU /** Starts draining the CPU's pipeline of all instructions in * order to stop all memory accesses. */ - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /** Resumes execution after a drain. */ - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; /** * Commit has reached a safe point to drain a thread. @@ -640,7 +639,7 @@ class FullO3CPU : public BaseO3CPU /** Wakes the CPU, rescheduling the CPU if it's not already active. */ void wakeCPU(); - virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE; + virtual void wakeup(ThreadID tid) override; /** Gets a free thread id. Use if thread ids change across system. */ ThreadID getFreeTid(); diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index e356dd442..039bba8b6 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -54,7 +54,6 @@ #include "arch/isa_traits.hh" #include "arch/locked_mem.hh" #include "arch/mmapped_ipr.hh" -#include "base/hashmap.hh" #include "config/the_isa.hh" #include "cpu/inst_seq.hh" #include "cpu/timebuf.hh" diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index c2c411fe4..ffe66be6b 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -46,8 +46,8 @@ #include <list> #include <memory> #include <set> +#include <unordered_map> -#include "base/hashmap.hh" #include "base/statistics.hh" #include "cpu/inst_seq.hh" #include "debug/MemDepUnit.hh" @@ -237,7 +237,7 @@ class MemDepUnit /** Moves an entry to the ready list. */ inline void moveToReady(MemDepEntryPtr &ready_inst_entry); - typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; + typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash; typedef typename MemDepHash::iterator MemDepHashIt; diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index cf9403e48..19235c44c 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -112,7 +112,7 @@ struct O3ThreadState : public ThreadState { profilePC = 3; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + void serialize(CheckpointOut &cp) const override { ThreadState::serialize(cp); // Use the ThreadContext serialization helper to serialize the @@ -120,7 +120,7 @@ struct O3ThreadState : public ThreadState { ::serialize(*tc, cp); } - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + void unserialize(CheckpointIn &cp) override { // Prevent squashing - we don't have any instructions in // flight that we need to squash since we just instantiated a diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh index f8b217567..1f26f1aac 100644 --- a/src/cpu/pred/bpred_unit.hh +++ b/src/cpu/pred/bpred_unit.hh @@ -77,7 +77,7 @@ class BPredUnit : public SimObject */ void regStats(); - void regProbePoints() M5_ATTR_OVERRIDE; + void regProbePoints() override; /** Perform sanity checks after a drain. */ void drainSanityCheck() const; diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index 2bea12ab2..372df7cbd 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -191,8 +191,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU public: - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; void switchOut(); void takeOverFrom(BaseCPU *oldCPU); diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 1fcd5c203..72ac9bb4b 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -93,7 +93,7 @@ class BaseSimpleCPU : public BaseCPU public: BaseSimpleCPU(BaseSimpleCPUParams *params); virtual ~BaseSimpleCPU(); - void wakeup(ThreadID tid) M5_ATTR_OVERRIDE; + void wakeup(ThreadID tid) override; virtual void init(); public: Trace::InstRecord *traceData; @@ -152,9 +152,8 @@ class BaseSimpleCPU : public BaseCPU virtual Counter totalInsts() const; virtual Counter totalOps() const; - void serializeThread(CheckpointOut &cp, - ThreadID tid) const M5_ATTR_OVERRIDE; - void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE; + void serializeThread(CheckpointOut &cp, ThreadID tid) const override; + void unserializeThread(CheckpointIn &cp, ThreadID tid) override; }; diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh index 591cf8227..43a012404 100644 --- a/src/cpu/simple/exec_context.hh +++ b/src/cpu/simple/exec_context.hh @@ -160,23 +160,21 @@ class SimpleExecContext : public ExecContext { { } /** Reads an integer register. */ - IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE + IntReg readIntRegOperand(const StaticInst *si, int idx) override { numIntRegReads++; return thread->readIntReg(si->srcRegIdx(idx)); } /** Sets an integer register to a value. */ - void setIntRegOperand(const StaticInst *si, int idx, IntReg val) - M5_ATTR_OVERRIDE + void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override { numIntRegWrites++; thread->setIntReg(si->destRegIdx(idx), val); } /** Reads a floating point register of single register width. */ - FloatReg readFloatRegOperand(const StaticInst *si, int idx) - M5_ATTR_OVERRIDE + FloatReg readFloatRegOperand(const StaticInst *si, int idx) override { numFpRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; @@ -185,8 +183,7 @@ class SimpleExecContext : public ExecContext { /** Reads a floating point register in its binary format, instead * of by value. */ - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) - M5_ATTR_OVERRIDE + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override { numFpRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; @@ -194,8 +191,8 @@ class SimpleExecContext : public ExecContext { } /** Sets a floating point register of single width to a value. */ - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) - M5_ATTR_OVERRIDE + void setFloatRegOperand(const StaticInst *si, int idx, + FloatReg val) override { numFpRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; @@ -205,37 +202,36 @@ class SimpleExecContext : public ExecContext { /** Sets the bits of a floating point register of single width * to a binary value. */ void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val) M5_ATTR_OVERRIDE + FloatRegBits val) override { numFpRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; thread->setFloatRegBits(reg_idx, val); } - CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE + CCReg readCCRegOperand(const StaticInst *si, int idx) override { numCCRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; return thread->readCCReg(reg_idx); } - void setCCRegOperand(const StaticInst *si, int idx, CCReg val) - M5_ATTR_OVERRIDE + void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override { numCCRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; thread->setCCReg(reg_idx, val); } - MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE + MiscReg readMiscRegOperand(const StaticInst *si, int idx) override { numIntRegReads++; int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; return thread->readMiscReg(reg_idx); } - void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val) - M5_ATTR_OVERRIDE + void setMiscRegOperand(const StaticInst *si, int idx, + const MiscReg &val) override { numIntRegWrites++; int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; @@ -246,7 +242,7 @@ class SimpleExecContext : public ExecContext { * Reads a miscellaneous register, handling any architectural * side effects due to reading that register. */ - MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE + MiscReg readMiscReg(int misc_reg) override { numIntRegReads++; return thread->readMiscReg(misc_reg); @@ -256,18 +252,18 @@ class SimpleExecContext : public ExecContext { * Sets a miscellaneous register, handling any architectural * side effects due to writing that register. */ - void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE + void setMiscReg(int misc_reg, const MiscReg &val) override { numIntRegWrites++; thread->setMiscReg(misc_reg, val); } - PCState pcState() const M5_ATTR_OVERRIDE + PCState pcState() const override { return thread->pcState(); } - void pcState(const PCState &val) M5_ATTR_OVERRIDE + void pcState(const PCState &val) override { thread->pcState(val); } @@ -278,7 +274,7 @@ class SimpleExecContext : public ExecContext { * * @note Only valid for memory ops. */ - void setEA(Addr EA) M5_ATTR_OVERRIDE + void setEA(Addr EA) override { panic("BaseSimpleCPU::setEA() not implemented\n"); } /** @@ -286,17 +282,17 @@ class SimpleExecContext : public ExecContext { * * @note Only valid for memory ops. */ - Addr getEA() const M5_ATTR_OVERRIDE + Addr getEA() const override { panic("BaseSimpleCPU::getEA() not implemented\n"); } Fault readMem(Addr addr, uint8_t *data, unsigned int size, - unsigned int flags) M5_ATTR_OVERRIDE + unsigned int flags) override { return cpu->readMem(addr, data, size, flags); } Fault writeMem(uint8_t *data, unsigned int size, Addr addr, - unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE + unsigned int flags, uint64_t *res) override { return cpu->writeMem(data, size, addr, flags, res); } @@ -304,7 +300,7 @@ class SimpleExecContext : public ExecContext { /** * Sets the number of consecutive store conditional failures. */ - void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE + void setStCondFailures(unsigned int sc_failures) override { thread->setStCondFailures(sc_failures); } @@ -312,7 +308,7 @@ class SimpleExecContext : public ExecContext { /** * Returns the number of consecutive store conditional failures. */ - unsigned int readStCondFailures() const M5_ATTR_OVERRIDE + unsigned int readStCondFailures() const override { return thread->readStCondFailures(); } @@ -320,7 +316,7 @@ class SimpleExecContext : public ExecContext { /** * Executes a syscall specified by the callnum. */ - void syscall(int64_t callnum) M5_ATTR_OVERRIDE + void syscall(int64_t callnum) override { if (FullSystem) panic("Syscall emulation isn't available in FS mode."); @@ -329,7 +325,7 @@ class SimpleExecContext : public ExecContext { } /** Returns a pointer to the ThreadContext. */ - ThreadContext *tcBase() M5_ATTR_OVERRIDE + ThreadContext *tcBase() override { return thread->getTC(); } @@ -338,7 +334,7 @@ class SimpleExecContext : public ExecContext { * Somewhat Alpha-specific function that handles returning from an * error or interrupt. */ - Fault hwrei() M5_ATTR_OVERRIDE + Fault hwrei() override { return thread->hwrei(); } @@ -347,17 +343,17 @@ class SimpleExecContext : public ExecContext { * Check for special simulator handling of specific PAL calls. If * return value is false, actual PAL call will be suppressed. */ - bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE + bool simPalCheck(int palFunc) override { return thread->simPalCheck(palFunc); } - bool readPredicate() M5_ATTR_OVERRIDE + bool readPredicate() override { return thread->readPredicate(); } - void setPredicate(bool val) M5_ATTR_OVERRIDE + void setPredicate(bool val) override { thread->setPredicate(val); @@ -369,41 +365,41 @@ class SimpleExecContext : public ExecContext { /** * Invalidate a page in the DTLB <i>and</i> ITLB. */ - void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE + void demapPage(Addr vaddr, uint64_t asn) override { thread->demapPage(vaddr, asn); } - void armMonitor(Addr address) M5_ATTR_OVERRIDE + void armMonitor(Addr address) override { cpu->armMonitor(thread->threadId(), address); } - bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE + bool mwait(PacketPtr pkt) override { return cpu->mwait(thread->threadId(), pkt); } - void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE + void mwaitAtomic(ThreadContext *tc) override { cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb); } - AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE + AddressMonitor *getAddrMonitor() override { return cpu->getCpuAddrMonitor(thread->threadId()); } #if THE_ISA == MIPS_ISA MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) - M5_ATTR_OVERRIDE + override { panic("Simple CPU models do not support multithreaded " "register access."); } void setRegOtherThread(int regIdx, MiscReg val, - ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE + ThreadID tid = InvalidThreadID) override { panic("Simple CPU models do not support multithreaded " "register access."); diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh index e2c343755..2f4ed080d 100644 --- a/src/cpu/simple/probes/simpoint.hh +++ b/src/cpu/simple/probes/simpoint.hh @@ -41,7 +41,8 @@ #ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__ #define __CPU_SIMPLE_PROBES_SIMPOINT_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "cpu/simple_thread.hh" #include "params/SimPoint.hh" #include "sim/probe/probe.hh" @@ -59,7 +60,7 @@ typedef std::pair<Addr, Addr> BasicBlockRange; /** Overload hash function for BasicBlockRange type */ -__hash_namespace_begin +namespace std { template <> struct hash<BasicBlockRange> { @@ -68,7 +69,7 @@ struct hash<BasicBlockRange> return hash<Addr>()(bb.first + bb.second); } }; -__hash_namespace_end +} class SimPoint : public ProbeListenerObject { @@ -109,7 +110,7 @@ class SimPoint : public ProbeListenerObject }; /** Hash table containing all previously seen basic blocks */ - m5::hash_map<BasicBlockRange, BBInfo> bbMap; + std::unordered_map<BasicBlockRange, BBInfo> bbMap; /** Currently executing basic block */ BasicBlockRange currentBBV; /** inst count in current basic block */ diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index f1cc09e42..a6c7df988 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -272,8 +272,8 @@ class TimingSimpleCPU : public BaseSimpleCPU public: - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; void switchOut(); void takeOverFrom(BaseCPU *oldCPU); diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 20acff6ee..631b8ccfc 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -154,8 +154,8 @@ class SimpleThread : public ThreadState void copyState(ThreadContext *oldContext); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void startup(); /*************************************************************** diff --git a/src/cpu/testers/rubytest/CheckTable.cc b/src/cpu/testers/rubytest/CheckTable.cc index decdd20a2..b75fd0a52 100644 --- a/src/cpu/testers/rubytest/CheckTable.cc +++ b/src/cpu/testers/rubytest/CheckTable.cc @@ -112,7 +112,7 @@ CheckTable::getCheck(const Addr address) { DPRINTF(RubyTest, "Looking for check by address: %s", address); - m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address); + auto i = m_lookup_map.find(address); if (i == m_lookup_map.end()) return NULL; diff --git a/src/cpu/testers/rubytest/CheckTable.hh b/src/cpu/testers/rubytest/CheckTable.hh index fe7109f26..23ca855d7 100644 --- a/src/cpu/testers/rubytest/CheckTable.hh +++ b/src/cpu/testers/rubytest/CheckTable.hh @@ -31,9 +31,9 @@ #define __CPU_RUBYTEST_CHECKTABLE_HH__ #include <iostream> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" class Check; @@ -63,7 +63,7 @@ class CheckTable CheckTable& operator=(const CheckTable& obj); std::vector<Check*> m_check_vector; - m5::hash_map<Addr, Check*> m_lookup_map; + std::unordered_map<Addr, Check*> m_lookup_map; int m_num_writers; int m_num_readers; diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh index 8b71443f9..e5295bcf5 100644 --- a/src/cpu/testers/traffic_gen/traffic_gen.hh +++ b/src/cpu/testers/traffic_gen/traffic_gen.hh @@ -41,7 +41,8 @@ #ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ #define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "base/statistics.hh" #include "cpu/testers/traffic_gen/generators.hh" #include "mem/mem_object.hh" @@ -135,7 +136,7 @@ class TrafficGen : public MemObject uint32_t currState; /** Map of generator states */ - m5::hash_map<uint32_t, BaseGen*> states; + std::unordered_map<uint32_t, BaseGen*> states; /** Master port specialisation for the traffic generator */ class TrafficGenPort : public MasterPort @@ -198,10 +199,10 @@ class TrafficGen : public MemObject void initState(); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** Register statistics */ void regStats(); diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index bd471e13a..3a35d444a 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -63,9 +63,9 @@ struct ThreadState : public Serializable { virtual ~ThreadState(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void unserialize(CheckpointIn &cp) override; int cpuId() const { return baseCpu->cpuId(); } diff --git a/src/dev/alpha/backdoor.hh b/src/dev/alpha/backdoor.hh index da6201059..59d800863 100644 --- a/src/dev/alpha/backdoor.hh +++ b/src/dev/alpha/backdoor.hh @@ -76,8 +76,8 @@ class AlphaBackdoor : public BasicPioDevice protected: struct Access : public AlphaAccess, public Serializable { - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; union { @@ -118,8 +118,8 @@ class AlphaBackdoor : public BasicPioDevice /** * standard serialization routines for checkpointing */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_ALPHA_BACKDOOR_HH__ diff --git a/src/dev/alpha/tsunami.hh b/src/dev/alpha/tsunami.hh index 19df8093e..9972ecc95 100644 --- a/src/dev/alpha/tsunami.hh +++ b/src/dev/alpha/tsunami.hh @@ -124,8 +124,8 @@ class Tsunami : public Platform */ virtual Addr calcPciMemAddr(Addr addr); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_TSUNAMI_HH__ diff --git a/src/dev/alpha/tsunami_cchip.hh b/src/dev/alpha/tsunami_cchip.hh index fdbe64ef1..45834f9ea 100644 --- a/src/dev/alpha/tsunami_cchip.hh +++ b/src/dev/alpha/tsunami_cchip.hh @@ -131,8 +131,8 @@ class TsunamiCChip : public BasicPioDevice */ void reqIPI(uint64_t ipreq); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __TSUNAMI_CCHIP_HH__ diff --git a/src/dev/alpha/tsunami_io.hh b/src/dev/alpha/tsunami_io.hh index 2b7f5484e..e1b05abe8 100644 --- a/src/dev/alpha/tsunami_io.hh +++ b/src/dev/alpha/tsunami_io.hh @@ -138,8 +138,8 @@ class TsunamiIO : public BasicPioDevice */ void clearPIC(uint8_t bitvector); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Start running. diff --git a/src/dev/alpha/tsunami_pchip.hh b/src/dev/alpha/tsunami_pchip.hh index 0eb992131..e37292d57 100644 --- a/src/dev/alpha/tsunami_pchip.hh +++ b/src/dev/alpha/tsunami_pchip.hh @@ -89,8 +89,8 @@ class TsunamiPChip : public BasicPioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __TSUNAMI_PCHIP_HH__ diff --git a/src/dev/arm/energy_ctrl.hh b/src/dev/arm/energy_ctrl.hh index a1a362879..3b9f8883f 100644 --- a/src/dev/arm/energy_ctrl.hh +++ b/src/dev/arm/energy_ctrl.hh @@ -132,8 +132,8 @@ class EnergyCtrl : public BasicPioDevice */ virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; void startup(); void init(); diff --git a/src/dev/arm/flash_device.hh b/src/dev/arm/flash_device.hh index 891217cbf..9dfb22a72 100644 --- a/src/dev/arm/flash_device.hh +++ b/src/dev/arm/flash_device.hh @@ -62,11 +62,11 @@ class FlashDevice : public AbstractNVM ~FlashDevice(); /** Checkpoint functions*/ - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; void checkDrain(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: /** Defines the possible actions to the flash*/ diff --git a/src/dev/arm/generic_timer.hh b/src/dev/arm/generic_timer.hh index 97823f05f..c606f1e60 100644 --- a/src/dev/arm/generic_timer.hh +++ b/src/dev/arm/generic_timer.hh @@ -93,8 +93,8 @@ class SystemCounter : public Serializable void setKernelControl(uint32_t val) { _regCntkctl = val; } uint32_t getKernelControl() { return _regCntkctl; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: // Disable copying @@ -189,8 +189,8 @@ class ArchTimer : public Serializable /// Returns the value of the counter which this timer relies on. uint64_t value() const; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: // Disable copying @@ -202,8 +202,8 @@ class GenericTimer : public SimObject public: GenericTimer(GenericTimerParams *p); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: void setMiscReg(int misc_reg, unsigned cpu, ArmISA::MiscReg val); @@ -262,10 +262,10 @@ class GenericTimerISA : public ArmISA::BaseISADevice GenericTimerISA(GenericTimer &_parent, unsigned _cpu) : parent(_parent), cpu(_cpu) {} - void setMiscReg(int misc_reg, ArmISA::MiscReg val) M5_ATTR_OVERRIDE { + void setMiscReg(int misc_reg, ArmISA::MiscReg val) override { parent.setMiscReg(misc_reg, cpu, val); } - ArmISA::MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE { + ArmISA::MiscReg readMiscReg(int misc_reg) override { return parent.readMiscReg(misc_reg, cpu); } @@ -279,13 +279,13 @@ class GenericTimerMem : public PioDevice public: GenericTimerMem(GenericTimerMemParams *p); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: // PioDevice - AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; } - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; + AddrRangeList getAddrRanges() const override { return addrRanges; } + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; protected: uint64_t ctrlRead(Addr addr, size_t size) const; diff --git a/src/dev/arm/gic_pl390.hh b/src/dev/arm/gic_pl390.hh index 17946145f..71ea2e761 100644 --- a/src/dev/arm/gic_pl390.hh +++ b/src/dev/arm/gic_pl390.hh @@ -300,8 +300,8 @@ class Pl390 : public BaseGic void driveIrqEn(bool state); /** @} */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; protected: /** Handle a read to the distributor poriton of the GIC diff --git a/src/dev/arm/gpu_nomali.hh b/src/dev/arm/gpu_nomali.hh index bc687c264..4e4f9dbcb 100644 --- a/src/dev/arm/gpu_nomali.hh +++ b/src/dev/arm/gpu_nomali.hh @@ -55,13 +55,13 @@ class NoMaliGpu : public PioDevice virtual ~NoMaliGpu(); public: /* Checkpointing */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: /* IO device interfaces */ - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; - AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE; + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; + AddrRangeList getAddrRanges() const override; private: /** diff --git a/src/dev/arm/hdlcd.hh b/src/dev/arm/hdlcd.hh index cb47b8522..3ce12a24d 100644 --- a/src/dev/arm/hdlcd.hh +++ b/src/dev/arm/hdlcd.hh @@ -95,18 +95,18 @@ class HDLcd: public AmbaDmaDevice HDLcd(const HDLcdParams *p); ~HDLcd(); - void regStats() M5_ATTR_OVERRIDE; + void regStats() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; public: // IO device interface - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; - AddrRangeList getAddrRanges() const M5_ATTR_OVERRIDE { return addrRanges; } + AddrRangeList getAddrRanges() const override { return addrRanges; } protected: // Parameters VncInput *vnc; @@ -328,16 +328,16 @@ class HDLcd: public AmbaDmaDevice void dumpSettings(); protected: - bool nextPixel(Pixel &p) M5_ATTR_OVERRIDE { return parent.pxlNext(p); } + bool nextPixel(Pixel &p) override { return parent.pxlNext(p); } - void onVSyncBegin() M5_ATTR_OVERRIDE { return parent.pxlVSyncBegin(); } - void onVSyncEnd() M5_ATTR_OVERRIDE { return parent.pxlVSyncEnd(); } + void onVSyncBegin() override { return parent.pxlVSyncBegin(); } + void onVSyncEnd() override { return parent.pxlVSyncEnd(); } - void onUnderrun(unsigned x, unsigned y) M5_ATTR_OVERRIDE { + void onUnderrun(unsigned x, unsigned y) override { parent.pxlUnderrun(); } - void onFrameDone() M5_ATTR_OVERRIDE { parent.pxlFrameDone(); } + void onFrameDone() override { parent.pxlFrameDone(); } protected: HDLcd &parent; @@ -366,12 +366,12 @@ class HDLcd: public AmbaDmaDevice void abortFrame(); void dumpSettings(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; protected: - void onEndOfBlock() M5_ATTR_OVERRIDE; - void onIdle() M5_ATTR_OVERRIDE; + void onEndOfBlock() override; + void onIdle() override; HDLcd &parent; const size_t lineSize; diff --git a/src/dev/arm/kmi.hh b/src/dev/arm/kmi.hh index 9b30b3c15..e5c58f7d7 100644 --- a/src/dev/arm/kmi.hh +++ b/src/dev/arm/kmi.hh @@ -157,8 +157,8 @@ class Pl050 : public AmbaIntDevice, public VncKeyboard, public VncMouse virtual void mouseAt(uint16_t x, uint16_t y, uint8_t buttons); virtual void keyPress(uint32_t key, bool down); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_ARM_PL050_HH__ diff --git a/src/dev/arm/pl011.hh b/src/dev/arm/pl011.hh index b0f7d576d..936dd81ed 100644 --- a/src/dev/arm/pl011.hh +++ b/src/dev/arm/pl011.hh @@ -60,15 +60,15 @@ class Pl011 : public Uart, public AmbaDevice public: Pl011(const Pl011Params *p); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: // PioDevice - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick read(PacketPtr pkt) override; + Tick write(PacketPtr pkt) override; public: // Uart - void dataAvailable() M5_ATTR_OVERRIDE; + void dataAvailable() override; protected: // Interrupt handling diff --git a/src/dev/arm/pl111.hh b/src/dev/arm/pl111.hh index 08d9147a4..d22c0883e 100644 --- a/src/dev/arm/pl111.hh +++ b/src/dev/arm/pl111.hh @@ -371,8 +371,8 @@ class Pl111: public AmbaDmaDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Determine the address ranges that this device responds to. diff --git a/src/dev/arm/rtc_pl031.hh b/src/dev/arm/rtc_pl031.hh index 406857e70..8c8fa1538 100644 --- a/src/dev/arm/rtc_pl031.hh +++ b/src/dev/arm/rtc_pl031.hh @@ -125,8 +125,8 @@ class PL031 : public AmbaIntDevice */ virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; diff --git a/src/dev/arm/rv_ctrl.hh b/src/dev/arm/rv_ctrl.hh index 905fe14d9..1a55025a8 100644 --- a/src/dev/arm/rv_ctrl.hh +++ b/src/dev/arm/rv_ctrl.hh @@ -171,17 +171,17 @@ class RealViewCtrl : public BasicPioDevice * @param pkt The memory request. * @param data Where to put the data. */ - Tick read(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick read(PacketPtr pkt) override; /** * All writes are simply ignored. * @param pkt The memory request. * @param data the data */ - Tick write(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick write(PacketPtr pkt) override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: void registerDevice(DeviceFunc func, uint8_t site, uint8_t pos, @@ -206,14 +206,14 @@ class RealViewOsc RealViewOsc(RealViewOscParams *p); virtual ~RealViewOsc() {}; - void startup() M5_ATTR_OVERRIDE; + void startup() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: // RealViewCtrl::Device interface - uint32_t read() const M5_ATTR_OVERRIDE; - void write(uint32_t freq) M5_ATTR_OVERRIDE; + uint32_t read() const override; + void write(uint32_t freq) override; protected: void clockPeriod(Tick clock_period); diff --git a/src/dev/arm/timer_cpulocal.hh b/src/dev/arm/timer_cpulocal.hh index 73a2d4493..56bb359d9 100644 --- a/src/dev/arm/timer_cpulocal.hh +++ b/src/dev/arm/timer_cpulocal.hh @@ -145,8 +145,8 @@ class CpuLocalTimer : public BasicPioDevice /** Handle write for a single timer */ void write(PacketPtr pkt, Addr daddr); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; friend class CpuLocalTimer; }; @@ -186,8 +186,8 @@ class CpuLocalTimer : public BasicPioDevice */ virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; diff --git a/src/dev/arm/timer_sp804.hh b/src/dev/arm/timer_sp804.hh index c5b3bb633..73e27ca34 100644 --- a/src/dev/arm/timer_sp804.hh +++ b/src/dev/arm/timer_sp804.hh @@ -121,8 +121,8 @@ class Sp804 : public AmbaPioDevice /** Handle write for a single timer */ void write(PacketPtr pkt, Addr daddr); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** Pointer to the GIC for causing an interrupt */ @@ -160,8 +160,8 @@ class Sp804 : public AmbaPioDevice virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; diff --git a/src/dev/arm/ufs_device.hh b/src/dev/arm/ufs_device.hh index 716b1bdcb..8789cf575 100644 --- a/src/dev/arm/ufs_device.hh +++ b/src/dev/arm/ufs_device.hh @@ -173,10 +173,10 @@ class UFSHostDevice : public DmaDevice UFSHostDevice(const UFSHostDeviceParams* p); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; void checkDrain(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: /** diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh index d44afd7a9..b365f0cf3 100644 --- a/src/dev/arm/vgic.hh +++ b/src/dev/arm/vgic.hh @@ -192,8 +192,8 @@ class VGic : public PioDevice uint8_t VMBP; uint8_t VMPriMask; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; struct std::array<vcpuIntData, VGIC_CPU_MAX> vcpuData; @@ -212,8 +212,8 @@ class VGic : public PioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: Tick readVCpu(PacketPtr pkt); diff --git a/src/dev/copy_engine.hh b/src/dev/copy_engine.hh index db701d451..b33d1145d 100644 --- a/src/dev/copy_engine.hh +++ b/src/dev/copy_engine.hh @@ -106,11 +106,11 @@ class CopyEngine : public PciDevice void channelRead(PacketPtr pkt, Addr daddr, int size); void channelWrite(PacketPtr pkt, Addr daddr, int size); - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: void fetchDescriptor(Addr address); @@ -204,8 +204,8 @@ class CopyEngine : public PciDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif //__DEV_COPY_ENGINE_HH__ diff --git a/src/dev/copy_engine_defs.hh b/src/dev/copy_engine_defs.hh index afefac2b5..9a88802ed 100644 --- a/src/dev/copy_engine_defs.hh +++ b/src/dev/copy_engine_defs.hh @@ -125,7 +125,7 @@ struct Regs : public Serializable { uint32_t attnStatus; // Read clears - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + void serialize(CheckpointOut &cp) const override { SERIALIZE_SCALAR(chanCount); SERIALIZE_SCALAR(xferCap); @@ -133,7 +133,7 @@ struct Regs : public Serializable { SERIALIZE_SCALAR(attnStatus); } - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + void unserialize(CheckpointIn &cp) override { UNSERIALIZE_SCALAR(chanCount); UNSERIALIZE_SCALAR(xferCap); @@ -197,7 +197,7 @@ struct ChanRegs : public Serializable { }; CHANERR error; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + void serialize(CheckpointOut &cp) const override { paramOut(cp, "ctrl", ctrl._data); paramOut(cp, "status", status._data); @@ -207,7 +207,7 @@ struct ChanRegs : public Serializable { paramOut(cp, "error", error._data); } - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + void unserialize(CheckpointIn &cp) override { paramIn(cp, "ctrl", ctrl._data); paramIn(cp, "status", status._data); diff --git a/src/dev/disk_image.hh b/src/dev/disk_image.hh index 25483eed5..01e32440d 100644 --- a/src/dev/disk_image.hh +++ b/src/dev/disk_image.hh @@ -36,8 +36,8 @@ #define __DISK_IMAGE_HH__ #include <fstream> +#include <unordered_map> -#include "base/hashmap.hh" #include "params/CowDiskImage.hh" #include "params/DiskImage.hh" #include "params/RawDiskImage.hh" @@ -111,7 +111,7 @@ class CowDiskImage : public DiskImage struct Sector { uint8_t data[SectorSize]; }; - typedef m5::hash_map<uint64_t, Sector *> SectorTable; + typedef std::unordered_map<uint64_t, Sector *> SectorTable; protected: std::string filename; @@ -129,8 +129,8 @@ class CowDiskImage : public DiskImage void save(const std::string &file) const; void writeback(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; virtual std::streampos size() const; diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh index a7a03d520..273b21e2b 100644 --- a/src/dev/dma_device.hh +++ b/src/dev/dma_device.hh @@ -148,7 +148,7 @@ class DmaPort : public MasterPort, public Drainable bool dmaPending() const { return pendingCount > 0; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; }; class DmaDevice : public PioDevice @@ -238,11 +238,11 @@ class DmaReadFifo : public Drainable, public Serializable ~DmaReadFifo(); public: // Serializable - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: // Drainable - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; public: // FIFO access /** diff --git a/src/dev/etherlink.hh b/src/dev/etherlink.hh index 4bfb751b9..0012d0003 100644 --- a/src/dev/etherlink.hh +++ b/src/dev/etherlink.hh @@ -158,8 +158,8 @@ class EtherLink : public EtherObject virtual EtherInt *getEthPort(const std::string &if_name, int idx); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; diff --git a/src/dev/ethertap.hh b/src/dev/ethertap.hh index 9c21dfc03..b1fa08559 100644 --- a/src/dev/ethertap.hh +++ b/src/dev/ethertap.hh @@ -115,8 +115,8 @@ class EtherTap : public EtherObject virtual bool recvPacket(EthPacketPtr packet); virtual void sendDone(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; class EtherTapInt : public EtherInt diff --git a/src/dev/i2cbus.hh b/src/dev/i2cbus.hh index 3ebfa308b..2fe8052fd 100644 --- a/src/dev/i2cbus.hh +++ b/src/dev/i2cbus.hh @@ -146,8 +146,8 @@ class I2CBus : public BasicPioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif //__DEV_I2CBUS diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index 3a3efb795..5b2d60916 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -329,8 +329,8 @@ class IGbE : public EtherDevice void reset(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; virtual bool hasOutstandingEvents() { return wbEvent.scheduled() || fetchEvent.scheduled(); @@ -393,8 +393,8 @@ class IGbE : public EtherDevice virtual bool hasOutstandingEvents(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; friend class RxDescCache; @@ -504,8 +504,8 @@ class IGbE : public EtherDevice } EventWrapper<TxDescCache, &TxDescCache::nullCallback> nullEvent; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; friend class TxDescCache; @@ -535,11 +535,11 @@ class IGbE : public EtherDevice bool ethRxPkt(EthPacketPtr packet); void ethTxDone(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; }; diff --git a/src/dev/i8254xGBe_defs.hh b/src/dev/i8254xGBe_defs.hh index 92257aea7..79a9413da 100644 --- a/src/dev/i8254xGBe_defs.hh +++ b/src/dev/i8254xGBe_defs.hh @@ -759,7 +759,7 @@ struct Regs : public Serializable { uint32_t sw_fw_sync; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE + void serialize(CheckpointOut &cp) const override { paramOut(cp, "ctrl", ctrl._data); paramOut(cp, "sts", sts._data); @@ -805,7 +805,7 @@ struct Regs : public Serializable { SERIALIZE_SCALAR(sw_fw_sync); } - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE + void unserialize(CheckpointIn &cp) override { paramIn(cp, "ctrl", ctrl._data); paramIn(cp, "sts", sts._data); diff --git a/src/dev/ide_ctrl.hh b/src/dev/ide_ctrl.hh index 7917432e4..398cab299 100644 --- a/src/dev/ide_ctrl.hh +++ b/src/dev/ide_ctrl.hh @@ -154,7 +154,7 @@ class IdeController : public PciDevice Tick read(PacketPtr pkt); Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __IDE_CTRL_HH_ diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh index 79e931a29..e1ea7a27d 100644 --- a/src/dev/ide_disk.hh +++ b/src/dev/ide_disk.hh @@ -365,8 +365,8 @@ class IdeDisk : public SimObject inline Addr pciToDma(Addr pciAddr); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; diff --git a/src/dev/mips/malta.hh b/src/dev/mips/malta.hh index c5ee92e3d..cbfa55703 100755 --- a/src/dev/mips/malta.hh +++ b/src/dev/mips/malta.hh @@ -135,8 +135,8 @@ class Malta : public Platform M5_DUMMY_RETURN } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_MALTA_HH__ diff --git a/src/dev/mips/malta_cchip.hh b/src/dev/mips/malta_cchip.hh index 707cd1048..5f8baad81 100755 --- a/src/dev/mips/malta_cchip.hh +++ b/src/dev/mips/malta_cchip.hh @@ -133,8 +133,8 @@ class MaltaCChip : public BasicPioDevice */ void reqIPI(uint64_t ipreq); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __MALTA_CCHIP_HH__ diff --git a/src/dev/mips/malta_io.hh b/src/dev/mips/malta_io.hh index bea6733fc..f6fdfa53b 100755 --- a/src/dev/mips/malta_io.hh +++ b/src/dev/mips/malta_io.hh @@ -130,8 +130,8 @@ class MaltaIO : public BasicPioDevice /** Clear an Interrupt to the CPU */ void clearIntr(uint8_t interrupt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Start running. diff --git a/src/dev/mips/malta_pchip.hh b/src/dev/mips/malta_pchip.hh index 368faf9c5..b1303c9c7 100755 --- a/src/dev/mips/malta_pchip.hh +++ b/src/dev/mips/malta_pchip.hh @@ -88,8 +88,8 @@ class MaltaPChip : public BasicPioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __TSUNAMI_PCHIP_HH__ diff --git a/src/dev/multi_etherlink.hh b/src/dev/multi_etherlink.hh index 7d1352d60..68e96f862 100644 --- a/src/dev/multi_etherlink.hh +++ b/src/dev/multi_etherlink.hh @@ -222,14 +222,14 @@ class MultiEtherLink : public EtherObject } virtual EtherInt *getEthPort(const std::string &if_name, - int idx) M5_ATTR_OVERRIDE; + int idx) override; - void memWriteback() M5_ATTR_OVERRIDE; - void init() M5_ATTR_OVERRIDE; - void startup() M5_ATTR_OVERRIDE; + void memWriteback() override; + void init() override; + void startup() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_MULTIETHERLINK_HH__ diff --git a/src/dev/multi_iface.hh b/src/dev/multi_iface.hh index 0e4859ecd..5c7834d51 100644 --- a/src/dev/multi_iface.hh +++ b/src/dev/multi_iface.hh @@ -275,7 +275,7 @@ class MultiIface : public Drainable * This is a global event so process() will be called by each * simulation threads. (See further comments in the .cc file.) */ - void process() M5_ATTR_OVERRIDE; + void process() override; /** * Schedule periodic sync when resuming from a checkpoint. */ @@ -471,7 +471,7 @@ class MultiIface : public Drainable */ void initRandom(); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /** * Callback when draining is complete. diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh index 08b02027a..0e6c1bd31 100644 --- a/src/dev/ns_gige.hh +++ b/src/dev/ns_gige.hh @@ -366,10 +366,10 @@ class NSGigE : public EtherDevBase bool recvPacket(EthPacketPtr packet); void transferDone(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; }; /* diff --git a/src/dev/pcidev.hh b/src/dev/pcidev.hh index 903d83c77..2064de90e 100644 --- a/src/dev/pcidev.hh +++ b/src/dev/pcidev.hh @@ -249,14 +249,14 @@ class PciDevice : public DmaDevice * Serialize this object to the given output stream. * @param os The stream to serialize to. */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; /** * Reconstruct the state of this object from a checkpoint. * @param cp The checkpoint use. * @param section The section name of this object */ - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void unserialize(CheckpointIn &cp) override; virtual BaseSlavePort &getSlavePort(const std::string &if_name, diff --git a/src/dev/pixelpump.hh b/src/dev/pixelpump.hh index 582e1aa18..159ee79cb 100644 --- a/src/dev/pixelpump.hh +++ b/src/dev/pixelpump.hh @@ -63,8 +63,8 @@ struct DisplayTimings : public Serializable unsigned hbp, unsigned h_sync, unsigned hfp, unsigned vbp, unsigned v_sync, unsigned vfp); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** How many pixel clocks are required for one line? */ Cycles cyclesPerLine() const { @@ -151,8 +151,8 @@ class BasePixelPump BasePixelPump(EventManager &em, ClockDomain &pxl_clk, unsigned pixel_chunk); virtual ~BasePixelPump(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: // Public API /** Starting pushing pixels using the supplied display timings. */ @@ -257,14 +257,14 @@ class BasePixelPump public: PixelEvent(const char *name, BasePixelPump *parent, CallbackType func); - DrainState drain() M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + DrainState drain() override; + void drainResume() override; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - const std::string name() const M5_ATTR_OVERRIDE { return _name; } - void process() M5_ATTR_OVERRIDE { + const std::string name() const override { return _name; } + void process() override { (parent.*func)(); } diff --git a/src/dev/sinic.hh b/src/dev/sinic.hh index 41a629af1..96727b0ca 100644 --- a/src/dev/sinic.hh +++ b/src/dev/sinic.hh @@ -73,8 +73,8 @@ class Base : public EtherDevBase * Serialization stuff */ public: - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Construction/Destruction/Parameters @@ -271,7 +271,7 @@ class Device : public Base public: virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - virtual void drainResume() M5_ATTR_OVERRIDE; + virtual void drainResume() override; void prepareIO(ContextID cpu, int index); void prepareRead(ContextID cpu, int index); @@ -297,8 +297,8 @@ class Device : public Base * Serialization stuff */ public: - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; public: Device(const Params *p); diff --git a/src/dev/sparc/dtod.hh b/src/dev/sparc/dtod.hh index a7b451364..98208a992 100644 --- a/src/dev/sparc/dtod.hh +++ b/src/dev/sparc/dtod.hh @@ -63,8 +63,8 @@ class DumbTOD : public BasicPioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __DEV_BADDEV_HH__ diff --git a/src/dev/sparc/iob.hh b/src/dev/sparc/iob.hh index 033ee3867..4772e8654 100644 --- a/src/dev/sparc/iob.hh +++ b/src/dev/sparc/iob.hh @@ -142,8 +142,8 @@ class Iob : public PioDevice AddrRangeList getAddrRanges() const; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif //__DEV_SPARC_IOB_HH__ diff --git a/src/dev/sparc/mm_disk.hh b/src/dev/sparc/mm_disk.hh index 2de3cac7d..6242ed943 100644 --- a/src/dev/sparc/mm_disk.hh +++ b/src/dev/sparc/mm_disk.hh @@ -61,7 +61,7 @@ class MmDisk : public BasicPioDevice virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; }; #endif //__DEV_SPARC_MM_DISK_HH__ diff --git a/src/dev/tcp_iface.hh b/src/dev/tcp_iface.hh index d34d3d002..553f862ca 100644 --- a/src/dev/tcp_iface.hh +++ b/src/dev/tcp_iface.hh @@ -98,19 +98,18 @@ class TCPIface : public MultiIface virtual void sendRaw(void *buf, unsigned length, - const MultiHeaderPkt::AddressType dest_addr=nullptr) - M5_ATTR_OVERRIDE + const MultiHeaderPkt::AddressType dest_addr=nullptr) override { sendTCP(sock, buf, length); } - virtual bool recvRaw(void *buf, unsigned length) M5_ATTR_OVERRIDE + virtual bool recvRaw(void *buf, unsigned length) override { return recvTCP(sock, buf, length); } virtual void syncRaw(MultiHeaderPkt::MsgType sync_req, - Tick sync_tick) M5_ATTR_OVERRIDE; + Tick sync_tick) override; public: /** @@ -128,7 +127,7 @@ class TCPIface : public MultiIface unsigned multi_rank, Tick sync_start, Tick sync_repeat, EventManager *em); - ~TCPIface() M5_ATTR_OVERRIDE; + ~TCPIface() override; }; #endif diff --git a/src/dev/uart8250.hh b/src/dev/uart8250.hh index 6b255594a..367d57f73 100644 --- a/src/dev/uart8250.hh +++ b/src/dev/uart8250.hh @@ -113,8 +113,8 @@ class Uart8250 : public Uart */ virtual bool intStatus() { return status ? true : false; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __TSUNAMI_UART_HH__ diff --git a/src/dev/virtio/base.hh b/src/dev/virtio/base.hh index de68f92e1..4d4c16536 100644 --- a/src/dev/virtio/base.hh +++ b/src/dev/virtio/base.hh @@ -319,8 +319,8 @@ public: /** @{ * @name Checkpointing Interface */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** @{ * @name Low-level Device Interface @@ -595,8 +595,8 @@ class VirtIODeviceBase : public SimObject /** @{ * @name SimObject Interfaces */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** @} */ diff --git a/src/dev/virtio/fs9p.hh b/src/dev/virtio/fs9p.hh index a7fb780aa..9fb53dd2d 100644 --- a/src/dev/virtio/fs9p.hh +++ b/src/dev/virtio/fs9p.hh @@ -216,8 +216,8 @@ class VirtIO9PProxy : public VirtIO9PBase VirtIO9PProxy(Params *params); virtual ~VirtIO9PProxy(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; protected: void recvTMsg(const P9MsgHeader &header, const uint8_t *data, size_t size); diff --git a/src/dev/x86/cmos.hh b/src/dev/x86/cmos.hh index f0234da54..63a6d6a68 100644 --- a/src/dev/x86/cmos.hh +++ b/src/dev/x86/cmos.hh @@ -84,8 +84,8 @@ class Cmos : public BasicPioDevice virtual void startup(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/dev/x86/i8042.hh b/src/dev/x86/i8042.hh index fd32b4c53..bddbe9b27 100644 --- a/src/dev/x86/i8042.hh +++ b/src/dev/x86/i8042.hh @@ -120,10 +120,8 @@ class PS2Mouse : public PS2Device bool processData(uint8_t data); - void serialize(const std::string &base, - CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(const std::string &base, - CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(const std::string &base, CheckpointOut &cp) const override; + void unserialize(const std::string &base, CheckpointIn &cp) override; }; class PS2Keyboard : public PS2Device @@ -249,8 +247,8 @@ class I8042 : public BasicPioDevice Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/dev/x86/i82094aa.hh b/src/dev/x86/i82094aa.hh index d047a49da..36986d2c4 100644 --- a/src/dev/x86/i82094aa.hh +++ b/src/dev/x86/i82094aa.hh @@ -105,14 +105,14 @@ class I82094AA : public BasicPioDevice, public IntDevice BaseMasterPort &getMasterPort(const std::string &if_name, PortID idx = InvalidPortID); - Tick recvResponse(PacketPtr pkt) M5_ATTR_OVERRIDE; + Tick recvResponse(PacketPtr pkt) override; void signalInterrupt(int line); void raiseInterruptPin(int number); void lowerInterruptPin(int number); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/dev/x86/i8237.hh b/src/dev/x86/i8237.hh index 481983b8e..49c1fd924 100644 --- a/src/dev/x86/i8237.hh +++ b/src/dev/x86/i8237.hh @@ -59,8 +59,8 @@ class I8237 : public BasicPioDevice Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/dev/x86/i8254.hh b/src/dev/x86/i8254.hh index c4f04bd42..86d4f0323 100644 --- a/src/dev/x86/i8254.hh +++ b/src/dev/x86/i8254.hh @@ -109,8 +109,8 @@ class I8254 : public BasicPioDevice pit.writeControl(val); } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; virtual void startup(); diff --git a/src/dev/x86/i8259.hh b/src/dev/x86/i8259.hh index 567ad7a32..0b2cee01c 100644 --- a/src/dev/x86/i8259.hh +++ b/src/dev/x86/i8259.hh @@ -109,8 +109,8 @@ class I8259 : public BasicPioDevice, public IntDevice void lowerInterruptPin(int number); int getVector(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/dev/x86/speaker.hh b/src/dev/x86/speaker.hh index 3c879060f..9f1656370 100644 --- a/src/dev/x86/speaker.hh +++ b/src/dev/x86/speaker.hh @@ -73,8 +73,8 @@ class Speaker : public BasicPioDevice Tick write(PacketPtr pkt); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace X86ISA diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh index 8cc1ca84e..c2c7abf2d 100644 --- a/src/kern/kernel_stats.hh +++ b/src/kern/kernel_stats.hh @@ -80,8 +80,8 @@ class Statistics : public Serializable void swpipl(int ipl); public: - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; } // namespace Kernel diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh index 26c9637f0..0ee0696d8 100644 --- a/src/mem/cache/cache.hh +++ b/src/mem/cache/cache.hh @@ -435,8 +435,8 @@ class Cache : public BaseCache /** serialize the state of the caches * We currently don't support checkpointing cache state, so this panics. */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** @@ -455,7 +455,7 @@ class CacheBlkVisitorWrapper : public CacheBlkVisitor CacheBlkVisitorWrapper(Cache &_cache, VisitorPtr _visitor) : cache(_cache), visitor(_visitor) {} - bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + bool operator()(CacheBlk &blk) override { return (cache.*visitor)(blk); } @@ -477,7 +477,7 @@ class CacheBlkIsDirtyVisitor : public CacheBlkVisitor CacheBlkIsDirtyVisitor() : _isDirty(false) {} - bool operator()(CacheBlk &blk) M5_ATTR_OVERRIDE { + bool operator()(CacheBlk &blk) override { if (blk.isDirty()) { _isDirty = true; return false; diff --git a/src/mem/cache/mshr_queue.hh b/src/mem/cache/mshr_queue.hh index 308d371fe..eebfed827 100644 --- a/src/mem/cache/mshr_queue.hh +++ b/src/mem/cache/mshr_queue.hh @@ -255,7 +255,7 @@ class MSHRQueue : public Drainable return readyList.empty() ? MaxTick : readyList.front()->readyTime; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; }; #endif //__MEM_CACHE_MSHR_QUEUE_HH__ diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh index 2798c823f..af17252d8 100644 --- a/src/mem/cache/prefetch/stride.hh +++ b/src/mem/cache/prefetch/stride.hh @@ -48,7 +48,8 @@ #ifndef __MEM_CACHE_PREFETCH_STRIDE_HH__ #define __MEM_CACHE_PREFETCH_STRIDE_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "mem/cache/prefetch/queued.hh" #include "params/StridePrefetcher.hh" @@ -99,7 +100,7 @@ class StridePrefetcher : public QueuedPrefetcher const int pcTableAssoc; const int pcTableSets; const std::string _name; - m5::hash_map<int, StrideEntry**> entries; + std::unordered_map<int, StrideEntry**> entries; StrideEntry** allocateNewContext(int context); }; diff --git a/src/mem/cache/tags/base_set_assoc.hh b/src/mem/cache/tags/base_set_assoc.hh index 9fe23ea91..e415603d9 100644 --- a/src/mem/cache/tags/base_set_assoc.hh +++ b/src/mem/cache/tags/base_set_assoc.hh @@ -407,7 +407,7 @@ public: * * \param visitor Visitor to call on each block. */ - void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE { + void forEachBlk(CacheBlkVisitor &visitor) override { for (unsigned i = 0; i < numSets * assoc; ++i) { if (!visitor(blks[i])) return; diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh index def4c9b2c..1728ee48a 100644 --- a/src/mem/cache/tags/fa_lru.hh +++ b/src/mem/cache/tags/fa_lru.hh @@ -49,8 +49,8 @@ #define __MEM_CACHE_TAGS_FA_LRU_HH__ #include <list> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/cache/tags/base.hh" #include "mem/cache/blk.hh" #include "mem/packet.hh" @@ -109,7 +109,7 @@ class FALRU : public BaseTags FALRUBlk *tail; /** Hash table type mapping addresses to cache block pointers. */ - typedef m5::hash_map<Addr, FALRUBlk *, m5::hash<Addr> > hash_t; + typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t; /** Iterator into the address hash table. */ typedef hash_t::const_iterator tagIterator; @@ -322,7 +322,7 @@ public: * * \param visitor Visitor to call on each block. */ - void forEachBlk(CacheBlkVisitor &visitor) M5_ATTR_OVERRIDE { + void forEachBlk(CacheBlkVisitor &visitor) override { for (int i = 0; i < numBlocks; i++) { if (!visitor(blks[i])) return; diff --git a/src/mem/coherent_xbar.hh b/src/mem/coherent_xbar.hh index d431a1d24..e99e9374f 100644 --- a/src/mem/coherent_xbar.hh +++ b/src/mem/coherent_xbar.hh @@ -258,7 +258,7 @@ class CoherentXBar : public BaseXBar * responses from so we can determine which snoop responses we * generated and which ones were merely forwarded. */ - m5::hash_set<RequestPtr> outstandingSnoop; + std::unordered_set<RequestPtr> outstandingSnoop; /** * Keep a pointer to the system to be allow to querying memory system diff --git a/src/mem/comm_monitor.hh b/src/mem/comm_monitor.hh index fb8f5eeb7..df61b0b80 100644 --- a/src/mem/comm_monitor.hh +++ b/src/mem/comm_monitor.hh @@ -74,17 +74,17 @@ class CommMonitor : public MemObject */ CommMonitor(Params* params); - void init() M5_ATTR_OVERRIDE; - void regStats() M5_ATTR_OVERRIDE; - void startup() M5_ATTR_OVERRIDE; - void regProbePoints() M5_ATTR_OVERRIDE; + void init() override; + void regStats() override; + void startup() override; + void regProbePoints() override; public: // MemObject interfaces BaseMasterPort& getMasterPort(const std::string& if_name, - PortID idx = InvalidPortID) M5_ATTR_OVERRIDE; + PortID idx = InvalidPortID) override; BaseSlavePort& getSlavePort(const std::string& if_name, - PortID idx = InvalidPortID) M5_ATTR_OVERRIDE; + PortID idx = InvalidPortID) override; private: diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh index bf0be04a7..a7f3e5602 100644 --- a/src/mem/dram_ctrl.hh +++ b/src/mem/dram_ctrl.hh @@ -872,14 +872,14 @@ class DRAMCtrl : public AbstractMemory DRAMCtrl(const DRAMCtrlParams* p); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); - virtual void init() M5_ATTR_OVERRIDE; - virtual void startup() M5_ATTR_OVERRIDE; - virtual void drainResume() M5_ATTR_OVERRIDE; + virtual void init() override; + virtual void startup() override; + virtual void drainResume() override; protected: diff --git a/src/mem/dramsim2.hh b/src/mem/dramsim2.hh index 5d8e64282..77486de88 100644 --- a/src/mem/dramsim2.hh +++ b/src/mem/dramsim2.hh @@ -45,8 +45,8 @@ #define __MEM_DRAMSIM2_HH__ #include <queue> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/abstract_mem.hh" #include "mem/dramsim2_wrapper.hh" #include "mem/qport.hh" @@ -114,8 +114,8 @@ class DRAMSim2 : public AbstractMemory * done so that we can return the right packet on completion from * DRAMSim. */ - m5::hash_map<Addr, std::queue<PacketPtr> > outstandingReads; - m5::hash_map<Addr, std::queue<PacketPtr> > outstandingWrites; + std::unordered_map<Addr, std::queue<PacketPtr> > outstandingReads; + std::unordered_map<Addr, std::queue<PacketPtr> > outstandingWrites; /** * Count the number of outstanding transactions so that we can @@ -189,7 +189,7 @@ class DRAMSim2 : public AbstractMemory */ void writeComplete(unsigned id, uint64_t addr, uint64_t cycle); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); diff --git a/src/mem/mem_checker.hh b/src/mem/mem_checker.hh index 0ec0f08df..6ceca74a7 100644 --- a/src/mem/mem_checker.hh +++ b/src/mem/mem_checker.hh @@ -44,9 +44,9 @@ #include <list> #include <map> #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/misc.hh" #include "base/types.hh" #include "debug/MemChecker.hh" @@ -184,7 +184,7 @@ class MemChecker : public SimObject * Map of Serial --> Transaction of all writes in cluster; contains * all, in-flight or already completed. */ - m5::hash_map<Serial, Transaction> writes; + std::unordered_map<Serial, Transaction> writes; private: Tick completeMax; @@ -509,7 +509,7 @@ class MemChecker : public SimObject * * Access via getByteTracker()! */ - m5::hash_map<Addr, ByteTracker> byte_trackers; + std::unordered_map<Addr, ByteTracker> byte_trackers; }; inline MemChecker::Serial diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh index f622bbbed..b9e020460 100644 --- a/src/mem/multi_level_page_table.hh +++ b/src/mem/multi_level_page_table.hh @@ -153,7 +153,7 @@ public: void unmap(Addr vaddr, int64_t size); bool isUnmapped(Addr vaddr, int64_t size); bool lookup(Addr vaddr, TheISA::TlbEntry &entry); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __MEM_MULTI_LEVEL_PAGE_TABLE_HH__ diff --git a/src/mem/packet_queue.hh b/src/mem/packet_queue.hh index 4eabd1bc4..e9cf34bb0 100644 --- a/src/mem/packet_queue.hh +++ b/src/mem/packet_queue.hh @@ -188,7 +188,7 @@ class PacketQueue : public Drainable */ void retry(); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; }; class ReqPacketQueue : public PacketQueue diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index ddec104a7..7dcbbd65a 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -38,10 +38,10 @@ #define __MEM_PAGE_TABLE_HH__ #include <string> +#include <unordered_map> #include "arch/isa_traits.hh" #include "arch/tlb.hh" -#include "base/hashmap.hh" #include "base/types.hh" #include "config/the_isa.hh" #include "mem/request.hh" @@ -200,7 +200,7 @@ class PageTableBase : public Serializable class FuncPageTable : public PageTableBase { private: - typedef m5::hash_map<Addr, TheISA::TlbEntry> PTable; + typedef std::unordered_map<Addr, TheISA::TlbEntry> PTable; typedef PTable::iterator PTableItr; PTable pTable; @@ -235,8 +235,8 @@ class FuncPageTable : public PageTableBase */ bool lookup(Addr vaddr, TheISA::TlbEntry &entry); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; /** diff --git a/src/mem/physical.hh b/src/mem/physical.hh index c577cd3ea..7f4c975f0 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -197,7 +197,7 @@ class PhysicalMemory : public Serializable * * @param os stream to serialize to */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; /** * Serialize a specific store. @@ -214,7 +214,7 @@ class PhysicalMemory : public Serializable * serialization, this action is independent of how the address * ranges are mapped to logical memories in the guest system. */ - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void unserialize(CheckpointIn &cp) override; /** * Unserialize a specific backing store, identified by a section. diff --git a/src/mem/probes/base.hh b/src/mem/probes/base.hh index ccb5ca749..78e6f6b8d 100644 --- a/src/mem/probes/base.hh +++ b/src/mem/probes/base.hh @@ -65,7 +65,7 @@ class BaseMemProbe : public SimObject public: BaseMemProbe(BaseMemProbeParams *params); - void regProbeListeners() M5_ATTR_OVERRIDE; + void regProbeListeners() override; protected: /** @@ -82,7 +82,7 @@ class BaseMemProbe : public SimObject : ProbeListenerArgBase(pm, name), parent(_parent) {} - void notify(const ProbePoints::PacketInfo &pkt_info) M5_ATTR_OVERRIDE { + void notify(const ProbePoints::PacketInfo &pkt_info) override { parent.handleRequest(pkt_info); } diff --git a/src/mem/probes/mem_trace.hh b/src/mem/probes/mem_trace.hh index 51f272812..d34235eef 100644 --- a/src/mem/probes/mem_trace.hh +++ b/src/mem/probes/mem_trace.hh @@ -52,8 +52,7 @@ class MemTraceProbe : public BaseMemProbe MemTraceProbe(MemTraceProbeParams *params); protected: - void handleRequest(const ProbePoints::PacketInfo &pkt_info) \ - M5_ATTR_OVERRIDE; + void handleRequest(const ProbePoints::PacketInfo &pkt_info) override; /** * Callback to flush and close all open output streams on exit. If diff --git a/src/mem/probes/stack_dist.hh b/src/mem/probes/stack_dist.hh index 8374672da..66b75109a 100644 --- a/src/mem/probes/stack_dist.hh +++ b/src/mem/probes/stack_dist.hh @@ -52,11 +52,10 @@ class StackDistProbe : public BaseMemProbe public: StackDistProbe(StackDistProbeParams *params); - void regStats() M5_ATTR_OVERRIDE; + void regStats() override; protected: - void handleRequest(const ProbePoints::PacketInfo &pkt_info) \ - M5_ATTR_OVERRIDE; + void handleRequest(const ProbePoints::PacketInfo &pkt_info) override; protected: // Cache line size to simulate diff --git a/src/mem/ruby/common/Address.hh b/src/mem/ruby/common/Address.hh index 90955447b..ded6f6f12 100644 --- a/src/mem/ruby/common/Address.hh +++ b/src/mem/ruby/common/Address.hh @@ -33,7 +33,6 @@ #include <iomanip> #include <iostream> -#include "base/hashmap.hh" #include "base/types.hh" const uint32_t ADDRESS_WIDTH = 64; // address width in bytes diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh index ebd44080b..9f12415c5 100644 --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_PROFILER_ADDRESSPROFILER_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/RubyRequest.hh" #include "mem/ruby/common/Address.hh" @@ -44,7 +44,7 @@ class Set; class AddressProfiler { public: - typedef m5::hash_map<Addr, AccessTraceForAddress> AddressMap; + typedef std::unordered_map<Addr, AccessTraceForAddress> AddressMap; public: AddressProfiler(int num_of_sequencers, Profiler *profiler); diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh index 146beadd6..7e45e8aeb 100644 --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -50,7 +50,6 @@ #include <vector> #include "base/callback.hh" -#include "base/hashmap.hh" #include "base/statistics.hh" #include "mem/protocol/AccessType.hh" #include "mem/protocol/PrefetchBit.hh" diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc index 6e4022ea6..a8a3ba949 100644 --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -113,7 +113,7 @@ CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) if (m_cache[cacheSet][it->second]->m_Permission != AccessPermission_NotPresent) @@ -129,7 +129,7 @@ CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, { assert(tag == makeLineAddress(tag)); // search the set for the tags - m5::hash_map<Addr, int>::const_iterator it = m_tag_index.find(tag); + auto it = m_tag_index.find(tag); if (it != m_tag_index.end()) return it->second; return -1; // Not found diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh index 7ce674e61..72805b32b 100644 --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -31,9 +31,9 @@ #define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/statistics.hh" #include "mem/protocol/CacheRequestType.hh" #include "mem/protocol/CacheResourceType.hh" @@ -168,7 +168,7 @@ class CacheMemory : public SimObject // The first index is the # of cache lines. // The second index is the the amount associativity. - m5::hash_map<Addr, int> m_tag_index; + std::unordered_map<Addr, int> m_tag_index; std::vector<std::vector<AbstractCacheEntry*> > m_cache; AbstractReplacementPolicy *m_replacementPolicy_ptr; diff --git a/src/mem/ruby/structures/PerfectCacheMemory.hh b/src/mem/ruby/structures/PerfectCacheMemory.hh index 2b8b87628..61d5e1244 100644 --- a/src/mem/ruby/structures/PerfectCacheMemory.hh +++ b/src/mem/ruby/structures/PerfectCacheMemory.hh @@ -29,7 +29,8 @@ #ifndef __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ #define __MEM_RUBY_STRUCTURES_PERFECTCACHEMEMORY_HH__ -#include "base/hashmap.hh" +#include <unordered_map> + #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/common/Address.hh" @@ -87,7 +88,7 @@ class PerfectCacheMemory PerfectCacheMemory& operator=(const PerfectCacheMemory& obj); // Data Members (m_prefix) - m5::hash_map<Addr, PerfectCacheLineState<ENTRY> > m_map; + std::unordered_map<Addr, PerfectCacheLineState<ENTRY> > m_map; }; template<class ENTRY> diff --git a/src/mem/ruby/structures/PersistentTable.hh b/src/mem/ruby/structures/PersistentTable.hh index a4604fce8..e5296d1e8 100644 --- a/src/mem/ruby/structures/PersistentTable.hh +++ b/src/mem/ruby/structures/PersistentTable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_PERSISTENTTABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/AccessType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/MachineID.hh" @@ -77,7 +77,7 @@ class PersistentTable PersistentTable& operator=(const PersistentTable& obj); // Data Members (m_prefix) - typedef m5::hash_map<Addr, PersistentTableEntry> AddressMap; + typedef std::unordered_map<Addr, PersistentTableEntry> AddressMap; AddressMap m_map; }; diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh index f5f31458b..75fe71dfb 100644 --- a/src/mem/ruby/structures/RubyMemoryControl.hh +++ b/src/mem/ruby/structures/RubyMemoryControl.hh @@ -60,7 +60,7 @@ class RubyMemoryControl : public AbstractMemory, public Consumer virtual BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; void wakeup(); void setDescription(const std::string& name) { m_description = name; }; diff --git a/src/mem/ruby/structures/TBETable.hh b/src/mem/ruby/structures/TBETable.hh index 4a24a5b13..a39c5af2e 100644 --- a/src/mem/ruby/structures/TBETable.hh +++ b/src/mem/ruby/structures/TBETable.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_STRUCTURES_TBETABLE_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/ruby/common/Address.hh" template<class ENTRY> @@ -63,7 +63,7 @@ class TBETable TBETable& operator=(const TBETable& obj); // Data Members (m_prefix) - m5::hash_map<Addr, ENTRY> m_map; + std::unordered_map<Addr, ENTRY> m_map; private: int m_number_of_TBEs; diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh index 44110cf9f..822b370e8 100644 --- a/src/mem/ruby/system/CacheRecorder.hh +++ b/src/mem/ruby/system/CacheRecorder.hh @@ -37,7 +37,6 @@ #include <vector> -#include "base/hashmap.hh" #include "base/types.hh" #include "mem/protocol/RubyRequestType.hh" #include "mem/ruby/common/Address.hh" diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh index f9d1b630e..1d5451f6e 100644 --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -108,7 +108,7 @@ class DMASequencer : public MemObject // A pointer to the controller is needed for atomic support. void setController(AbstractController* _cntrl) { m_controller = _cntrl; } uint32_t getId() { return m_version; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /* SLICC callback */ void dataCallback(const DataBlock & dblk); diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index cbcc678d3..98fab8c4e 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -161,7 +161,7 @@ class RubyPort : public MemObject // void setController(AbstractController* _cntrl) { m_controller = _cntrl; } uint32_t getId() { return m_version; } - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; protected: void ruby_hit_callback(PacketPtr pkt); diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh index 7026f6756..23974e924 100644 --- a/src/mem/ruby/system/RubySystem.hh +++ b/src/mem/ruby/system/RubySystem.hh @@ -94,9 +94,9 @@ class RubySystem : public ClockedObject void resetStats(); void memWriteback(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; - void drainResume() M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; + void drainResume() override; void process(); void startup(); bool functionalRead(Packet *ptr); diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index aa4ac742a..26db6b6f8 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -634,10 +634,10 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) template <class KEY, class VALUE> std::ostream & -operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map) +operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map) { - typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin(); - typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end(); + auto i = map.begin(); + auto end = map.end(); out << "["; for (; i != end; ++i) diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 4716aa653..47af7ea1e 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -30,8 +30,8 @@ #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__ #include <iostream> +#include <unordered_map> -#include "base/hashmap.hh" #include "mem/protocol/MachineType.hh" #include "mem/protocol/RubyRequestType.hh" #include "mem/protocol/SequencerRequestType.hh" @@ -185,7 +185,7 @@ class Sequencer : public RubyPort Cycles m_data_cache_hit_latency; Cycles m_inst_cache_hit_latency; - typedef m5::hash_map<Addr, SequencerRequest*> RequestTable; + typedef std::unordered_map<Addr, SequencerRequest*> RequestTable; RequestTable m_writeRequestTable; RequestTable m_readRequestTable; // Global outstanding request count, across all request tables diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh index 98c41623f..c5b932bf0 100644 --- a/src/mem/simple_mem.hh +++ b/src/mem/simple_mem.hh @@ -185,7 +185,7 @@ class SimpleMemory : public AbstractMemory SimpleMemory(const SimpleMemoryParams *p); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; BaseSlavePort& getSlavePort(const std::string& if_name, PortID idx = InvalidPortID); diff --git a/src/mem/snoop_filter.hh b/src/mem/snoop_filter.hh index 407b6f7f1..2a8d1ce21 100755 --- a/src/mem/snoop_filter.hh +++ b/src/mem/snoop_filter.hh @@ -45,9 +45,9 @@ #ifndef __MEM_SNOOP_FILTER_HH__ #define __MEM_SNOOP_FILTER_HH__ +#include <unordered_map> #include <utility> -#include "base/hashmap.hh" #include "mem/packet.hh" #include "mem/port.hh" #include "mem/qport.hh" @@ -218,7 +218,7 @@ class SnoopFilter : public SimObject { /** * HashMap of SnoopItems indexed by line address */ - typedef m5::hash_map<Addr, SnoopItem> SnoopFilterCache; + typedef std::unordered_map<Addr, SnoopItem> SnoopFilterCache; /** * Simple factory methods for standard return values. diff --git a/src/mem/xbar.hh b/src/mem/xbar.hh index 79e9a5380..251ad62cb 100644 --- a/src/mem/xbar.hh +++ b/src/mem/xbar.hh @@ -52,9 +52,9 @@ #define __MEM_XBAR_HH__ #include <deque> +#include <unordered_map> #include "base/addr_range_map.hh" -#include "base/hashmap.hh" #include "base/types.hh" #include "mem/mem_object.hh" #include "mem/qport.hh" @@ -114,7 +114,7 @@ class BaseXBar : public MemObject * * @return 1 if busy or waiting to retry, or 0 if idle */ - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; /** * Get the crossbar layer's name @@ -327,7 +327,7 @@ class BaseXBar : public MemObject * the underlying Request pointer inside the Packet stays * constant. */ - m5::unordered_map<RequestPtr, PortID> routeTo; + std::unordered_map<RequestPtr, PortID> routeTo; /** all contigous ranges seen by this crossbar */ AddrRangeList xbarRanges; diff --git a/src/sim/clock_domain.hh b/src/sim/clock_domain.hh index e0dce973b..cc26d7bbd 100644 --- a/src/sim/clock_domain.hh +++ b/src/sim/clock_domain.hh @@ -239,8 +239,8 @@ class SrcClockDomain : public ClockDomain void startup(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: /** diff --git a/src/sim/dvfs_handler.hh b/src/sim/dvfs_handler.hh index 6e495fff5..f587f7c25 100644 --- a/src/sim/dvfs_handler.hh +++ b/src/sim/dvfs_handler.hh @@ -198,8 +198,8 @@ class DVFSHandler : public SimObject */ bool isEnabled() const { return enableHandler; } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: typedef std::map<DomainID, SrcClockDomain*> Domains; diff --git a/src/sim/eventq.cc b/src/sim/eventq.cc index 604de4a71..698ecd116 100644 --- a/src/sim/eventq.cc +++ b/src/sim/eventq.cc @@ -35,9 +35,9 @@ #include <cassert> #include <iostream> #include <string> +#include <unordered_map> #include <vector> -#include "base/hashmap.hh" #include "base/misc.hh" #include "base/trace.hh" #include "cpu/smt.hh" @@ -319,7 +319,7 @@ EventQueue::dump() const bool EventQueue::debugVerify() const { - m5::hash_map<long, bool> map; + std::unordered_map<long, bool> map; Tick time = 0; short priority = 0; diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index db134a4be..184d6ec3b 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -358,8 +358,8 @@ class Event : public EventBase, public Serializable virtual BaseGlobalEvent *globalEvent() { return NULL; } #ifndef SWIG - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; #endif }; diff --git a/src/sim/fd_entry.hh b/src/sim/fd_entry.hh index e0fd0b0a2..0cbb769b5 100644 --- a/src/sim/fd_entry.hh +++ b/src/sim/fd_entry.hh @@ -56,8 +56,8 @@ class FDEntry : public Serializable fileOffset(0), filename(""), driver(NULL) { } - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** * Check if the target file descriptor is in use. diff --git a/src/sim/process.hh b/src/sim/process.hh index 43d1a4edc..b3a33bcd9 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -122,7 +122,7 @@ class Process : public SimObject virtual void initState(); - DrainState drain() M5_ATTR_OVERRIDE; + DrainState drain() override; public: @@ -223,8 +223,8 @@ class Process : public SimObject */ bool map(Addr vaddr, Addr paddr, int size, bool cacheable = true); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; // diff --git a/src/sim/root.hh b/src/sim/root.hh index 1c330e2c4..4d9c63a6b 100644 --- a/src/sim/root.hh +++ b/src/sim/root.hh @@ -106,14 +106,14 @@ class Root : public SimObject /** Schedule the timesync event at loadState() so that curTick is correct */ - void loadState(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void loadState(CheckpointIn &cp) override; /** Schedule the timesync event at initState() when not unserializing */ void initState(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif // __SIM_ROOT_HH__ diff --git a/src/sim/serialize.cc b/src/sim/serialize.cc index f9a945b95..90cb5e288 100644 --- a/src/sim/serialize.cc +++ b/src/sim/serialize.cc @@ -487,8 +487,8 @@ class Globals : public Serializable Globals() : unserializedCurTick(0) {} - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; Tick unserializedCurTick; }; diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh index 8a384019a..dbbc5174f 100644 --- a/src/sim/sim_events.hh +++ b/src/sim/sim_events.hh @@ -92,8 +92,8 @@ class LocalSimLoopExitEvent : public Event virtual const char *description() const; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; static Serializable *createForUnserialize(CheckpointIn &cp, const std::string §ion); }; diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh index d2cedf5be..7c1452f01 100644 --- a/src/sim/sim_object.hh +++ b/src/sim/sim_object.hh @@ -184,7 +184,7 @@ class SimObject : public EventManager, public Serializable, public Drainable * Provide a default implementation of the drain interface for * objects that don't need draining. */ - DrainState drain() M5_ATTR_OVERRIDE { return DrainState::Drained; } + DrainState drain() override { return DrainState::Drained; } /** * Write back dirty buffers to memory using functional writes. @@ -209,8 +209,8 @@ class SimObject : public EventManager, public Serializable, public Drainable */ virtual void memInvalidate() {}; - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE {}; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE {}; + void serialize(CheckpointOut &cp) const override {}; + void unserialize(CheckpointIn &cp) override {}; /** * Serialize all SimObjects in the system. diff --git a/src/sim/system.hh b/src/sim/system.hh index 82096826d..be0538839 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -519,10 +519,10 @@ class System : public MemObject ContextID assigned = InvalidContextID); void replaceThreadContext(ThreadContext *tc, ContextID context_id); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; - void drainResume() M5_ATTR_OVERRIDE; + void drainResume() override; public: Counter totalNumInsts; diff --git a/src/sim/ticked_object.hh b/src/sim/ticked_object.hh index 97750873f..c3c6a0153 100644 --- a/src/sim/ticked_object.hh +++ b/src/sim/ticked_object.hh @@ -164,8 +164,8 @@ class Ticked : public Serializable } /** Checkpoint lastStopped */ - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; /** Action to call on the clock tick */ virtual void evaluate() = 0; @@ -199,8 +199,8 @@ class TickedObject : public ClockedObject, public Ticked /** Pass on regStats, serialize etc. onto Ticked */ void regStats(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; }; #endif /* __SIM_TICKED_OBJECT_HH__ */ diff --git a/src/sim/voltage_domain.hh b/src/sim/voltage_domain.hh index 596daba40..d22556083 100644 --- a/src/sim/voltage_domain.hh +++ b/src/sim/voltage_domain.hh @@ -128,8 +128,8 @@ class VoltageDomain : public SimObject void regStats(); - void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; - void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; + void serialize(CheckpointOut &cp) const override; + void unserialize(CheckpointIn &cp) override; private: typedef std::vector<double> Voltages; |