Ruby: Convert AccessModeType to RubyAccessMode

This patch converts AccessModeType to RubyAccessMode so that both the
protocol dependent and independent code uses the same access mode.

21 files changed, 50 insertions, 55 deletions

diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc
index a33351312..9eed7270b 100644
--- a/src/cpu/testers/rubytest/Check.cc
+++ b/src/cpu/testers/rubytest/Check.cc
@@ -44,7 +44,7 @@ Check::Check(const Address& address, const Address& pc,
     pickInitiatingNode();
     changeAddress(address);
     m_pc = pc;
-    m_access_mode = AccessModeType(random() % AccessModeType_NUM);
+    m_access_mode = RubyAccessMode(random() % RubyAccessMode_NUM);
     m_store_count = 0;
 }
 
diff --git a/src/cpu/testers/rubytest/Check.hh b/src/cpu/testers/rubytest/Check.hh
index 1ce795a21..d16c10f57 100644
--- a/src/cpu/testers/rubytest/Check.hh
+++ b/src/cpu/testers/rubytest/Check.hh
@@ -33,7 +33,7 @@
 #include <iostream>
 
 #include "cpu/testers/rubytest/RubyTester.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/TesterStatus.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -73,7 +73,7 @@ class Check
     NodeID m_initiatingNode;
     Address m_address;
     Address m_pc;
-    AccessModeType m_access_mode;
+    RubyAccessMode m_access_mode;
     int m_num_cpu_sequencers;
     RubyTester* m_tester_ptr;
 };
diff --git a/src/mem/protocol/MESI_CMP_directory-msg.sm b/src/mem/protocol/MESI_CMP_directory-msg.sm
index dff49a8c8..2292ac1d1 100644
--- a/src/mem/protocol/MESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MESI_CMP_directory-msg.sm
@@ -62,7 +62,7 @@ enumeration(CoherenceResponseType, desc="...") {
 structure(RequestMsg, desc="...", interface="NetworkMessage") {
   Address Address,              desc="Physical address for this request";
   CoherenceRequestType Type,    desc="Type of request (GetS, GetX, PutX, etc)";
-  AccessModeType AccessMode,    desc="user/supervisor access type";
+  RubyAccessMode AccessMode,    desc="user/supervisor access type";
   MachineID Requestor      ,    desc="What component request";
   NetDest Destination,          desc="What components receive the request, includes MachineType and num";
   MessageSizeType MessageSize,  desc="size category of the message";
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm
index c901fb4ff..07cc51c9a 100644
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -84,7 +84,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   DataBlock DataBlk,           desc="data for the cache line (DMA WRITE request)";
   int Acks,                    desc="How many acks to expect";
   MessageSizeType MessageSize, desc="size category of the message";
-  AccessModeType AccessMode,    desc="user/supervisor access type";
+  RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 7683b485f..f801bebd8 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -149,7 +149,7 @@ machine(L1Cache, "Token protocol")
 
     AccessType AccessType,                desc="Type of request (used for profiling)";
     Time IssueTime,                       desc="Time the request was issued";
-    AccessModeType AccessMode,    desc="user/supervisor access type";
+    RubyAccessMode AccessMode,    desc="user/supervisor access type";
     PrefetchBit Prefetch,         desc="Is this a prefetch request";
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 5cad4d448..c411d1c4b 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -424,7 +424,7 @@ machine(Directory, "Token protocol")
         out_msg.Destination.add(map_Address_to_Directory(address));
         out_msg.MessageSize := MessageSizeType:Persistent_Control;
         out_msg.Prefetch := PrefetchBit:No;
-        out_msg.AccessMode := AccessModeType:SupervisorMode;
+        out_msg.AccessMode := RubyAccessMode:Supervisor;
       }
       markPersistentEntries(address);
       starving := true;
@@ -466,7 +466,7 @@ machine(Directory, "Token protocol")
         out_msg.RetryNum := 0;
         out_msg.MessageSize := MessageSizeType:Broadcast_Control;
         out_msg.Prefetch := PrefetchBit:No;
-        out_msg.AccessMode := AccessModeType:SupervisorMode;
+        out_msg.AccessMode := RubyAccessMode:Supervisor;
       }
     }
   }
@@ -494,7 +494,7 @@ machine(Directory, "Token protocol")
         out_msg.Destination.add(map_Address_to_Directory(address));
         out_msg.MessageSize := MessageSizeType:Persistent_Control;
         out_msg.Prefetch := PrefetchBit:No;
-        out_msg.AccessMode := AccessModeType:SupervisorMode;
+        out_msg.AccessMode := RubyAccessMode:Supervisor;
       }
       markPersistentEntries(address);
       starving := true;
@@ -532,7 +532,7 @@ machine(Directory, "Token protocol")
         out_msg.RetryNum := 0;
         out_msg.MessageSize := MessageSizeType:Broadcast_Control;
         out_msg.Prefetch := PrefetchBit:No;
-        out_msg.AccessMode := AccessModeType:SupervisorMode;
+        out_msg.AccessMode := RubyAccessMode:Supervisor;
       }
     }
   }
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm
index fd7266c99..6f1504d54 100644
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_token-msg.sm
@@ -78,7 +78,7 @@ structure(PersistentMsg, desc="...", interface="NetworkMessage") {
   MachineID Requestor,            desc="Node who initiated the request";
   NetDest Destination,             desc="Destination set";
   MessageSizeType MessageSize, desc="size category of the message";
-  AccessModeType AccessMode,    desc="user/supervisor access type";
+  RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 }
 
@@ -91,7 +91,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") {
   bool isLocal,                    desc="Is this request from a local L1";
   int RetryNum,                    desc="retry sequence number";
   MessageSizeType MessageSize, desc="size category of the message";
-  AccessModeType AccessMode,    desc="user/supervisor access type";
+  RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 }
 
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index e3eb8ebeb..7258e9ccd 100644
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -193,10 +193,11 @@ enumeration(AccessType, desc="...") {
   Write, desc="Writing to cache";
 }
 
-// AccessModeType
-enumeration(AccessModeType, default="AccessModeType_UserMode", desc="...") {
-  SupervisorMode, desc="Supervisor mode";
-  UserMode,       desc="User mode";
+// RubyAccessMode
+enumeration(RubyAccessMode, default="RubyAccessMode_User", desc="...") {
+  Supervisor, desc="Supervisor mode";
+  User,       desc="User mode";
+  Device, desc="Device mode";
 }
 
 enumeration(PrefetchBit, default="PrefetchBit_No", desc="...") {
@@ -212,7 +213,7 @@ structure(CacheMsg, desc="...", interface="Message") {
   Address PhysicalAddress,   desc="Physical address for this request";
   CacheRequestType Type,     desc="Type of request (LD, ST, etc)";
   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
-  AccessModeType AccessMode, desc="user/supervisor access type";
+  RubyAccessMode AccessMode, desc="user/supervisor access type";
   int Size,                  desc="size in bytes of access";
   PrefetchBit Prefetch,      desc="Is this a prefetch request";
 }
@@ -223,7 +224,7 @@ structure(SequencerMsg, desc="...", interface="Message") {
   Address PhysicalAddress,   desc="Physical address for this request";
   SequencerRequestType Type,     desc="Type of request (LD, ST, etc)";
   Address ProgramCounter,    desc="Program counter of the instruction that caused the miss";
-  AccessModeType AccessMode, desc="user/supervisor access type";
+  RubyAccessMode AccessMode, desc="user/supervisor access type";
   DataBlock DataBlk,         desc="Data";
   int Len,                   desc="size in bytes of access";
   PrefetchBit Prefetch,      desc="Is this a prefetch request";
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index c856dd921..d9c3077a2 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -129,7 +129,7 @@ structure (CacheMemory, external = "yes") {
   void profileMiss(CacheMsg);
 
   void profileGenericRequest(GenericRequestType,
-                             AccessModeType,
+                             RubyAccessMode,
                              PrefetchBit);
 
   void setMRU(Address);
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.cc b/src/mem/ruby/profiler/AccessTraceForAddress.cc
index e7aaa2515..9cbf71163 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.cc
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.cc
@@ -59,7 +59,7 @@ AccessTraceForAddress::print(std::ostream& out) const
 
 void
 AccessTraceForAddress::update(CacheRequestType type,
-                              AccessModeType access_mode, NodeID cpu,
+                              RubyAccessMode access_mode, NodeID cpu,
                               bool sharing_miss)
 {
     m_touched_by.add(cpu);
@@ -74,7 +74,7 @@ AccessTraceForAddress::update(CacheRequestType type,
         //  ERROR_MSG("Trying to add invalid access to trace");
     }
 
-    if (access_mode == AccessModeType_UserMode) {
+    if (access_mode == RubyAccessMode_User) {
         m_user++;
     }
 
diff --git a/src/mem/ruby/profiler/AccessTraceForAddress.hh b/src/mem/ruby/profiler/AccessTraceForAddress.hh
index b950f2be2..9b6db2376 100644
--- a/src/mem/ruby/profiler/AccessTraceForAddress.hh
+++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh
@@ -31,7 +31,7 @@
 
 #include <iostream>
 
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -50,7 +50,7 @@ class AccessTraceForAddress
     ~AccessTraceForAddress();
 
     void setAddress(const Address& addr) { m_addr = addr; }
-    void update(CacheRequestType type, AccessModeType access_mode, NodeID cpu,
+    void update(CacheRequestType type, RubyAccessMode access_mode, NodeID cpu,
                 bool sharing_miss);
     int getTotal() const;
     int getSharing() const { return m_sharing; }
diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc
index 5c1b7352c..6ec0e20ba 100644
--- a/src/mem/ruby/profiler/AddressProfiler.cc
+++ b/src/mem/ruby/profiler/AddressProfiler.cc
@@ -257,7 +257,7 @@ AddressProfiler::profileGetX(const Address& datablock, const Address& PC,
     m_getx_sharing_histogram.add(num_indirections);
     bool indirection_miss = (num_indirections > 0);
 
-    addTraceSample(datablock, PC, CacheRequestType_ST, AccessModeType(0),
+    addTraceSample(datablock, PC, CacheRequestType_ST, RubyAccessMode(0),
                    requestor, indirection_miss);
 }
 
@@ -274,14 +274,14 @@ AddressProfiler::profileGetS(const Address& datablock, const Address& PC,
     m_gets_sharing_histogram.add(num_indirections);
     bool indirection_miss = (num_indirections > 0);
 
-    addTraceSample(datablock, PC, CacheRequestType_LD, AccessModeType(0),
+    addTraceSample(datablock, PC, CacheRequestType_LD, RubyAccessMode(0),
                    requestor, indirection_miss);
 }
 
 void
 AddressProfiler::addTraceSample(Address data_addr, Address pc_addr,
                                 CacheRequestType type,
-                                AccessModeType access_mode, NodeID id,
+                                RubyAccessMode access_mode, NodeID id,
                                 bool sharing_miss)
 {
     if (m_all_instructions) {
diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh
index 5422fe095..fe822c116 100644
--- a/src/mem/ruby/profiler/AddressProfiler.hh
+++ b/src/mem/ruby/profiler/AddressProfiler.hh
@@ -55,7 +55,7 @@ class AddressProfiler
     void clearStats();
 
     void addTraceSample(Address data_addr, Address pc_addr,
-                        CacheRequestType type, AccessModeType access_mode,
+                        CacheRequestType type, RubyAccessMode access_mode,
                         NodeID id, bool sharing_miss);
     void profileRetry(const Address& data_addr, AccessType type, int count);
     void profileGetX(const Address& datablock, const Address& PC,
diff --git a/src/mem/ruby/profiler/CacheProfiler.cc b/src/mem/ruby/profiler/CacheProfiler.cc
index a969b9074..fcad227fb 100644
--- a/src/mem/ruby/profiler/CacheProfiler.cc
+++ b/src/mem/ruby/profiler/CacheProfiler.cc
@@ -94,10 +94,10 @@ CacheProfiler::printStats(ostream& out) const
 
         out << endl;
 
-        for (int i = 0; i < AccessModeType_NUM; i++){
+        for (int i = 0; i < RubyAccessMode_NUM; i++){
             if (m_accessModeTypeHistogram[i] > 0) {
                 out << description << "_access_mode_type_"
-                    << (AccessModeType) i << ":   "
+                    << (RubyAccessMode) i << ":   "
                     << m_accessModeTypeHistogram[i] << "    "
                     << 100.0 * m_accessModeTypeHistogram[i] / requests
                     << "%" << endl;
@@ -122,14 +122,14 @@ CacheProfiler::clearStats()
     m_prefetches = 0;
     m_sw_prefetches = 0;
     m_hw_prefetches = 0;
-    for (int i = 0; i < AccessModeType_NUM; i++) {
+    for (int i = 0; i < RubyAccessMode_NUM; i++) {
         m_accessModeTypeHistogram[i] = 0;
     }
 }
 
 void
 CacheProfiler::addCacheStatSample(CacheRequestType requestType,
-                                  AccessModeType accessType, 
+                                  RubyAccessMode accessType,
                                   PrefetchBit pfBit)
 {
     m_cacheRequestType[requestType]++;
@@ -138,7 +138,7 @@ CacheProfiler::addCacheStatSample(CacheRequestType requestType,
 
 void
 CacheProfiler::addGenericStatSample(GenericRequestType requestType,
-                                    AccessModeType accessType, 
+                                    RubyAccessMode accessType,
                                     PrefetchBit pfBit)
 {
     m_genericRequestType[requestType]++;
@@ -146,7 +146,7 @@ CacheProfiler::addGenericStatSample(GenericRequestType requestType,
 }
 
 void
-CacheProfiler::addStatSample(AccessModeType accessType, 
+CacheProfiler::addStatSample(RubyAccessMode accessType,
                              PrefetchBit pfBit)
 {
     m_misses++;
diff --git a/src/mem/ruby/profiler/CacheProfiler.hh b/src/mem/ruby/profiler/CacheProfiler.hh
index 2e59c9d82..9a8fdefb4 100644
--- a/src/mem/ruby/profiler/CacheProfiler.hh
+++ b/src/mem/ruby/profiler/CacheProfiler.hh
@@ -33,7 +33,7 @@
 #include <string>
 #include <vector>
 
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/PrefetchBit.hh"
@@ -51,11 +51,11 @@ class CacheProfiler
     void clearStats();
 
     void addCacheStatSample(CacheRequestType requestType, 
-                            AccessModeType type,
+                            RubyAccessMode type,
                             PrefetchBit pfBit);
 
     void addGenericStatSample(GenericRequestType requestType, 
-                              AccessModeType type,
+                              RubyAccessMode type,
                               PrefetchBit pfBit);
 
     void print(std::ostream& out) const;
@@ -64,7 +64,7 @@ class CacheProfiler
     // Private copy constructor and assignment operator
     CacheProfiler(const CacheProfiler& obj);
     CacheProfiler& operator=(const CacheProfiler& obj);
-    void addStatSample(AccessModeType type, PrefetchBit pfBit);
+    void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
 
     std::string m_description;
     int64 m_misses;
@@ -72,7 +72,7 @@ class CacheProfiler
     int64 m_prefetches;
     int64 m_sw_prefetches;
     int64 m_hw_prefetches;
-    int64 m_accessModeTypeHistogram[AccessModeType_NUM];
+    int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
 
     std::vector<int> m_cacheRequestType;
     std::vector<int> m_genericRequestType;
diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh
index c0cee1d7d..a3eb8cd71 100644
--- a/src/mem/ruby/profiler/Profiler.hh
+++ b/src/mem/ruby/profiler/Profiler.hh
@@ -51,7 +51,7 @@
 #include <vector>
 
 #include "base/hashmap.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/AccessType.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericMachineType.hh"
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index b97e8cbbc..6d0e23bfe 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -32,7 +32,7 @@
 #include <ostream>
 
 #include "mem/packet.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/Message.hh"
 #include "mem/protocol/PrefetchBit.hh"
@@ -53,12 +53,6 @@ enum RubyRequestType {
   RubyRequestType_NUM
 };
 
-enum RubyAccessMode {
-  RubyAccessMode_User,
-  RubyAccessMode_Supervisor,
-  RubyAccessMode_Device
-};
-
 class RubyRequest
 {
   public:
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index b80c1c356..7fcb5431b 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -353,7 +353,7 @@ CacheMemory::profileMiss(const CacheMsg& msg)
 
 void
 CacheMemory::profileGenericRequest(GenericRequestType requestType,
-                                   AccessModeType accessType,
+                                   RubyAccessMode accessType,
                                    PrefetchBit pfBit)
 {
     m_profiler_ptr->addGenericStatSample(requestType, 
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 1f0ffd500..6e311edc3 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -110,7 +110,7 @@ class CacheMemory : public SimObject
     void profileMiss(const CacheMsg & msg);
 
     void profileGenericRequest(GenericRequestType requestType,
-                               AccessModeType accessType,
+                               RubyAccessMode accessType,
                                PrefetchBit pfBit);
 
     void getMemoryValue(const Address& addr, char* value,
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 800352eed..7f916957b 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -644,16 +644,16 @@ Sequencer::issueRequest(const RubyRequest& request)
         assert(0);
     }
 
-    AccessModeType amtype;
+    RubyAccessMode amtype;
     switch(request.access_mode){
       case RubyAccessMode_User:
-        amtype = AccessModeType_UserMode;
+        amtype = RubyAccessMode_User;
         break;
       case RubyAccessMode_Supervisor:
-        amtype = AccessModeType_SupervisorMode;
+        amtype = RubyAccessMode_Supervisor;
         break;
       case RubyAccessMode_Device:
-        amtype = AccessModeType_UserMode;
+        amtype = RubyAccessMode_User;
         break;
       default:
         assert(0);
@@ -686,7 +686,7 @@ Sequencer::issueRequest(const RubyRequest& request)
 #if 0
 bool
 Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
-                          AccessModeType access_mode,
+                          RubyAccessMode access_mode,
                           int size, DataBlock*& data_ptr)
 {
     CacheMemory *cache =
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 453a8cbae..7793af889 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -32,7 +32,7 @@
 #include <iostream>
 
 #include "base/hashmap.hh"
-#include "mem/protocol/AccessModeType.hh"
+#include "mem/protocol/RubyAccessMode.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/PrefetchBit.hh"
@@ -113,7 +113,7 @@ class Sequencer : public RubyPort, public Consumer
 
   private:
     bool tryCacheAccess(const Address& addr, CacheRequestType type,
-                        const Address& pc, AccessModeType access_mode,
+                        const Address& pc, RubyAccessMode access_mode,
                         int size, DataBlock*& data_ptr);
     void issueRequest(const RubyRequest& request);