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authorAndreas Hansson <andreas.hansson@arm.com>2012-03-02 09:21:48 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-03-02 09:21:48 -0500
commit32eae8094d8931f161784825ad013e9c6d995c17 (patch)
treeef3dc2b37cecd53d7bd1fcd5809b0ed251f30b3a /src
parentc0b9f324bf2780b344bef04a4ce7ee063e172e40 (diff)
downloadgem5-32eae8094d8931f161784825ad013e9c6d995c17.tar.xz
CPU: Check that the interrupt controller is created when needed
This patch adds a creation-time check to the CPU to ensure that the interrupt controller is created for the cases where it is needed, i.e. if the CPU is not being switched in later and not a checker CPU. The patch also adds the "createInterruptController" call to a number of the regression scripts.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/base.cc17
-rw-r--r--src/cpu/base.hh2
-rw-r--r--src/cpu/checker/cpu.cc2
-rw-r--r--src/cpu/inorder/cpu.cc6
-rw-r--r--src/cpu/o3/cpu.cc6
5 files changed, 26 insertions, 7 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 86edf62cf..0722f319d 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -118,7 +118,7 @@ CPUProgressEvent::description() const
return "CPU Progress";
}
-BaseCPU::BaseCPU(Params *p)
+BaseCPU::BaseCPU(Params *p, bool is_checker)
: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
_instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")),
@@ -219,10 +219,17 @@ BaseCPU::BaseCPU(Params *p)
schedule(event, p->function_trace_start);
}
}
- // Check if CPU model has interrupts connected. The CheckerCPU
- // cannot take interrupts directly for example.
- if (interrupts)
- interrupts->setCPU(this);
+
+ // The interrupts should always be present unless this CPU is
+ // switched in later or in case it is a checker CPU
+ if (!params()->defer_registration && !is_checker) {
+ if (interrupts) {
+ interrupts->setCPU(this);
+ } else {
+ fatal("CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+ }
if (FullSystem) {
profileEvent = NULL;
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 8728a6e07..74bb8dc12 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -302,7 +302,7 @@ class BaseCPU : public MemObject
typedef BaseCPUParams Params;
const Params *params() const
{ return reinterpret_cast<const Params *>(_params); }
- BaseCPU(Params *params);
+ BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU();
virtual void init();
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index fb381d24d..b21ceeb92 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -64,7 +64,7 @@ CheckerCPU::init()
}
CheckerCPU::CheckerCPU(Params *p)
- : BaseCPU(p), thread(NULL), tc(NULL)
+ : BaseCPU(p, true), thread(NULL), tc(NULL)
{
memReq = NULL;
curStaticInst = NULL;
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 84f5e3850..ac7a1b209 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -387,6 +387,12 @@ InOrderCPU::InOrderCPU(Params *params)
}
+ // InOrderCPU always requires an interrupt controller.
+ if (!params->defer_registration && !interrupts) {
+ fatal("InOrderCPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+
dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyReqInst->setSquashed();
dummyReqInst->resetInstCount();
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 5dd2c3f3c..bf2cc80e3 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -460,6 +460,12 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
this->threadContexts.push_back(tc);
}
+ // FullO3CPU always requires an interrupt controller.
+ if (!params->defer_registration && !interrupts) {
+ fatal("FullO3CPU %s has no interrupt controller.\n"
+ "Ensure createInterruptController() is called.\n", name());
+ }
+
for (ThreadID tid = 0; tid < this->numThreads; tid++)
this->thread[tid]->setFuncExeInst(0);