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authorAli Saidi <Ali.Saidi@ARM.com>2010-12-07 16:19:57 -0800
committerAli Saidi <Ali.Saidi@ARM.com>2010-12-07 16:19:57 -0800
commit42ba158479c3feed12335958684200de8b6d2ece (patch)
treee16873a83f3571fce483231c57839fcabaad75b0 /src
parent1cfe2c88204aed6310fa8be9a310350cb06f6026 (diff)
downloadgem5-42ba158479c3feed12335958684200de8b6d2ece.tar.xz
O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).
The store queue doesn't need to be ISA specific and architectures can frequently store more than an int registers worth of data. A 128 bits seems more common, but even 256 bits may be appropriate. Pretty much anything less than a cache line size is buildable.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/lsq_unit.hh4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 372e76b71..e9e3fea96 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -63,8 +63,6 @@ class DerivO3CPUParams;
*/
template <class Impl>
class LSQUnit {
- protected:
- typedef TheISA::IntReg IntReg;
public:
typedef typename Impl::O3CPU O3CPU;
typedef typename Impl::DynInstPtr DynInstPtr;
@@ -338,7 +336,7 @@ class LSQUnit {
/** The size of the store. */
int size;
/** The store data. */
- char data[sizeof(IntReg)];
+ char data[16];
/** Whether or not the store is split into two requests. */
bool isSplit;
/** Whether or not the store can writeback. */