diff options
author | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:09:28 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-09-06 16:09:28 -0700 |
commit | 4478487c372ac79fb98b85f3710ab3c101c82a00 (patch) | |
tree | dc25c45cb6c86aa99f1286c59468c125585a3ec4 /src | |
parent | 57da0594157058f9d741dd19a4f08830652789f3 (diff) | |
download | gem5-4478487c372ac79fb98b85f3710ab3c101c82a00.tar.xz |
X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.
--HG--
extra : convert_revision : ee0b5acde08d12c51a5282efb58d1ac72e0779af
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/x86/isa/decoder/two_byte_opcodes.isa | 2 | ||||
-rw-r--r-- | src/arch/x86/isa/includes.isa | 1 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/sse/__init__.py | 3 | ||||
-rw-r--r-- | src/arch/x86/isa/insts/sse/compare.py | 71 | ||||
-rw-r--r-- | src/arch/x86/isa/microops/regop.isa | 34 |
5 files changed, 102 insertions, 9 deletions
diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa index fc5729540..ae2318899 100644 --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa @@ -196,7 +196,7 @@ 0x3: movntpd_Mo_Vo(); 0x4: cvttpd2pi_Pq_Wo(); 0x5: cvtpd2pi_Pq_Wo(); - 0x6: ucomisd_Vq_Wq(); + 0x6: Inst::UCOMISD(Vq,Wq); 0x7: comisd_Vq_Wq(); } // repne (0xF2) diff --git a/src/arch/x86/isa/includes.isa b/src/arch/x86/isa/includes.isa index f9e1e971c..9629a54e3 100644 --- a/src/arch/x86/isa/includes.isa +++ b/src/arch/x86/isa/includes.isa @@ -143,6 +143,7 @@ output exec {{ #include <limits> #include <cmath> +#include "arch/x86/miscregs.hh" #include "base/bigint.hh" #include "cpu/base.hh" #include "cpu/exetrace.hh" diff --git a/src/arch/x86/isa/insts/sse/__init__.py b/src/arch/x86/isa/insts/sse/__init__.py index 976e2dd52..05c306885 100644 --- a/src/arch/x86/isa/insts/sse/__init__.py +++ b/src/arch/x86/isa/insts/sse/__init__.py @@ -57,7 +57,8 @@ categories = ["move", "convert", "add_and_subtract", "multiply_and_divide", - "logical"] + "logical", + "compare"] microcode = ''' # SSE instructions diff --git a/src/arch/x86/isa/insts/sse/compare.py b/src/arch/x86/isa/insts/sse/compare.py new file mode 100644 index 000000000..8721dffa7 --- /dev/null +++ b/src/arch/x86/isa/insts/sse/compare.py @@ -0,0 +1,71 @@ +# Copyright (c) 2007 The Hewlett-Packard Development Company +# All rights reserved. +# +# Redistribution and use of this software in source and binary forms, +# with or without modification, are permitted provided that the +# following conditions are met: +# +# The software must be used only for Non-Commercial Use which means any +# use which is NOT directed to receiving any direct monetary +# compensation for, or commercial advantage from such use. Illustrative +# examples of non-commercial use are academic research, personal study, +# teaching, education and corporate research & development. +# Illustrative examples of commercial use are distributing products for +# commercial advantage and providing services using the software for +# commercial advantage. +# +# If you wish to use this software or functionality therein that may be +# covered by patents for commercial use, please contact: +# Director of Intellectual Property Licensing +# Office of Strategy and Technology +# Hewlett-Packard Company +# 1501 Page Mill Road +# Palo Alto, California 94304 +# +# Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. Redistributions +# in binary form must reproduce the above copyright notice, this list of +# conditions and the following disclaimer in the documentation and/or +# other materials provided with the distribution. Neither the name of +# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. No right of +# sublicense is granted herewith. Derivatives of the software and +# output created using the software may be prepared, but only for +# Non-Commercial Uses. Derivatives of the software may be shared with +# others provided: (i) the others agree to abide by the list of +# conditions herein which includes the Non-Commercial Use restrictions; +# and (ii) such Derivatives of the software include the above copyright +# notice to acknowledge the contribution from this software where +# applicable, this list of conditions and the disclaimer below. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Gabe Black + +microcode = ''' +def macroop UCOMISD_R_R { + compfp xmml, xmmlm +}; + +def macroop UCOMISD_R_M { + ldfp ufp1, seg, sib, disp + compfp xmml, ufp1 +}; + +def macroop UCOMISD_R_P { + rdip t7 + ldfp ufp1, seg, riprel, disp + compfp xmml, ufp1 +}; +''' diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa index dca6d7377..ec6f49424 100644 --- a/src/arch/x86/isa/microops/regop.isa +++ b/src/arch/x86/isa/microops/regop.isa @@ -488,13 +488,6 @@ let {{ code = 'DestReg = merge(SrcReg1, op2, dataSize)' else_code = 'DestReg=DestReg;' - class Xorfp(RegOp): - code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' - - class Movfp(CondRegOp): - code = 'FpDestReg.uqw = FpSrcReg2.uqw;' - else_code = 'FpDestReg.uqw = FpDestReg.uqw;' - # Shift instructions class Sll(FlagRegOp): @@ -640,6 +633,33 @@ let {{ class Zext(RegOp): code = 'DestReg = bits(psrc1, imm8-1, 0);' + class Compfp(WrRegOp): + # This class sets the condition codes in rflags according to the + # rules for comparing floating point. + code = ''' + // ZF PF CF + // Unordered 1 1 1 + // Greater than 0 0 0 + // Less than 0 0 1 + // Equal 1 0 0 + // OF = SF = AF = 0 + ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | + ZFBit | PFBit | CFBit); + if (isnan(FpSrcReg1) || isnan(FpSrcReg2)) + ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); + else if(FpSrcReg1 < FpSrcReg2) + ccFlagBits = ccFlagBits | CFBit; + else if(FpSrcReg1 == FpSrcReg2) + ccFlagBits = ccFlagBits | ZFBit; + ''' + + class Xorfp(RegOp): + code = 'FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw;' + + class Movfp(CondRegOp): + code = 'FpDestReg.uqw = FpSrcReg2.uqw;' + else_code = 'FpDestReg.uqw = FpDestReg.uqw;' + # Conversion microops class ConvOp(RegOp): abstract = True |