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authorSascha Bischoff <sascha.bischoff@arm.com>2017-02-21 14:14:44 +0000
committerSascha Bischoff <sascha.bischoff@arm.com>2017-02-21 14:14:44 +0000
commit46b4c402779cd8fa37bde8de0069b80bfdaa8454 (patch)
tree25d9c3eb2e387d03d961f080024502839ce874e5 /src
parent767aed453420fcf6c1fa0611a122a8636bf71003 (diff)
downloadgem5-46b4c402779cd8fa37bde8de0069b80bfdaa8454.tar.xz
mem: Fix MSHR assert triggering for invalidated prefetches
This changeset updates an assert in src/mem/cache/mshr.cc which was erroneously catching invalidated prefetch requests. These requests can become invalidated if another component writes (an exclusive access) to this location during the time that the read request is in flight. The original assert made the assumption that these cases can only occur for reads generated by the CPU, and hence prefetcher-generated requests would sometimes trip the assert. Change-Id: If4f043273a688c2bab8f7a641192a2b583e7b20e Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/mem/cache/mshr.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index e3282f9b8..25f73d79a 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2012-2013, 2015-2017 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -465,7 +465,8 @@ MSHR::extractServiceableTargets(PacketPtr pkt)
// avoid memory consistency violations.
if (pkt->cmd == MemCmd::ReadRespWithInvalidate) {
auto it = targets.begin();
- assert(it->source == Target::FromCPU);
+ assert((it->source == Target::FromCPU) ||
+ (it->source == Target::FromPrefetcher));
ready_targets.push_back(*it);
it = targets.erase(it);
while (it != targets.end()) {