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authorAli Saidi <Ali.Saidi@ARM.com>2011-05-04 20:38:26 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-05-04 20:38:26 -0500
commit48f7fda706b854f053d66df5e14e0084df775910 (patch)
tree7a2c8ecf89e5c4530ada1453cfe756edaa8799be /src
parent632cf8dd80f29f85097aa90cd704ca01cc57ff39 (diff)
downloadgem5-48f7fda706b854f053d66df5e14e0084df775910.tar.xz
ARM: Add vfpv3 support to native trace.
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/nativetrace.cc18
-rw-r--r--src/arch/arm/nativetrace.hh12
2 files changed, 24 insertions, 6 deletions
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 2dd225e80..a8d01a0f2 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -54,7 +54,11 @@ namespace Trace {
static const char *regNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
- "cpsr"
+ "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
+ "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
+ "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
+ "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
+ "f31", "fpscr"
};
#endif
@@ -67,7 +71,7 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
memcpy(newState, oldState, sizeof(state[0]));
- uint32_t diffVector;
+ uint64_t diffVector;
parent->read(&diffVector, sizeof(diffVector));
diffVector = ArmISA::gtoh(diffVector);
@@ -82,7 +86,7 @@ Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
diffVector >>= 1;
}
- uint32_t values[changes];
+ uint64_t values[changes];
parent->read(values, sizeof(values));
int pos = 0;
for (int i = 0; i < STATE_NUMVALS; i++) {
@@ -114,6 +118,14 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
tc->readIntReg(INTREG_CONDCODES);
changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
+
+ for (int i = 0; i < NumFloatArchRegs; i += 2) {
+ newState[STATE_F0 + (i >> 1)] =
+ static_cast<uint64_t>(tc->readFloatRegBits(i + 1)) << 32 |
+ tc->readFloatRegBits(i);
+ }
+ newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
+ tc->readIntReg(INTREG_FPCONDCODES);
}
void
diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh
index 221d40e2f..d3f96f3ad 100644
--- a/src/arch/arm/nativetrace.hh
+++ b/src/arch/arm/nativetrace.hh
@@ -62,15 +62,21 @@ class ArmNativeTrace : public NativeTrace
STATE_R15,
STATE_PC = STATE_R15,
STATE_CPSR,
+ STATE_F0, STATE_F1, STATE_F2, STATE_F3, STATE_F4, STATE_F5, STATE_F6,
+ STATE_F7, STATE_F8, STATE_F9, STATE_F10, STATE_F11, STATE_F12,
+ STATE_F13, STATE_F14, STATE_F15, STATE_F16, STATE_F17, STATE_F18,
+ STATE_F19, STATE_F20, STATE_F21, STATE_F22, STATE_F23, STATE_F24,
+ STATE_F25, STATE_F26, STATE_F27, STATE_F28, STATE_F29, STATE_F30,
+ STATE_F31, STATE_FPSCR,
STATE_NUMVALS
};
protected:
struct ThreadState {
bool changed[STATE_NUMVALS];
- uint32_t state[2][STATE_NUMVALS];
- uint32_t *newState;
- uint32_t *oldState;
+ uint64_t state[2][STATE_NUMVALS];
+ uint64_t *newState;
+ uint64_t *oldState;
int current;
void update(NativeTrace *parent);
void update(ThreadContext *tc);