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| author | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-23 18:45:30 -0400 |
|---|---|---|
| committer | Lisa Hsu <hsul@eecs.umich.edu> | 2006-10-23 18:45:30 -0400 |
| commit | 4da3938ed99e3691cfb16c275eea659cbaaa6c30 (patch) | |
| tree | 96cd83b1ddfaad66f9e3e6baf0f8ec9fd4644393 /src | |
| parent | 0a2387f38c6887f688144a18e0d7ff50e80bd04c (diff) | |
| download | gem5-4da3938ed99e3691cfb16c275eea659cbaaa6c30.tar.xz | |
get rid of the "resume" step at the end of changeToTiming/Atomic because this will cause an assertion when you do the CPU switch. instead, push the responsibility of the resume upwards towards the user - documented in se.py and fs.py so it should be ok.
--HG--
extra : convert_revision : 7530cf140844e18cc26df80057f8760f29ec952b
Diffstat (limited to 'src')
| -rw-r--r-- | src/python/m5/__init__.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index 03e0508fb..d41fd5a61 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -150,7 +150,6 @@ def changeToAtomic(system): doDrain(system) print "Changing memory mode to atomic" system.changeTiming(cc_main.SimObject.Atomic) - resume(system) def changeToTiming(system): if not isinstance(system, objects.Root) and not isinstance(system, objects.System): @@ -159,7 +158,6 @@ def changeToTiming(system): doDrain(system) print "Changing memory mode to timing" system.changeTiming(cc_main.SimObject.Timing) - resume(system) def switchCpus(cpuList): print "switching cpus" @@ -190,7 +188,6 @@ def switchCpus(cpuList): cc_main.cleanupCountedDrain(drain_event) # Now all of the CPUs are ready to be switched out for old_cpu in old_cpus: - print "switching" old_cpu._ccObject.switchOut() index = 0 for new_cpu in new_cpus: |