summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-11-15 14:04:04 -0600
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-11-15 14:04:04 -0600
commit745df74fe0ee57444487c7a231ce02a96244e48d (patch)
treeb79414b5d16abf70679415067bde97ff8498a4a4 /src
parent4a1814bd524e7444f57dcd1ea24070fd7b375af3 (diff)
downloadgem5-745df74fe0ee57444487c7a231ce02a96244e48d.tar.xz
O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits. Code and associated comment was copied from execute() and initiateAcc() methods
Diffstat (limited to 'src')
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 6f7c23b2f..268746655 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -113,8 +113,17 @@ template <class Impl>
Fault
BaseO3DynInst<Impl>::completeAcc(PacketPtr pkt)
{
+ // @todo: Pretty convoluted way to avoid squashing from happening
+ // when using the TC during an instruction's execution
+ // (specifically for instructions that have side-effects that use
+ // the TC). Fix this.
+ bool in_syscall = this->thread->inSyscall;
+ this->thread->inSyscall = true;
+
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
+ this->thread->inSyscall = in_syscall;
+
return this->fault;
}