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authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:31:30 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:31:30 -0700
commit80d51650c8bce1503e5ce3877f3bfe21d3e57d45 (patch)
tree00d12d52753f73bc7d7f196b0797140eeb689ddd /src
parentfcd04f953ce56f85da52d916f5770924fedd0297 (diff)
downloadgem5-80d51650c8bce1503e5ce3877f3bfe21d3e57d45.tar.xz
O3 CPU: Remove alignment check from dynamic instruction read/write functions.
--HG-- extra : convert_revision : e5d415b4bf79353ef3c9f4dc5af09ab4102c55fb
Diffstat (limited to 'src')
-rw-r--r--src/cpu/base_dyn_inst.hh12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 362babeff..0f2a90bf6 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -847,12 +847,6 @@ BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->readCpuId(), threadNumber);
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- delete req;
- return TheISA::genAlignmentFault();
- }
-
fault = cpu->translateDataReadReq(req, thread);
if (req->isUncacheable())
@@ -909,12 +903,6 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
req->setThreadContext(thread->readCpuId(), threadNumber);
- if ((req->getVaddr() & (TheISA::VMPageSize - 1)) + req->getSize() >
- TheISA::VMPageSize) {
- delete req;
- return TheISA::genAlignmentFault();
- }
-
fault = cpu->translateDataWriteReq(req, thread);
if (req->isUncacheable())