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authorKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:37 -0400
committerKorey Sewell <ksewell@umich.edu>2011-06-19 21:43:37 -0400
commit89d0f95bf02489ab8fed382af2f104c4788b8db6 (patch)
treee0ae62c3c28b5c902bcf5320b81393486335c5d7 /src
parent479195d4cf5d52138a1dc3cf1e5ffe588c6e924f (diff)
downloadgem5-89d0f95bf02489ab8fed382af2f104c4788b8db6.tar.xz
inorder: branch predictor update
only update BTB on a taken branch and update branch predictor w/pcstate from instruction --- only pay attention to branch predictor updates if the the inst. is in fact a branch
Diffstat (limited to 'src')
-rw-r--r--src/cpu/inorder/cpu.cc3
-rw-r--r--src/cpu/inorder/pipeline_stage.cc2
-rw-r--r--src/cpu/inorder/resources/bpred_unit.cc6
-rw-r--r--src/cpu/inorder/resources/branch_predictor.cc8
-rw-r--r--src/cpu/inorder/resources/fetch_seq_unit.cc6
5 files changed, 17 insertions, 8 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 03c44ea86..75e9e06d9 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -506,6 +506,9 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
}
+ if (inst->isControl())
+ W.needs(BPred, BranchPredictor::UpdatePredictor);
+
// Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index e739fd2e6..263720700 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -420,7 +420,7 @@ PipelineStage::squash(InstSeqNum squash_seq_num, ThreadID tid)
while (cur_it != end_it) {
if ((*cur_it)->seqNum <= squash_seq_num) {
DPRINTF(InOrderStage, "[tid:%i]: Cannot remove skidBuffer "
- "instructions (starting w/[sn:%i]) before delay slot "
+ "instructions (starting w/[sn:%i]) before "
"[sn:%i]. %i insts left.\n", tid,
(*cur_it)->seqNum, squash_seq_num,
skidBuffer[tid].size());
diff --git a/src/cpu/inorder/resources/bpred_unit.cc b/src/cpu/inorder/resources/bpred_unit.cc
index 25b8b165a..778366532 100644
--- a/src/cpu/inorder/resources/bpred_unit.cc
+++ b/src/cpu/inorder/resources/bpred_unit.cc
@@ -250,7 +250,7 @@ BPredUnit::predict(DynInstPtr &inst, TheISA::PCState &predPC, ThreadID tid)
tid, asid, inst->pcState(), target);
} else {
DPRINTF(InOrderBPred, "[tid:%i]: BTB doesn't have a "
- "valid entry.\n",tid);
+ "valid entry, predicting false.\n",tid);
pred_taken = false;
}
}
@@ -369,7 +369,9 @@ BPredUnit::squash(const InstSeqNum &squashed_sn,
BPUpdate((*hist_it).pc.instAddr(), actually_taken,
pred_hist.front().bpHistory);
- BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
+ // only update BTB on branch taken right???
+ if (actually_taken)
+ BTB.update((*hist_it).pc.instAddr(), corrTarget, asid);
DPRINTF(InOrderBPred, "[tid:%i]: Removing history for [sn:%i] "
"PC %s.\n", tid, (*hist_it).seqNum, (*hist_it).pc);
diff --git a/src/cpu/inorder/resources/branch_predictor.cc b/src/cpu/inorder/resources/branch_predictor.cc
index 3132770d4..3dea92cfb 100644
--- a/src/cpu/inorder/resources/branch_predictor.cc
+++ b/src/cpu/inorder/resources/branch_predictor.cc
@@ -152,10 +152,14 @@ BranchPredictor::squash(DynInstPtr inst, int squash_stage,
DPRINTF(InOrderBPred, "[tid:%i][sn:%i] Squashing...\n", tid,
bpred_squash_num);
+ // update due to branch resolution
if (squash_stage >= ThePipeline::BackEndStartStage) {
- bool taken = inst->predTaken();
- branchPred.squash(bpred_squash_num, inst->readPredTarg(), taken, tid);
+ branchPred.squash(bpred_squash_num,
+ inst->pcState(),
+ inst->pcState().branching(),
+ tid);
} else {
+ // update due to predicted taken branch
branchPred.squash(bpred_squash_num, tid);
}
}
diff --git a/src/cpu/inorder/resources/fetch_seq_unit.cc b/src/cpu/inorder/resources/fetch_seq_unit.cc
index 072ecb76f..8a55822a6 100644
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc
@@ -79,13 +79,13 @@ FetchSeqUnit::execute(int slot_num)
ThreadID tid = inst->readTid();
int stage_num = fs_req->getStageNum();
- DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
- pc[tid]);
-
switch (fs_req->cmd)
{
case AssignNextPC:
{
+ DPRINTF(InOrderFetchSeq, "[tid:%i]: Current PC is %s\n", tid,
+ pc[tid]);
+
if (pcValid[tid]) {
inst->pcState(pc[tid]);
inst->setMemAddr(pc[tid].instAddr());