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authorGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:30 -0700
committerGabe Black <gblack@eecs.umich.edu>2010-08-13 06:16:30 -0700
commit961aafc044b934ac0e5d1ffe51fc5f33813b052b (patch)
treef03913ff8fd0d917b033935fcfb5d5c72de01f2b /src
parentaa8c6e9c959eab4d516bc07593bea20ade9ad80c (diff)
parent73d9a51835f7f9b725b4bec851dac9d6482438e7 (diff)
downloadgem5-961aafc044b934ac0e5d1ffe51fc5f33813b052b.tar.xz
Merge with head.
Diffstat (limited to 'src')
-rw-r--r--src/cpu/simple/timing.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1670cb066..b04288ca6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -891,6 +891,8 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
// received a response from the dcache: complete the load or store
// instruction
assert(!pkt->isError());
+ assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
+ pkt->req->getFlags().isSet(Request::NO_ACCESS));
numCycles += tickToCycles(curTick - previousTick);
previousTick = curTick;
@@ -920,7 +922,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
}
}
- assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
_status = Running;
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);