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authorGabe Black <gblack@eecs.umich.edu>2008-10-12 22:16:53 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-12 22:16:53 -0700
commit961b40cdb537382f6463479e3707e7d04a223f38 (patch)
treeb59d681c1609907efa15eedecd9609256329c7de /src
parent989fa4fc0fa95906f2986deec99cfb8e6e49cc1a (diff)
downloadgem5-961b40cdb537382f6463479e3707e7d04a223f38.tar.xz
X86: Implement an wrdh microop which loads bases/offsets from 16 byte descriptors.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/isa/microops/regop.isa28
1 files changed, 28 insertions, 0 deletions
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index ba996060c..d7d1e3063 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -236,6 +236,15 @@ output header {{
SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck,
SegSSCheck, SegIretCheck, SegIntCSCheck
};
+
+ enum LongModeDescriptorType {
+ LDT64 = 2,
+ AvailableTSS64 = 9,
+ BusyTSS64 = 0xb,
+ CallGate64 = 0xc,
+ IntGate64 = 0xe,
+ TrapGate64 = 0xf
+ };
}};
output decoder {{
@@ -1098,7 +1107,26 @@ let {{
class Wrdh(RegOp):
code = '''
+ SegDescriptor desc = SrcReg1;
+ uint64_t target = bits(SrcReg2, 31, 0) << 32;
+ switch(desc.type) {
+ case LDT64:
+ case AvailableTSS64:
+ case BusyTSS64:
+ replaceBits(target, 23, 0, desc.baseLow);
+ replaceBits(target, 31, 24, desc.baseHigh);
+ break;
+ case CallGate64:
+ case IntGate64:
+ case TrapGate64:
+ replaceBits(target, 15, 0, bits(desc, 15, 0));
+ replaceBits(target, 31, 16, bits(desc, 63, 48));
+ break;
+ default:
+ panic("Wrdh used with wrong descriptor type!\\n");
+ }
+ DestReg = target;
'''
class Wrtsc(WrRegOp):