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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-02-29 19:13:13 -0600 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-02-29 19:13:13 -0600 |
| commit | c0d19391d423d16c5dc587c4946e8395b9c0db91 (patch) | |
| tree | 0f232ea2582d733467413ed590d3ec53c53f22d2 /src | |
| parent | aa674268e97810c50110d0418e13d6ec96217689 (diff) | |
| download | gem5-c0d19391d423d16c5dc587c4946e8395b9c0db91.tar.xz | |
arm: Squash after returning from exceptions in v7
Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/arm/isa/insts/data.isa | 6 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/macromem.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 3 |
3 files changed, 8 insertions, 5 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 881676496..df5a8b51e 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -273,10 +273,12 @@ let {{ ''' buildImmDataInst(mnem + 's', code, flagType, suffix = "ImmPclr", buildCc = False, - instFlags = ["IsSerializeAfter","IsNonSpeculative"]) + instFlags = ["IsSerializeAfter","IsNonSpeculative", + "IsSquashAfter"]) buildRegDataInst(mnem + 's', code, flagType, suffix = "RegPclr", buildCc = False, - instFlags = ["IsSerializeAfter","IsNonSpeculative"]) + instFlags = ["IsSerializeAfter","IsNonSpeculative", + "IsSquashAfter"]) buildDataInst("and", "Dest = resTemp = Op1 & secondOp;") buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;") diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index 8c1b26808..cc7366e2b 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -124,7 +124,7 @@ let {{ 'EA = URb + (up ? imm : -imm);', 'predicate_test': condPredicateTest}, ['IsMicroop','IsNonSpeculative', - 'IsSerializeAfter']) + 'IsSerializeAfter', 'IsSquashAfter']) microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);" microStrUopIop = InstObjParams('str_uop', 'MicroStrUop', @@ -668,7 +668,7 @@ let {{ {'code': microRetUopCode % 'URb', 'predicate_test': predicateTest}, ['IsMicroop', 'IsNonSpeculative', - 'IsSerializeAfter']) + 'IsSerializeAfter', 'IsSquashAfter']) setPCCPSRDecl = ''' CPSR cpsrOrCondCodes = URc; diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index c8b1de1d8..77c22e6ca 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -130,7 +130,8 @@ let {{ eretIop = InstObjParams("eret", "Eret", "PredOp", { "code": eretCode, "predicate_test": predicateTest }, - ["IsNonSpeculative", "IsSerializeAfter"]) + ["IsNonSpeculative", "IsSerializeAfter", + "IsSquashAfter"]) header_output += BasicDeclare.subst(eretIop) decoder_output += BasicConstructor.subst(eretIop) exec_output += PredOpExecute.subst(eretIop) |