summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-04-13 12:05:34 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-04-19 11:59:16 +0000
commitc21a2a54ca366c2e699571b1dddd083a77601831 (patch)
tree7048c09c4f2c7f75114db8b65a0ca4264ca5b084 /src
parent291c2798103999b66f9ad5b9a885a67f3ef2160e (diff)
downloadgem5-c21a2a54ca366c2e699571b1dddd083a77601831.tar.xz
arch-arm: Fix Unknown Instruction disassemble
Do not print the entire ExtMachInst when disassembling an Unknown Instruction. Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10062 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/arm/insts/misc.cc2
-rw-r--r--src/arch/arm/insts/misc64.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index d4a2ba2d2..ef78c236e 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -324,5 +324,5 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
std::string
UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return csprintf("%-10s (inst %#08x)", "unknown", machInst);
+ return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
}
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index edc916dbb..5bdf6cb94 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -78,7 +78,7 @@ RegRegRegImmOp64::generateDisassembly(
std::string
UnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
- return csprintf("%-10s (inst %#08x)", "unknown", machInst);
+ return csprintf("%-10s (inst %#08x)", "unknown", machInst & mask(32));
}
std::string