Rename cache files for brevity and consistency with rest of tree.

--HG--
rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62

27 files changed, 23 insertions, 27 deletions

diff --git a/src/mem/cache/SConscript b/src/mem/cache/SConscript
index d5899b623..3b8bdb0c8 100644
--- a/src/mem/cache/SConscript
+++ b/src/mem/cache/SConscript
@@ -32,10 +32,12 @@ Import('*')
 
 SimObject('BaseCache.py')
 
-Source('base_cache.cc')
+Source('base.cc')
 Source('cache.cc')
-Source('cache_blk.cc')
-Source('cache_builder.cc')
+Source('blk.cc')
+Source('builder.cc')
+Source('mshr.cc')
+Source('mshr_queue.cc')
 
 TraceFlag('Cache')
 TraceFlag('CachePort')
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base.cc
index 9fa9e2d29..9fa9e2d29 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base.cc
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base.hh
index 604474524..604474524 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base.hh
diff --git a/src/mem/cache/cache_blk.cc b/src/mem/cache/blk.cc
index d4a2eaee8..d4a2eaee8 100644
--- a/src/mem/cache/cache_blk.cc
+++ b/src/mem/cache/blk.cc
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/blk.hh
index bafb46a89..bafb46a89 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/blk.hh
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/builder.cc
index d67a9c9a4..d67a9c9a4 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/builder.cc
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/mshr.cc
index d711ca537..d711ca537 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/mshr.cc
diff --git a/src/mem/cache/miss/mshr.hh b/src/mem/cache/mshr.hh
index fdb0485cb..fdb0485cb 100644
--- a/src/mem/cache/miss/mshr.hh
+++ b/src/mem/cache/mshr.hh
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/mshr_queue.cc
index 71da7e4c1..71da7e4c1 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/mshr_queue.cc
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/mshr_queue.hh
index e04745087..e04745087 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/mshr_queue.hh
diff --git a/src/mem/cache/prefetch/SConscript b/src/mem/cache/prefetch/SConscript
index 8a7f1232c..7314b5ccf 100644
--- a/src/mem/cache/prefetch/SConscript
+++ b/src/mem/cache/prefetch/SConscript
@@ -30,8 +30,8 @@
 
 Import('*')
 
-Source('base_prefetcher.cc')
-Source('ghb_prefetcher.cc')
-Source('stride_prefetcher.cc')
-Source('tagged_prefetcher.cc')
+Source('base.cc')
+Source('ghb.cc')
+Source('stride.cc')
+Source('tagged.cc')
 
diff --git a/src/mem/cache/prefetch/base_prefetcher.cc b/src/mem/cache/prefetch/base.cc
index 1af900849..1af900849 100644
--- a/src/mem/cache/prefetch/base_prefetcher.cc
+++ b/src/mem/cache/prefetch/base.cc
diff --git a/src/mem/cache/prefetch/base_prefetcher.hh b/src/mem/cache/prefetch/base.hh
index 1515d8a93..1515d8a93 100644
--- a/src/mem/cache/prefetch/base_prefetcher.hh
+++ b/src/mem/cache/prefetch/base.hh
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.cc b/src/mem/cache/prefetch/ghb.cc
index d7d819a2d..d7d819a2d 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.cc
+++ b/src/mem/cache/prefetch/ghb.cc
diff --git a/src/mem/cache/prefetch/ghb_prefetcher.hh b/src/mem/cache/prefetch/ghb.hh
index c44e9c456..c44e9c456 100644
--- a/src/mem/cache/prefetch/ghb_prefetcher.hh
+++ b/src/mem/cache/prefetch/ghb.hh
diff --git a/src/mem/cache/prefetch/stride_prefetcher.cc b/src/mem/cache/prefetch/stride.cc
index 8d957182a..8d957182a 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.cc
+++ b/src/mem/cache/prefetch/stride.cc
diff --git a/src/mem/cache/prefetch/stride_prefetcher.hh b/src/mem/cache/prefetch/stride.hh
index 4d5ac2f0d..4d5ac2f0d 100644
--- a/src/mem/cache/prefetch/stride_prefetcher.hh
+++ b/src/mem/cache/prefetch/stride.hh
diff --git a/src/mem/cache/prefetch/tagged_prefetcher.cc b/src/mem/cache/prefetch/tagged.cc
index b25cb5054..b25cb5054 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher.cc
+++ b/src/mem/cache/prefetch/tagged.cc
diff --git a/src/mem/cache/prefetch/tagged_prefetcher.hh b/src/mem/cache/prefetch/tagged.hh
index f3094445f..f3094445f 100644
--- a/src/mem/cache/prefetch/tagged_prefetcher.hh
+++ b/src/mem/cache/prefetch/tagged.hh
diff --git a/src/mem/cache/tags/Repl.py b/src/mem/cache/tags/Repl.py
deleted file mode 100644
index b76aa1d6e..000000000
--- a/src/mem/cache/tags/Repl.py
+++ /dev/null
@@ -1,11 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class Repl(SimObject):
-    type = 'Repl'
-    abstract = True
-
-class GenRepl(Repl):
-    type = 'GenRepl'
-    fresh_res = Param.Int("Fresh pool residency time")
-    num_pools = Param.Int("Number of priority pools")
-    pool_res = Param.Int("Pool residency time")
diff --git a/src/mem/cache/tags/SConscript b/src/mem/cache/tags/SConscript
index 18ed8408b..9153d97e7 100644
--- a/src/mem/cache/tags/SConscript
+++ b/src/mem/cache/tags/SConscript
@@ -30,7 +30,7 @@
 
 Import('*')
 
-Source('base_tags.cc')
+Source('base.cc')
 Source('fa_lru.cc')
 Source('iic.cc')
 Source('lru.cc')
@@ -38,8 +38,8 @@ Source('split.cc')
 Source('split_lifo.cc')
 Source('split_lru.cc')
 
-SimObject('Repl.py')
-Source('repl/gen.cc')
+SimObject('iic_repl/Repl.py')
+Source('iic_repl/gen.cc')
 
 TraceFlag('IIC')
 TraceFlag('IICMore')
diff --git a/src/mem/cache/tags/base_tags.cc b/src/mem/cache/tags/base.cc
index 153737300..153737300 100644
--- a/src/mem/cache/tags/base_tags.cc
+++ b/src/mem/cache/tags/base.cc
diff --git a/src/mem/cache/tags/base_tags.hh b/src/mem/cache/tags/base.hh
index b7b0c7ef0..b7b0c7ef0 100644
--- a/src/mem/cache/tags/base_tags.hh
+++ b/src/mem/cache/tags/base.hh
diff --git a/src/mem/cache/miss/SConscript b/src/mem/cache/tags/iic_repl/Repl.py
index 376d670cd..4c333e897 100644
--- a/src/mem/cache/miss/SConscript
+++ b/src/mem/cache/tags/iic_repl/Repl.py
@@ -1,6 +1,4 @@
-# -*- mode:python -*-
-
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -28,7 +26,14 @@
 #
 # Authors: Nathan Binkert
 
-Import('*')
+from m5.SimObject import SimObject
+from m5.params import *
+class Repl(SimObject):
+    type = 'Repl'
+    abstract = True
 
-Source('mshr.cc')
-Source('mshr_queue.cc')
+class GenRepl(Repl):
+    type = 'GenRepl'
+    fresh_res = Param.Int("Fresh pool residency time")
+    num_pools = Param.Int("Number of priority pools")
+    pool_res = Param.Int("Pool residency time")
diff --git a/src/mem/cache/tags/repl/gen.cc b/src/mem/cache/tags/iic_repl/gen.cc
index bc4e6b86a..bc4e6b86a 100644
--- a/src/mem/cache/tags/repl/gen.cc
+++ b/src/mem/cache/tags/iic_repl/gen.cc
diff --git a/src/mem/cache/tags/repl/gen.hh b/src/mem/cache/tags/iic_repl/gen.hh
index 09a8d5995..09a8d5995 100644
--- a/src/mem/cache/tags/repl/gen.hh
+++ b/src/mem/cache/tags/iic_repl/gen.hh
diff --git a/src/mem/cache/tags/repl/repl.hh b/src/mem/cache/tags/iic_repl/repl.hh
index cdb5ae4b8..cdb5ae4b8 100644
--- a/src/mem/cache/tags/repl/repl.hh
+++ b/src/mem/cache/tags/iic_repl/repl.hh