More Changes, working towards cache.cc compiling. Headers cleaned up.

src/mem/cache/cache_blk.hh:
    Remove XC

--HG--
extra : convert_revision : aa2c43e4412ebb93165e12f693d5126983cfd0dc

11 files changed, 124 insertions, 114 deletions

diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 78e87479b..587faaf51 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -138,7 +138,7 @@ class Cache : public BaseCache
     };
 
     /** Instantiates a basic cache object. */
-    Cache(const std::string &_name, HierParams *hier_params, Params &params);
+    Cache(const std::string &_name, Params &params);
 
     void regStats();
 
@@ -147,7 +147,7 @@ class Cache : public BaseCache
      * @param req The request to perform.
      * @return The result of the access.
      */
-    MemAccessResult access(Packet * &pkt);
+    bool access(Packet * &pkt);
 
     /**
      * Selects a request to send on the bus.
@@ -233,7 +233,8 @@ class Cache : public BaseCache
      */
     void respond(Packet * &pkt, Tick time)
     {
-        si->respond(pkt,time);
+        //si->respond(pkt,time);
+        cpuSidePort->sendAtomic(pkt);
     }
 
     /**
diff --git a/src/mem/cache/cache_blk.hh b/src/mem/cache/cache_blk.hh
index 02fdd7a51..67e65d25b 100644
--- a/src/mem/cache/cache_blk.hh
+++ b/src/mem/cache/cache_blk.hh
@@ -97,7 +97,7 @@ class CacheBlk
     int refCount;
 
     CacheBlk()
-        : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0), xc(0),
+        : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0),
           set(-1), refCount(0)
     {}
 
@@ -114,7 +114,6 @@ class CacheBlk
         size = rhs.size;
         status = rhs.status;
         whenReady = rhs.whenReady;
-        xc = rhs.xc;
         set = rhs.set;
         refCount = rhs.refCount;
         return *this;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 3dc95af68..699d874de 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -51,14 +51,6 @@
 #include "mem/cache/miss/mshr.hh"
 #include "mem/cache/prefetch/prefetcher.hh"
 
-#include "mem/bus/bus.hh"
-
-#include "mem/bus/slave_interface.hh"
-#include "mem/memory_interface.hh"
-#include "mem/bus/master_interface.hh"
-
-#include "mem/mem_debug.hh"
-
 #include "sim/sim_events.hh" // for SimExitEvent
 
 using namespace std;
@@ -66,7 +58,7 @@ using namespace std;
 template<class TagStore, class Buffering, class Coherence>
 bool
 Cache<TagStore,Buffering,Coherence>::
-doTimingAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
+doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 {
     if (isCpuSide)
     {
@@ -74,17 +66,18 @@ doTimingAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
     }
     else
     {
-        if (pkt->isRespnse())
+        if (pkt->isResponse())
             handleResponse(pkt);
         else
             snoop(pkt);
     }
+    return true; //Deal with blocking....
 }
 
 template<class TagStore, class Buffering, class Coherence>
 Tick
 Cache<TagStore,Buffering,Coherence>::
-doAtomicAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
+doAtomicAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 {
     if (isCpuSide)
     {
@@ -92,7 +85,7 @@ doAtomicAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
     }
     else
     {
-        if (pkt->isRespnse())
+        if (pkt->isResponse())
             handleResponse(pkt);
         else
             snoopProbe(pkt, true);
@@ -102,7 +95,7 @@ doAtomicAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
 template<class TagStore, class Buffering, class Coherence>
 void
 Cache<TagStore,Buffering,Coherence>::
-doFunctionalAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
+doFunctionalAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
 {
     if (isCpuSide)
     {
@@ -110,7 +103,7 @@ doFunctionalAccess(Packet *pkt, MemoryPort *memoryPort, bool isCpuSide)
     }
     else
     {
-        if (pkt->isRespnse())
+        if (pkt->isResponse())
             handleResponse(pkt);
         else
             snoopProbe(pkt, false);
@@ -128,9 +121,9 @@ recvStatusChange(Port::Status status, bool isCpuSide)
 
 template<class TagStore, class Buffering, class Coherence>
 Cache<TagStore,Buffering,Coherence>::
-Cache(const std::string &_name, HierParams *hier_params,
+Cache(const std::string &_name,
       Cache<TagStore,Buffering,Coherence>::Params &params)
-    : BaseCache(_name, hier_params, params.baseParams),
+    : BaseCache(_name, params.baseParams),
       prefetchAccess(params.prefetchAccess),
       tags(params.tags), missQueue(params.missQueue),
       coherence(params.coherence), prefetcher(params.prefetcher),
@@ -148,7 +141,7 @@ Cache(const std::string &_name, HierParams *hier_params,
     prefetcher->setTags(tags);
     prefetcher->setBuffer(missQueue);
     invalidatePkt = new Packet;
-    invalidatePkt->cmd = Invalidate;
+    invalidatePkt->cmd = Packet::InvalidateReq;
 }
 
 template<class TagStore, class Buffering, class Coherence>
@@ -163,12 +156,13 @@ Cache<TagStore,Buffering,Coherence>::regStats()
 }
 
 template<class TagStore, class Buffering, class Coherence>
-MemAccessResult
-Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
+bool
+Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
 {
-    MemDebug::cacheAccess(pkt);
+//@todo Add back in MemDebug Calls
+//    MemDebug::cacheAccess(pkt);
     BlkType *blk = NULL;
-    PacketList* writebacks;
+    PacketList writebacks;
     int size = blkSize;
     int lat = hitLatency;
     if (prefetchAccess) {
@@ -176,18 +170,19 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
         prefetcher->handleMiss(pkt, curTick);
     }
     if (!pkt->req->isUncacheable()) {
-        if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
-            && !pkt->cmd.isWrite()) {
+        if (pkt->isInvalidate() && !pkt->isRead()
+            && !pkt->isWrite()) {
             //Upgrade or Invalidate
             //Look into what happens if two slave caches on bus
-            DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmd.toString(),
-                    pkt->req->asid, pkt->paddr & (((ULL(1))<<48)-1),
-                    pkt->paddr & ~((Addr)blkSize - 1));
+            DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
+                    pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1),
+                    pkt->addr & ~((Addr)blkSize - 1));
 
             //@todo Should this return latency have the hit latency in it?
 //	    respond(pkt,curTick+lat);
-            pkt->flags |= SATISFIED;
-            return MA_HIT;
+            (int)pkt->coherence |= SATISFIED;
+//            return MA_HIT; //@todo, return values
+            return true;
         }
         blk = tags->handleAccess(pkt, lat, writebacks);
     } else {
@@ -198,10 +193,10 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
     /** @todo make the fast write alloc (wh64) work with coherence. */
     /** @todo Do we want to do fast writes for writebacks as well? */
     if (!blk && pkt->size >= blkSize && coherence->allowFastWrites() &&
-        (pkt->cmd == Write || pkt->cmd == WriteInvalidate) ) {
+        (pkt->cmd == Packet::WriteReq || pkt->cmd == Packet::WriteInvalidateReq) ) {
         // not outstanding misses, can do this
-        MSHR* outstanding_miss = missQueue->findMSHR(pkt->paddr, pkt->req->asid);
-        if (pkt->cmd ==WriteInvalidate || !outstanding_miss) {
+        MSHR* outstanding_miss = missQueue->findMSHR(pkt->addr, pkt->req->asid);
+        if (pkt->cmd == Packet::WriteInvalidateReq || !outstanding_miss) {
             if (outstanding_miss) {
                 warn("WriteInv doing a fastallocate"
                      "with an outstanding miss to the same address\n");
@@ -215,16 +210,17 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
         missQueue->doWriteback(writebacks.front());
         writebacks.pop_front();
     }
-    DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmd.toString(),
-            pkt->req->asid, pkt->paddr & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
-            pkt->paddr & ~((Addr)blkSize - 1), pkt->pc);
+    DPRINTF(Cache, "%s %d %x %s blk_addr: %x pc %x\n", pkt->cmdString(),
+            pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
+            pkt->addr & ~((Addr)blkSize - 1), pkt->req->pc);
     if (blk) {
         // Hit
         hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
         // clear dirty bit if write through
-        if (!pkt->cmd.isNoResponse())
+        if (pkt->needsResponse())
             respond(pkt, curTick+lat);
-        return MA_HIT;
+//	return MA_HIT;
+        return true;
     }
 
     // Miss
@@ -234,11 +230,12 @@ Cache<TagStore,Buffering,Coherence>::access(Packet &pkt)
         if (missCount) {
             --missCount;
             if (missCount == 0)
-                new SimExitEvent("A cache reached the maximum miss count");
+                new SimLoopExitEvent("A cache reached the maximum miss count");
         }
     }
     missQueue->handleMiss(pkt, size, curTick + hitLatency);
-    return MA_CACHE_MISS;
+//    return MA_CACHE_MISS;
+    return true;
 }
 
 
@@ -249,7 +246,7 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
     Packet * pkt = missQueue->getPacket();
     if (pkt) {
         if (!pkt->req->isUncacheable()) {
-            if (pkt->cmd == Hard_Prefetch) misses[Hard_Prefetch][pkt->req->getThreadNum()]++;
+            if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
             BlkType *blk = tags->findBlock(pkt);
             Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
                                               (blk)? blk->status : 0);
@@ -257,19 +254,19 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
         }
     }
 
-    assert(!doMasterPktuest() || missQueue->havePending());
+    assert(!doMasterRequest() || missQueue->havePending());
     assert(!pkt || pkt->time <= curTick);
     return pkt;
 }
 
 template<class TagStore, class Buffering, class Coherence>
 void
-Cache<TagStore,Buffering,Coherence>::sendResult(MemPktPtr &pkt, bool success)
+Cache<TagStore,Buffering,Coherence>::sendResult(PacketPtr &pkt, bool success)
 {
     if (success) {
         missQueue->markInService(pkt);
           //Temp Hack for UPGRADES
-          if (pkt->cmd == Upgrade) {
+          if (pkt->cmd == Packet::UpgradeReq) {
               handleResponse(pkt);
           }
     } else if (pkt && !pkt->req->isUncacheable()) {
@@ -283,14 +280,14 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
 {
     BlkType *blk = NULL;
     if (pkt->senderState) {
-        MemDebug::cacheResponse(pkt);
-        DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->paddr,
-                pkt->paddr & (((ULL(1))<<48)-1));
+//	MemDebug::cacheResponse(pkt);
+        DPRINTF(Cache, "Handling reponse to %x, blk addr: %x\n",pkt->addr,
+                pkt->addr & (((ULL(1))<<48)-1));
 
         if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
             blk = tags->findBlock(pkt);
             CacheBlk::State old_state = (blk) ? blk->status : 0;
-            MemPktList writebacks;
+            PacketList writebacks;
             blk = tags->handleFill(blk, pkt->senderState,
                                    coherence->getNewState(pkt,old_state),
                                    writebacks);
@@ -309,11 +306,11 @@ Cache<TagStore,Buffering,Coherence>::pseudoFill(Addr addr, int asid)
     // Need to temporarily move this blk into MSHRs
     MSHR *mshr = missQueue->allocateTargetList(addr, asid);
     int lat;
-    PacketList* dummy;
+    PacketList dummy;
     // Read the data into the mshr
     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
     assert(dummy.empty());
-    assert(mshr->pkt->isSatisfied());
+    assert((int)mshr->pkt->coherence & SATISFIED);
     // can overload order since it isn't used on non pending blocks
     mshr->order = blk->status;
     // temporarily remove the block from the cache.
@@ -325,17 +322,17 @@ void
 Cache<TagStore,Buffering,Coherence>::pseudoFill(MSHR *mshr)
 {
     // Need to temporarily move this blk into MSHRs
-    assert(mshr->pkt->cmd == Read);
+    assert(mshr->pkt->cmd == Packet::ReadReq);
     int lat;
-    PacketList* dummy;
+    PacketList dummy;
     // Read the data into the mshr
     BlkType *blk = tags->handleAccess(mshr->pkt, lat, dummy, false);
     assert(dummy.empty());
-    assert(mshr->pkt->isSatisfied());
+    assert((int)mshr->pkt->coherence & SATISFIED);
     // can overload order since it isn't used on non pending blocks
     mshr->order = blk->status;
     // temporarily remove the block from the cache.
-    tags->invalidateBlk(mshr->pkt->paddr, mshr->pkt->req->asid);
+    tags->invalidateBlk(mshr->pkt->addr, mshr->pkt->req->asid);
 }
 
 
@@ -351,19 +348,19 @@ template<class TagStore, class Buffering, class Coherence>
 void
 Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
 {
-    Addr blk_addr = pkt->paddr & ~(Addr(blkSize-1));
+    Addr blk_addr = pkt->addr & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
     if (isTopLevel() && coherence->hasProtocol()) { //@todo Move this into handle bus req
         //If we find an mshr, and it is in service, we need to NACK or invalidate
         if (mshr) {
             if (mshr->inService) {
-                if ((mshr->pkt->cmd.isInvalidate() || !mshr->pkt->isCacheFill())
-                    && (pkt->cmd != Invalidate && pkt->cmd != WriteInvalidate)) {
+                if ((mshr->pkt->isInvalidate() || !mshr->pkt->isCacheFill())
+                    && (pkt->cmd != Packet::InvalidateReq && pkt->cmd != Packet::WriteInvalidateReq)) {
                     //If the outstanding request was an invalidate (upgrade,readex,..)
                     //Then we need to ACK the request until we get the data
                     //Also NACK if the outstanding request is not a cachefill (writeback)
-                    pkt->flags |= NACKED_LINE;
+                    (int)pkt->coherence |= NACKED_LINE;
                     return;
                 }
                 else {
@@ -376,11 +373,11 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
                     //@todo Make it so that a read to a pending read can't be exclusive now.
 
                     //Set the address so find match works
-                    invalidatePkt->paddr = pkt->paddr;
+                    invalidatePkt->addr = pkt->addr;
 
                     //Append the invalidate on
                     missQueue->addTarget(mshr,invalidatePkt);
-                    DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->paddr & (((ULL(1))<<48)-1));
+                    DPRINTF(Cache, "Appending Invalidate to blk_addr: %x\n", pkt->addr & (((ULL(1))<<48)-1));
                     return;
                 }
             }
@@ -388,34 +385,32 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
         //We also need to check the writeback buffers and handle those
         std::vector<MSHR *> writebacks;
         if (missQueue->findWrites(blk_addr, pkt->req->asid, writebacks)) {
-            DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->paddr & (((ULL(1))<<48)-1));
+            DPRINTF(Cache, "Snoop hit in writeback to blk_addr: %x\n", pkt->addr & (((ULL(1))<<48)-1));
 
             //Look through writebacks for any non-uncachable writes, use that
             for (int i=0; i<writebacks.size(); i++) {
                 mshr = writebacks[i];
 
                 if (!mshr->pkt->req->isUncacheable()) {
-                    if (pkt->cmd.isRead()) {
+                    if (pkt->isRead()) {
                         //Only Upgrades don't get here
                         //Supply the data
-                        pkt->flags |= SATISFIED;
+                        (int)pkt->coherence |= SATISFIED;
 
                         //If we are in an exclusive protocol, make it ask again
                         //to get write permissions (upgrade), signal shared
-                        pkt->flags |= SHARED_LINE;
+                        (int)pkt->coherence |= SHARED_LINE;
 
-                        if (doData()) {
-                            assert(pkt->cmd.isRead());
+                        assert(pkt->isRead());
+                        assert(pkt->offset < blkSize);
+                        assert(pkt->size <= blkSize);
+                        assert(pkt->offset + pkt->size <=blkSize);
+                        memcpy(pkt->data, mshr->pkt->data + pkt->offset, pkt->size);
 
-                            assert(pkt->offset < blkSize);
-                            assert(pkt->size <= blkSize);
-                            assert(pkt->offset + pkt->size <=blkSize);
-                            memcpy(pkt->data, mshr->pkt->data + pkt->offset, pkt->size);
-                        }
                         respondToSnoop(pkt);
                     }
 
-                    if (pkt->cmd.isInvalidate()) {
+                    if (pkt->isInvalidate()) {
                         //This must be an upgrade or other cache will take ownership
                         missQueue->markInService(mshr->pkt);
                     }
@@ -439,7 +434,7 @@ void
 Cache<TagStore,Buffering,Coherence>::snoopResponse(Packet * &pkt)
 {
     //Need to handle the response, if NACKED
-    if (pkt->isNacked()) {
+    if ((int)pkt->coherence & NACKED_LINE) {
         //Need to mark it as not in service, and retry for bus
         assert(0); //Yeah, we saw a NACK come through
 
@@ -467,16 +462,16 @@ template<class TagStore, class Buffering, class Coherence>
 Tick
 Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 {
-    MemDebug::cacheProbe(pkt);
+//    MemDebug::cacheProbe(pkt);
 
     if (!pkt->req->isUncacheable()) {
-        if (pkt->cmd.isInvalidate() && !pkt->cmd.isRead()
-            && !pkt->cmd.isWrite()) {
+        if (pkt->isInvalidate() && !pkt->isRead()
+            && !pkt->isWrite()) {
             //Upgrade or Invalidate, satisfy it, don't forward
-            DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmd.toString(),
-                    pkt->req->asid, pkt->paddr & (((ULL(1))<<48)-1),
-                    pkt->paddr & ~((Addr)blkSize - 1));
-            pkt->flags |= SATISFIED;
+            DPRINTF(Cache, "%s %d %x ? blk_addr: %x\n", pkt->cmdString(),
+                    pkt->req->asid, pkt->addr & (((ULL(1))<<48)-1),
+                    pkt->addr & ~((Addr)blkSize - 1));
+            (int)pkt->coherence |= SATISFIED;
             return 0;
         }
     }
@@ -486,13 +481,13 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
         return mi->sendProbe(pkt,update);
     }
 
-    PacketList* writebacks;
+    PacketList writebacks;
     int lat;
     BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
 
     if (!blk) {
         // Need to check for outstanding misses and writes
-        Addr blk_addr = pkt->paddr & ~(blkSize - 1);
+        Addr blk_addr = pkt->addr & ~(blkSize - 1);
 
         // There can only be one matching outstanding miss.
         MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
@@ -513,12 +508,12 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                     Packet * target = *i;
                     // If the target contains data, and it overlaps the
                     // probed request, need to update data
-                    if (target->cmd.isWrite() && target->overlaps(pkt)) {
+                    if (target->isWrite() && target->overlaps(pkt)) {
                         uint8_t* pkt_data;
                         uint8_t* write_data;
                         int data_size;
-                        if (target->paddr < pkt->paddr) {
-                            int offset = pkt->paddr - target->paddr;
+                        if (target->addr < pkt->addr) {
+                            int offset = pkt->addr - target->paddr;
                             pkt_data = pkt->data;
                             write_data = target->data + offset;
                             data_size = target->size - offset;
@@ -526,7 +521,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                             if (data_size > pkt->size)
                                 data_size = pkt->size;
                         } else {
-                            int offset = target->paddr - pkt->paddr;
+                            int offset = target->addr - pkt->addr;
                             pkt_data = pkt->data + offset;
                             write_data = target->data;
                             data_size = pkt->size - offset;
@@ -535,7 +530,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                                 data_size = target->size;
                         }
 
-                        if (pkt->cmd.isWrite()) {
+                        if (pkt->isWrite()) {
                             memcpy(pkt_data, write_data, data_size);
                         } else {
                             memcpy(write_data, pkt_data, data_size);
@@ -550,8 +545,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                     uint8_t* pkt_data;
                     uint8_t* write_data;
                     int data_size;
-                    if (write->paddr < pkt->paddr) {
-                        int offset = pkt->paddr - write->paddr;
+                    if (write->addr < pkt->addr) {
+                        int offset = pkt->addr - write->addr;
                         pkt_data = pkt->data;
                         write_data = write->data + offset;
                         data_size = write->size - offset;
@@ -559,7 +554,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                         if (data_size > pkt->size)
                             data_size = pkt->size;
                     } else {
-                        int offset = write->paddr - pkt->paddr;
+                        int offset = write->addr - pkt->addr;
                         pkt_data = pkt->data + offset;
                         write_data = write->data;
                         data_size = pkt->size - offset;
@@ -568,7 +563,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
                             data_size = write->size;
                     }
 
-                    if (pkt->cmd.isWrite()) {
+                    if (pkt->isWrite()) {
                         memcpy(pkt_data, write_data, data_size);
                     } else {
                         memcpy(write_data, pkt_data, data_size);
@@ -585,8 +580,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
             }
             if (!pkt->req->isUncacheable()) {
                 // Fetch the cache block to fill
-                Packet * busPkt = new MemPkt();
-                busPkt->paddr = blk_addr;
+                Packet * busPkt = new Packet();
+                busPkt->addr = blk_addr;
                 busPkt->size = blkSize;
                 busPkt->data = new uint8_t[blkSize];
 
@@ -632,7 +627,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 
         if (update) {
             hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
-        } else if (pkt->cmd.isWrite()) {
+        } else if (pkt->isWrite()) {
             // Still need to change data in all locations.
             return mi->sendProbe(pkt, update);
         }
@@ -644,9 +639,9 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
 
 template<class TagStore, class Buffering, class Coherence>
 Tick
-Cache<TagStore,Buffering,Coherence>::snoopProbe(MemPktPtr &pkt, bool update)
+Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
 {
-    Addr blk_addr = pkt->paddr & ~(Addr(blkSize-1));
+    Addr blk_addr = pkt->addr & ~(Addr(blkSize-1));
     BlkType *blk = tags->findBlock(pkt);
     MSHR *mshr = missQueue->findMSHR(blk_addr, pkt->req->asid);
     CacheBlk::State new_state = 0;
diff --git a/src/mem/cache/coherence/coherence_protocol.hh b/src/mem/cache/coherence/coherence_protocol.hh
index 4f6520552..21351ace4 100644
--- a/src/mem/cache/coherence/coherence_protocol.hh
+++ b/src/mem/cache/coherence/coherence_protocol.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Erik Hallnor
+ *          Ron Dreslinski
  *          Steve Reinhardt
  */
 
@@ -40,7 +41,6 @@
 
 #include "sim/sim_object.hh"
 #include "mem/packet.hh"
-#include "mem/mem_cmd.hh"
 #include "mem/cache/cache_blk.hh"
 #include "base/statistics.hh"
 
@@ -89,7 +89,7 @@ class CoherenceProtocol : public SimObject
      * @param oldState The current block state.
      * @return The new state.
      */
-    CacheBlk::State getNewState(const Packet * &pkt,
+    CacheBlk::State getNewState(Packet * &pkt,
                                 CacheBlk::State oldState);
 
     /**
diff --git a/src/mem/cache/coherence/simple_coherence.hh b/src/mem/cache/coherence/simple_coherence.hh
index 195674590..ca9d18beb 100644
--- a/src/mem/cache/coherence/simple_coherence.hh
+++ b/src/mem/cache/coherence/simple_coherence.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Erik Hallnor
+ *          Ron Dreslinski
  */
 
 /**
@@ -39,7 +40,6 @@
 #include <string>
 
 #include "mem/packet.hh"
-#include "mem/mem_cmd.hh"
 #include "mem/cache/cache_blk.hh"
 #include "mem/cache/miss/mshr_queue.hh"
 #include "mem/cache/coherence/coherence_protocol.hh"
@@ -119,7 +119,7 @@ class SimpleCoherence
 //Got rid of, there could be an MSHR, but it can't be in service
         if (blk != NULL)
         {
-            if (pkt->cmd != Writeback) {
+            if (pkt->cmd != Packet::Writeback) {
                 return protocol->handleBusRequest(cache, pkt, blk, mshr,
                                               new_state);
             }
@@ -138,7 +138,7 @@ class SimpleCoherence
      */
     Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
     {
-        if (cmd == Writeback) return Writeback;
+        if (cmd == Packet::Writeback) return Packet::Writeback;
         return protocol->getBusCmd(cmd, state);
     }
 
diff --git a/src/mem/cache/coherence/uni_coherence.hh b/src/mem/cache/coherence/uni_coherence.hh
index b64f6c931..4e895997f 100644
--- a/src/mem/cache/coherence/uni_coherence.hh
+++ b/src/mem/cache/coherence/uni_coherence.hh
@@ -34,7 +34,6 @@
 #include "base/trace.hh"
 #include "mem/cache/cache_blk.hh"
 #include "mem/cache/miss/mshr_queue.hh"
-#include "mem/mem_cmd.hh"
 #include "mem/packet.hh"
 
 class BaseCache;
@@ -79,11 +78,11 @@ class UniCoherence
      */
     Packet::Command getBusCmd(Packet::Command &cmd, CacheBlk::State state)
     {
-        if (cmd == Hard_Prefetch && state)
+        if (cmd == Packet::HardPFReq && state)
             warn("Trying to issue a prefetch to a block we already have\n");
-        if (cmd == Writeback)
-            return Writeback;
-        return Read;
+        if (cmd == Packet::Writeback)
+            return Packet::Writeback;
+        return Packet::ReadReq;
     }
 
     /**
@@ -96,7 +95,7 @@ class UniCoherence
     {
         if (pkt->senderState) //Blocking Buffers don't get mshrs
         {
-            if (pkt->senderState->originalCmd == Hard_Prefetch) {
+            if (((MSHR *)(pkt->senderState))->originalCmd == Packet::HardPFReq) {
                 DPRINTF(HWPrefetch, "Marking a hardware prefetch as such in the state\n");
                 return BlkHWPrefetched | BlkValid | BlkWritable;
             }
diff --git a/src/mem/cache/miss/blocking_buffer.hh b/src/mem/cache/miss/blocking_buffer.hh
index 08814b43e..39a06a377 100644
--- a/src/mem/cache/miss/blocking_buffer.hh
+++ b/src/mem/cache/miss/blocking_buffer.hh
@@ -166,7 +166,7 @@ public:
      * has been sent to the bus, this function removes all of its targets.
      * @param req->getThreadNum()ber The thread number of the requests to squash.
      */
-    void squash(int req->getThreadNum()ber);
+    void squash(int threadNum);
 
     /**
      * Return the current number of outstanding misses.
diff --git a/src/mem/cache/miss/miss_queue.hh b/src/mem/cache/miss/miss_queue.hh
index d45982108..b88b7038c 100644
--- a/src/mem/cache/miss/miss_queue.hh
+++ b/src/mem/cache/miss/miss_queue.hh
@@ -270,7 +270,7 @@ class MissQueue
      * has been sent to the bus, this function removes all of its targets.
      * @param req->getThreadNum()ber The thread number of the requests to squash.
      */
-    void squash(int req->getThreadNum()ber);
+    void squash(int threadNum);
 
     /**
      * Return the current number of outstanding misses.
diff --git a/src/mem/cache/miss/mshr_queue.hh b/src/mem/cache/miss/mshr_queue.hh
index 563368d29..a67f1b9a6 100644
--- a/src/mem/cache/miss/mshr_queue.hh
+++ b/src/mem/cache/miss/mshr_queue.hh
@@ -192,7 +192,7 @@ class MSHRQueue {
      * is in service, just squashes the targets.
      * @param req->getThreadNum()ber The thread to squash.
      */
-    void squash(int req->getThreadNum()ber);
+    void squash(int threadNum);
 
     /**
      * Returns true if the pending list is not empty.
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 176c6f793..3d3768676 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -41,10 +41,17 @@
 #include "mem/request.hh"
 #include "arch/isa_traits.hh"
 #include "sim/root.hh"
+#include <list>
 
 struct Packet;
 typedef Packet* PacketPtr;
 typedef uint8_t* PacketDataPtr;
+typedef std::list<PacketPtr> PacketList;
+
+//Coherence Flags
+#define NACKED_LINE 1 << 0
+#define SATISFIED 1 << 1
+#define SHARED_LINE 1 << 2
 
 //For statistics we need max number of commands, hard code it at
 //20 for now.  @todo fix later
@@ -173,7 +180,10 @@ class Packet
         SoftPFReq       = IsRead  | IsRequest | IsSWPrefetch | NeedsResponse,
         HardPFReq       = IsRead  | IsRequest | IsHWPrefetch | NeedsResponse,
         SoftPFResp      = IsRead  | IsRequest | IsSWPrefetch | IsResponse,
-        HardPFResp      = IsRead  | IsRequest | IsHWPrefetch | IsResponse
+        HardPFResp      = IsRead  | IsRequest | IsHWPrefetch | IsResponse,
+        InvalidateReq   = IsInvalidate | IsRequest,
+        WriteInvalidateReq = IsWrite | IsInvalidate | IsRequest,
+        UpgradeReq      = IsInvalidate | NeedsResponse
     };
 
     /** Return the string name of the cmd field (for debugging and
@@ -190,9 +200,14 @@ class Packet
     Command cmd;
 
     bool isRead() 	 { return (cmd & IsRead)  != 0; }
+    bool isWrite()       { return (cmd & IsWrite) != 0; }
     bool isRequest()	 { return (cmd & IsRequest)  != 0; }
     bool isResponse()	 { return (cmd & IsResponse) != 0; }
     bool needsResponse() { return (cmd & NeedsResponse) != 0; }
+    bool isInvalidate()  { return (cmd * IsInvalidate) != 0; }
+
+    bool isCacheFill() { assert("Unimplemented yet\n" && 0); }
+    bool isNoAllocate() { assert("Unimplemented yet\n" && 0); }
 
     /** Possible results of a packet's request. */
     enum Result
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 469184b13..46d9b6fd7 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -44,6 +44,7 @@ class Request;
 
 typedef Request* RequestPtr;
 
+
 /** The request is a Load locked/store conditional. */
 const unsigned LOCKED		= 0x001;
 /** The virtual address is also the physical address. */