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authorGabe Black <gblack@eecs.umich.edu>2008-10-11 15:14:37 -0700
committerGabe Black <gblack@eecs.umich.edu>2008-10-11 15:14:37 -0700
commit526933e5d03f5d7963bc5a244294ddbb068c4770 (patch)
tree024299f029be90c97c2f811dd57693f023e29228 /src
parentf621b7b81f0913612381d5dc4993f52bb2116902 (diff)
downloadgem5-526933e5d03f5d7963bc5a244294ddbb068c4770.tar.xz
X86: Add an Intel MP table to the simulation.
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/bios/IntelMP.py9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/bios/IntelMP.py b/src/arch/x86/bios/IntelMP.py
index 70e7963fa..758932180 100644
--- a/src/arch/x86/bios/IntelMP.py
+++ b/src/arch/x86/bios/IntelMP.py
@@ -86,6 +86,15 @@ class X86IntelMPConfigTable(SimObject):
ext_entries = VectorParam.X86IntelMPExtConfigEntry([],
'extended configuration table entries')
+ def add_entry(self, entry):
+ if isinstance(entry, X86IntelMPBaseConfigEntry):
+ self.base_entries.append(entry)
+ elif isinstance(entry, X86IntelMPExtConfigEntry):
+ self.base_entries.append(entry)
+ else:
+ panic("Don't know what type of Intel MP entry %s is." \
+ % entry.__class__.__name__)
+
class X86IntelMPBaseConfigEntry(SimObject):
type = 'X86IntelMPBaseConfigEntry'
cxx_class = 'X86ISA::IntelMP::BaseConfigEntry'