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authorAli Saidi <saidi@eecs.umich.edu>2007-01-31 18:32:27 -0500
committerAli Saidi <saidi@eecs.umich.edu>2007-01-31 18:32:27 -0500
commit5c7192daedcd33d9f7deb42406002adf4f2ffb68 (patch)
tree6d0cf97f10eda6dfda23d5e5b10e31e0bbe1aa66 /src
parent36a1912bf01433acc86837ed60da6d510323aa1e (diff)
downloadgem5-5c7192daedcd33d9f7deb42406002adf4f2ffb68.tar.xz
make sparc fs less chatty
src/SConscript: strip doesn't take a src and dest in solaris --HG-- extra : convert_revision : 57f95eda0e3232475a5b55753ace3f3f0fced8b3
Diffstat (limited to 'src')
-rw-r--r--src/SConscript5
-rw-r--r--src/arch/sparc/tlb.cc1
-rw-r--r--src/python/m5/objects/T1000.py52
3 files changed, 30 insertions, 28 deletions
diff --git a/src/SConscript b/src/SConscript
index 2a61100c1..74bed9a7e 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -304,7 +304,10 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
newEnv.Program(bin, make_objs(sources, newEnv))
if strip:
stripped_bin = bin + '.stripped'
- newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
+ if sys.platform == 'sunos5':
+ newEnv.Command(stripped_bin, bin, 'cp $SOURCE $TARGET; strip $TARGET')
+ else:
+ newEnv.Command(stripped_bin, bin, 'strip $SOURCE -o $TARGET')
bin = stripped_bin
targets = newEnv.Concat(exe, [bin, 'python/m5py.zip'])
newEnv.M5Binary = targets[0]
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 32e172957..ebc8c0e7a 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -899,7 +899,6 @@ DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
break;
case ASI_SPARC_ERROR_STATUS_REG:
- warn("returning 0 for SPARC ERROR regsiter read\n");
pkt->set((uint64_t)0);
break;
case ASI_HYP_SCRATCHPAD:
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 7b93268ac..85c4db6df 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -21,53 +21,53 @@ class T1000(Platform):
type = 'T1000'
system = Param.System(Parent.any, "system")
- fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000,
- warn_access="Accessing Clock Unit -- Unimplemented!")
+ fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
+ #warn_access="Accessing Clock Unit -- Unimplemented!")
fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
- ret_data64=0x0000000000000000, update_data=False,
- warn_access="Accessing Memory Banks -- Unimplemented!")
+ ret_data64=0x0000000000000000, update_data=False)
+ #warn_access="Accessing Memory Banks -- Unimplemented!")
- fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000,
- warn_access="Accessing IOB -- Unimplemented!")
+ fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000)
+ #warn_access="Accessing IOB -- Unimplemented!")
- fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000,
- warn_access="Accessing JBI -- Unimplemented!")
+ fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
+ #warn_access="Accessing JBI -- Unimplemented!")
fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True,
- warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000001, update_data=True)
+ #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True,
- warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000001, update_data=True)
+ #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True,
- warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000001, update_data=True)
+ #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True,
- warn_access="Accessing L2 Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000001, update_data=True)
+ #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True,
- warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000000, update_data=True)
+ #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True,
- warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000000, update_data=True)
+ #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True,
- warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000000, update_data=True)
+ #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True,
- warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
+ ret_data64=0x0000000000000000, update_data=True)
+ #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
- fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000,
- warn_access="Accessing SSI -- Unimplemented!")
+ fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
+ #warn_access="Accessing SSI -- Unimplemented!")
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()