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authorKevin Lim <ktlim@umich.edu>2006-07-27 16:43:02 -0400
committerKevin Lim <ktlim@umich.edu>2006-07-27 16:43:02 -0400
commit64b72130463f217bc2ce3e592630406e9f832d16 (patch)
tree4576e05f9f2e9305bfafbd6e212a403754f434b7 /src
parentf9729e999f71895f6b53f8189bdff535e7c7b70e (diff)
downloadgem5-64b72130463f217bc2ce3e592630406e9f832d16.tar.xz
Need config read/write latency.
--HG-- extra : convert_revision : 2d978635db89e727f228890738b24fcad9b6ced6
Diffstat (limited to 'src')
-rw-r--r--src/dev/ide_ctrl.cc3
-rw-r--r--src/dev/ns_gige.cc3
-rw-r--r--src/dev/sinic.cc3
-rw-r--r--src/python/m5/objects/Ethernet.py2
-rw-r--r--src/python/m5/objects/Ide.py2
5 files changed, 13 insertions, 0 deletions
diff --git a/src/dev/ide_ctrl.cc b/src/dev/ide_ctrl.cc
index 5ffc02d34..e8d7f4817 100644
--- a/src/dev/ide_ctrl.cc
+++ b/src/dev/ide_ctrl.cc
@@ -756,6 +756,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
SimObjectVectorParam<IdeDisk *> disks;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
@@ -769,6 +770,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(disks, "IDE disks attached to this controller")
END_INIT_SIM_OBJECT_PARAMS(IdeController)
@@ -784,6 +786,7 @@ CREATE_SIM_OBJECT(IdeController)
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->disks = disks;
return new IdeController(params);
}
diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc
index bf2279d93..704afcf7d 100644
--- a/src/dev/ns_gige.cc
+++ b/src/dev/ns_gige.cc
@@ -2815,6 +2815,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
Param<Tick> clock;
Param<bool> dma_desc_free;
@@ -2848,6 +2849,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(clock, "State machine cycle time"),
INIT_PARAM(dma_desc_free, "DMA of Descriptors is free"),
@@ -2885,6 +2887,7 @@ CREATE_SIM_OBJECT(NSGigE)
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->clock = clock;
params->dma_desc_free = dma_desc_free;
diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc
index 815cecca5..40bf29c87 100644
--- a/src/dev/sinic.cc
+++ b/src/dev/sinic.cc
@@ -1639,6 +1639,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
+ Param<Tick> config_latency;
Param<Tick> intr_delay;
Param<Tick> clock;
@@ -1681,6 +1682,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
+ INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(clock, "State machine cycle time"),
@@ -1725,6 +1727,7 @@ CREATE_SIM_OBJECT(Device)
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
+ params->config_delay = config_latency;
params->intr_delay = intr_delay;
params->clock = clock;
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index db7efe004..fb641bf80 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -68,6 +68,8 @@ class EtherDevBase(PciDevice):
clock = Param.Clock('0ns', "State machine processor frequency")
+ config_latency = Param.Latency('20ns', "Config read or write latency")
+
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index a5fe1b595..a8bd4ac5a 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -36,4 +36,6 @@ class IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+ config_latency = Param.Latency('20ns', "Config read or write latency")
+
configdata =IdeControllerPciData()