diff options
author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-09-25 11:49:40 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2012-09-25 11:49:40 -0500 |
commit | 6598241f2c188ba6f4ce035d9e1fbdd4619c7e00 (patch) | |
tree | a9785f2f7fd62f92916eb8f3900ad0427b96396d /src | |
parent | 5f32eceeda92f45d253a0835c6643e786a91ba49 (diff) | |
download | gem5-6598241f2c188ba6f4ce035d9e1fbdd4619c7e00.tar.xz |
sim: Move CPU-specific methods from SimObject to the BaseCPU class
Diffstat (limited to 'src')
-rw-r--r-- | src/cpu/BaseCPU.py | 16 | ||||
-rw-r--r-- | src/cpu/base.hh | 24 | ||||
-rw-r--r-- | src/python/m5/SimObject.py | 5 | ||||
-rw-r--r-- | src/python/m5/simulate.py | 2 | ||||
-rw-r--r-- | src/sim/sim_object.cc | 13 | ||||
-rw-r--r-- | src/sim/sim_object.hh | 23 |
6 files changed, 36 insertions, 47 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index c27fd1c27..6e5f6ff1a 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -77,6 +77,22 @@ class BaseCPU(MemObject): type = 'BaseCPU' abstract = True + @classmethod + def export_method_cxx_predecls(cls, code): + code('#include "cpu/base.hh"') + + + @classmethod + def export_methods(cls, code): + code(''' + void switchOut(); + void takeOverFrom(BaseCPU *cpu); +''') + + def takeOverFrom(self, old_cpu): + self._ccObject.takeOverFrom(old_cpu._ccObject) + + system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") numThreads = Param.Unsigned(1, "number of HW thread contexts") diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 82864ae7b..0c1d19856 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -278,13 +278,27 @@ class BaseCPU : public MemObject void registerThreadContexts(); - /// Prepare for another CPU to take over execution. When it is - /// is ready (drained pipe) it signals the sampler. + /** + * Prepare for another CPU to take over execution. + * + * When this method exits, all internal state should have been + * flushed. After the method returns, the simulator calls + * takeOverFrom() on the new CPU with this CPU as its parameter. + */ virtual void switchOut(); - /// Take over execution from the given CPU. Used for warm-up and - /// sampling. - virtual void takeOverFrom(BaseCPU *); + /** + * Load the state of a CPU from the previous CPU object, invoked + * on all new CPUs that are about to be switched in. + * + * A CPU model implementing this method is expected to initialize + * its state from the old CPU and connect its memory (unless they + * are already connected) to the memories connected to the old + * CPU. + * + * @param cpu CPU to initialize read state from. + */ + virtual void takeOverFrom(BaseCPU *cpu); /** * Number of threads we're actually simulating (<= SMT_MAX_THREADS). diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index c8227c067..b63aa22d5 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -602,8 +602,6 @@ class SimObject(object): unsigned int drain(Event *drain_event); void resume(); - void switchOut(); - void takeOverFrom(BaseCPU *cpu); ''') # Initialize new instance. For objects with SimObject-valued @@ -1050,9 +1048,6 @@ class SimObject(object): for portRef in self._port_refs.itervalues(): portRef.ccConnect() - def takeOverFrom(self, old_cpu): - self._ccObject.takeOverFrom(old_cpu._ccObject) - # Function to provide to C++ so it can look up instances based on paths def resolveSimObject(name): obj = instanceDict[name] diff --git a/src/python/m5/simulate.py b/src/python/m5/simulate.py index 17150cd4f..e95136548 100644 --- a/src/python/m5/simulate.py +++ b/src/python/m5/simulate.py @@ -221,7 +221,7 @@ def switchCpus(cpuList): # Now all of the CPUs are ready to be switched out for old_cpu, new_cpu in cpuList: - old_cpu._ccObject.switchOut() + old_cpu.switchOut() for old_cpu, new_cpu in cpuList: new_cpu.takeOverFrom(old_cpu) diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc index 866ce0ce2..32e936ff2 100644 --- a/src/sim/sim_object.cc +++ b/src/sim/sim_object.cc @@ -163,19 +163,6 @@ SimObject::resume() state = Running; } -void -SimObject::switchOut() -{ - panic("Unimplemented!"); -} - -void -SimObject::takeOverFrom(BaseCPU *cpu) -{ - panic("Unimplemented!"); -} - - SimObject * SimObject::find(const char *name) { diff --git a/src/sim/sim_object.hh b/src/sim/sim_object.hh index 4fa2b7f05..c1238e23f 100644 --- a/src/sim/sim_object.hh +++ b/src/sim/sim_object.hh @@ -255,29 +255,6 @@ class SimObject : public EventManager, public Serializable */ virtual void resume(); - /** - * Prepare a CPU model to be switched out, invoked on active CPUs - * that are about to be replaced. - * - * @note This should only be implemented in CPU models. - */ - virtual void switchOut(); - - /** - * Load the state of a CPU from the previous CPU object, invoked - * on all new CPUs that are about to be switched in. - * - * A CPU model implementing this method is expected to initialize - * its state from the old CPU and connect its memory (unless they - * are already connected) to the memories connected to the old - * CPU. - * - * @note This should only be implemented in CPU models. - * - * @param cpu CPU to initialize read state from. - */ - virtual void takeOverFrom(BaseCPU *cpu); - #ifdef DEBUG public: bool doDebugBreak; |