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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:05 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:05 -0600
commit776c07591797ccd103619de111ec27df04f96bb3 (patch)
tree1f64e61079588d55d510311f26e421d877b3580b /src
parent5f59e195d61c9144c817aab4a9179036adad6c9c (diff)
downloadgem5-776c07591797ccd103619de111ec27df04f96bb3.tar.xz
O3: reset architetural state by calling clear()
Diffstat (limited to 'src')
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 367442830..060baed32 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2004-2006 The Regents of The University of Michigan
* All rights reserved.
*
@@ -257,7 +269,9 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
template <class Impl>
void
O3ThreadContext<Impl>::clearArchRegs()
-{}
+{
+ cpu->isa[thread->threadId()].clear();
+}
template <class Impl>
uint64_t